Intel CORE 2 DUO E7000 - UPDATE 7-2010 User manual

Intel®Core™2 Duo Processor
E8000Δand E7000ΔSeries
Specification Update
— on 45 nm Process in the 775-land LGA Package
July 2010
Notice: The Intel® CoreTM2 Duo processor may contain design defects or errors known as
errata which may cause the product to deviate from published specifications. Current
characterized errata are documented in this Specification Update.
Document Number: 318733-018

2 Intel® Core™2 Duo Processor
Specification Update
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Φ Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications
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Copyright © 2008 - 2010, Intel Corporation. All rights reserved.

Intel® Core™2 Duo Processor
Specification Update 3
Contents
Contents ............................................................................................................................... 3
Revision History..................................................................................................................... 4
Preface ................................................................................................................................. 6
Summary Tables of Changes ................................................................................................... 8
Identification Information ...................................................................................................... 14
Component Identification Information ..................................................................................... 15
Errata.................................................................................................................................. 18
Specification Changes ........................................................................................................... 48
Specification Clarifications ..................................................................................................... 49
Documentation Changes ........................................................................................................ 50
§

4 Intel® Core™2 Duo Processor
Specification Update
Revision History
Revision
Number Description Date
001 Initial release of Intel®Core™2 Duo Desktop Processor E8000
Series Specification Update Jan 7th 2008
002 •Added Erratum AW51 Feb 1st 2008
003 •Added Errata AW52 to AW54 Feb 13th 2008
004 •Changed document title to include E7000 series
•Included E7200 and E8300 processor information April 20th 2008
005
•Included M0 stepping information
•Added new errata AW55-AW57
•Added Spec Clarification AW1
May 14th 2008
006
•Updated Erratum AW18
•Deleted Erratum AW53 and replaced with a new erratum
•Added Errata AW58-AW60
Jul 16th 2008
007
•Included E7300 processor on M0 stepping
•Included E8600 processor on E0 stepping
•Included E0 stepping information
•Added new Errata AW61-AW70
Aug 10th 2008
008 •Included E8400 and E8500 processor on E0 stepping
•Added Errata AW71-AW74 Sept 10th 2008
009 •Added E7400 information Oct 20th 2008
010 •Updated Erratum AW35 Nov 12th 2008
011 •Added Erratum AW75 Dec 17th 2008
012 •Updated Erratum AW72
•Added E7500 processor information Jan 19th 2009
013 •Corrected the Errata ID numbers for Errata AW58 to AW63 to
align with the errata description Feb 11th 2009
014 •Updated Erratum AW1 Mar 11th 2009
015 •Added Erratum AW76 May 13th 2009
016 •Added E7600 processor information June 3rd 2009

Intel® Core™2 Duo Processor
Specification Update 5
Revision
Number Description Date
017 •Added Errata AW77 and AW78 July 15th 2009
018 •Added Errata AW79 March 16th, 2010
019 •Added Errata AW80
•Removed Item Numbering Section July 19th, 2010

Preface
6 Intel® Core™2 Duo Processor
Specification Update
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents/Related Documents table. It is a compilation of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
Document Title Document Number
Intel®Core™2 Duo Processor E8000 and E7000 Series Datasheet 318732
Rev 006
Related Documents
Document Title Document Location
Intel®64 and IA-32 Architectures Software Developer’s
Manual Volume 1: Basic Architecture
http://www.intel.com/produc
ts/processor/manuals/index.
htm
Intel®64 and IA-32 Architectures Software Developer’s
Manual Volume 2A: Instruction Set Reference Manual A–M
Intel®64 and IA-32 Architectures Software Developer’s
Manual Volume 2B: Instruction Set Reference Manual, N–Z
Intel®64 and IA-32 Architectures Software Developer’s
Manual Volume 3A: System Programming Guide
Intel®64 and IA-32 Architectures Software Developer’s
Manual Volume 3B: System Programming Guide

Preface
Intel® Core™2 Duo Processor
Specification Update 7
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics (e.g., core speed, L2 cache size, package
type, etc.) as described in the processor identification information table. Care should
be taken to read all notes associated with each S-Spec number
QDF Number is a several digit code that is used to distinguish between engineering
samples. These processors are used for qualification and early design validation. The
functionality of these parts can range from mechanical only to fully functional. The
NDA specification update has a processor identification information table that lists
these QDF numbers and the corresponding product sample details.
Errata are design defects or errors. Errata may cause the processor’s behavior to
deviate from published specifications. Hardware and software designed to be used
with any given stepping must assume that all errata documented for that stepping are
present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in the next release of the specifications.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon
request. Specification changes, specification clarifications and documentation changes
are removed from the specification update when the appropriate changes are made to
the appropriate product specification or user documentation (datasheets, manuals,
etc.).
§

Summary Tables of Changes
8 Intel® Core™2 Duo Processor
Specification Update
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed MCH steppings.
Intel intends to fix some of the errata in a future stepping of the component, and to
account for the other outstanding issues through documentation or Specification
Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that applies
to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Shaded: This item is either new or modified from the previous
version of the document.

Summary Tables of Changes
Intel® Core™2 Duo Processor
Specification Update 9
The Specification Updates for the Pentium® processor, Pentium® Pro processor, and
other Intel products do not use this convention.
NO C0 M0 E0 R0 Plan ERRATA
AW1 X X X X No Fix EFLAGS Discrepancy on Page Faults after a Translation
Change
AW2 X X X X No Fix INVLPG Operation for Large (2M/4M) Pages May be
Incomplete under Certain Conditions
AW3 X X X X No Fix Store to WT Memory Data May be Seen in Wrong Order by
Two Subsequent Loads
AW4 X X X X No Fix Non-Temporal Data Store May be Observed in Wrong
Program Order
AW5 X X X X No Fix Page Access Bit May be Set Prior to Signaling a Code
Segment Limit Fault
AW6 X X X X No Fix Updating Code Page Directory Attributes without TLB
Invalidation May Result in Improper Handling of Code #PF
AW7 X X X X No Fix Storage of PEBS Record Delayed Following Execution of
MOV SS or STI
AW8 X X X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX
May Not Count Some Transitions
AW9 X X X X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range
May Prevent Triggering of the Monitoring Hardware
AW10 X X X X No Fix Performance Monitoring Event MISALIGN_MEM_REF May
Over Count
AW11 X X X X No Fix The Processor May Report a #TS Instead of a #GP Fault
AW12 X X X X No Fix Code Segment limit violation may occur on 4 Gigabyte limit
check
AW13 X X X X No Fix A Write to an APIC Register Sometimes May Appear to
Have Not Occurred
AW14 X X X X No Fix Last Branch Records (LBR) Updates May be Incorrect after
a Task Switch
AW15 X X X X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types
may use an Incorrect Data Size or Lead to Memory-
Ordering Violations
AW16 X X X X No Fix Upper 32 bits of ‘From’ Address Reported through BTMs or
BTSs May be Incorrect
AW17 X X X X No Fix Address Reported by Machine-Check Architecture (MCA) on
Single-bit L2 ECC Errors May be Incorrect
AW18 X X X X No Fix
Code Segment Limit/Canonical Faults on RSM May be
Serviced before Higher Priority Interrupts/Exceptions and
May Push the Wrong Address Onto the Stack
AW19 X X X X No Fix Store Ordering May be Incorrect between WC and WP
Memory Types

Summary Tables of Changes
10 Intel® Core™2 Duo Processor
Specification Update
NO C0 M0 E0 R0 Plan ERRATA
AW20 X X X X No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect
after Shutdown
AW21 X X X X No Fix Premature Execution of a Load Operation Prior to Exception
Handler Invocation
AW22 X X X X No Fix Performance Monitoring Events for Retired Instructions
(C0H) May Not Be Accurate
AW23 X X X X No Fix Returning to Real Mode from SMM with EFLAGS.VM Set
May Result in Unpredictable System Behavior
AW24 X X X X No Fix CMPSB, LODSB, or SCASB in 64-bit Mode with Count
Greater or Equal to 248 May Terminate Early
AW25 X X X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is
Pending May Cause an Unexpected Interrupt
AW26 X X X X No Fix Pending x87 FPU Exceptions (#MF) Following STI May Be
Serviced Before Higher Priority Interrupts
AW27 X X X X No Fix VERW/VERR/LSL/LAR Instructions May Unexpectedly
Update the Last Exception Record (LER) MSR
AW28 X X X X No Fix INIT Does Not Clear Global Entries in the TLB
AW29 X X X X No Fix Split Locked Stores May not Trigger the Monitoring
Hardware
AW30 X X X X No Fix Programming the Digital Thermal Sensor (DTS) Threshold
May Cause Unexpected Thermal Interrupts
AW31 X X X X No Fix
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a
Memory Ordering Issue
AW32 X X X X No Fix General Protection (#GP) Fault May Not Be Signaled on
Data Segment Limit Violation above 4-G Limit
AW33 X X X X No Fix An Asynchronous MCE During a Far Transfer May Corrupt
ESP
AW34 X X X X Plan Fix
CPUID Reports Architectural Performance
Monitoring Version 2 is Supported, When Only Version 1
Capabilities are Available
AW35 X X X X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code
Breakpoint
AW36 X X X X No Fix
An xTPR Update Transaction Cycle, if Enabled, May be
Issued to the FSB after the Processor has Issued a Stop-
Grant Special Cycle
AW37 X X Fixed
Performance Monitoring Event IA32_FIXED_CTR2 May Not
Function Properly when Max Ratio is a Non-Integer Core-
to-Bus Ratio
AW38 X X X X No Fix Instruction Fetch May Cause a Livelock During Snoops of
the L1 Data Cache
AW39 X X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type
may Cause a System Hang or a Machine Check Exception

Summary Tables of Changes
Intel® Core™2 Duo Processor
Specification Update 11
NO C0 M0 E0 R0 Plan ERRATA
AW40 X X X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May
Lead to Memory-Ordering Violations
AW41 X Fixed
VM Exit with Exit Reason “TPR Below Threshold” Can Cause
the Blocking by MOV/POP SS and Blocking by STI Bits to be
Cleared in the Guest Interruptibility-State Field
AW42 X X X X No Fix Using Memory Type Aliasing with cacheable and WC
Memory Types May Lead to Memory Ordering Violations
AW43 X X No Fix VM Exit Caused by a SIPI Results in Zero to be Saved to
the Guest RIP Field in the VMCS
AW44 X X Fixed NMIs May Not Be Blocked by a VM-Entry Failure
AW45 X X Fixed Partial Streaming Load Instruction Sequence May Cause
the Processor to Hang
AW46 X X Fixed Self/Cross Modifying Code May Not be Detected or May
Cause a Machine Check Exception
AW47 X X Fixed Data TLB Eviction Condition in the Middle of a Cacheline
Split Load Operation May Cause the Processor to Hang
AW48 X X Fixed
Update of Read/Write (R/W) or User/Supervisor (U/S) or
Present (P) Bits without TLB Shootdown May Cause
Unexpected Processor Behavior
AW49 X X Fixed
RSM Instruction Execution under Certain Conditions May
Cause Processor Hang or Unexpected Instruction Execution
Results
AW50 X X X X No Fix Benign Exception after a Double Fault May Not Cause a
Triple Fault Shutdown
AW51 X X X X Plan Fix Short Nested Loops That Span Multiple 16-Byte Boundaries
May Cause a Machine Check Exception or a System Hang
AW52 X X X X No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be
Taken after MOV SS/POP SS Instruction if it is Followed by
an Instruction That Signals a Floating Point Exception
AW53 X X X X No Fix LER MSRs May be Incorrectly Updated
AW54 X X X X No Fix IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine
Check Error Reporting Enable Correctly
AW55 X X No Fix A VM Exit Due to a Fault While Delivering a Software
Interrupt May Save Incorrect Data into the VMCS
AW56 X X No Fix A VM Exit Occuring in IA-32e Mode May Not Produce a VMX
Abort When Expected
AW57 X X X X No Fix IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception
AW58 X X X X Plan Fix PSI# Signal Asserted During Reset
AW59 X X X X No Fix Thermal Interrupts are Dropped During and While Exiting
Intel® Deep Power-Down State
AW60 X X X X No Fix VM Entry May Fail When Attempting to Set
IA32_DEBUGCTL.FREEZE_WHILE_SMM_EN

Summary Tables of Changes
12 Intel® Core™2 Duo Processor
Specification Update
NO C0 M0 E0 R0 Plan ERRATA
AW61 X X No Fix Processor May Hold-off / Delay a PECI Transaction Longer
than Specified by the PECI Protocol
AW62 X No Fix VM Entry May Use Wrong Address to Access Virtual-APIC
Page
AW63 X X No Fix XRSTOR Instruction May Cause Extra Memory Reads
AW64 X X Plan Fix CPUID Instruction May Return Incorrect Brand String
AW65 X No Fix Global Instruction TLB Entries May Not be Invalidated on a
VM Exit or VM Entry
AW66 X X No Fix When Intel® Deep Power-Down State is Being Used,
IA32_FIXED_CTR2 May Return Incorrect Cycle Counts
AW67 X X No Fix Enabling PECI via the PECI_CTL MSR incorrectly
writes CPUID_FEATURE_MASK1 MSR
AW68 X X No Fix INIT Incorrectly Resets IA32_LSTAR MSR
AW69 X X X X No Fix Corruption of CS Segment Register During RSM While
Transitioning From Real Mode to Protected Mode
AW70 X X X X No Fix LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
AW71 X X No Fix The XRSTOR Instruction May Fail to Cause a General-
Protection Exception
AW72 X X No Fix The XSAVE Instruction May Erroneously Set Reserved Bits
in the XSTATE_BV Field
AW73 X X No Fix Store Ordering Violation When Using XSAVE
AW74 X X X X No Fix Memory Ordering Violation With Stores/Loads Crossing a
Cacheline Boundary
AW75 X X Plan Fix Unsynchronized Cross-Modifying Code Operations Can
Cause Unexpected Instruction Execution Results
AW76 X X X X No Fix A Page Fault May Not be Generated When the PS bit is set
to “1” in a PML4E or PDPTE
AW77 X X X X No Fix Not-Present Page Faults May Set the RSVD Flag in the
Error Code
AW78 X X X X No Fix VM Exits Due to “NMI-Window Exiting” May Be Delayed by
One Instruction
AW79 X X X X No Fix
FP Data Operand Pointer May Be Incorrectly Calculated
After an FP Access Which Wraps a 4-Gbyte Boundary in
Code That Uses 32-Bit Address Size in 64-bit Mode
AW80 X X No Fix VM Entry May Overwrite the Value for the IA32_DEBUGCTL
MSR Specified in the VM-Entry MSR-Load Area
Number SPECIFICATION CHANGES
- There are no Specification Changes in this Specification Update revision.

Summary Tables of Changes
Intel® Core™2 Duo Processor
Specification Update 13
Number SPECIFICATION CLARIFICATIONS
AW1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation
Number DOCUMENTATION CHANGES
- There are no Documentation Changes in this Specification Update revision.
§

Identification Information
14 Intel® Core™2 Duo Processor
Specification Update
Identification Information
Figure 1. Processor Package Example
§

Component Identification Information
Intel® Core™2 Duo Processor
Specification Update 15
Component Identification
Information
The Intel® Core™2 duo processor can be identified by the following values:
Reserve
d Extended Family1Extended Model2Reserved Processor Type3Family Code4Model Number5Stepping ID6
31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0
00000000b 0001b 00b 0110b 0111b XXXXb
When EAX is initialized to a value of 1, the CPUID instruction returns the Extended
Family, Extended Model, Type, Family, Model and Stepping value in the EAX register.
Note that the EDX processor signature value after reset is equivalent to the processor
signature output value in the EAX register.
NOTES:
1. The Extended Family, bits [27:20] are used in conjunction with the Family Code,
specified in bits [11:8], to indicate whether the processor belongs to the Intel386,
Intel486, Pentium, Pentium Pro, Pentium 4, Intel® CoreTM, or Enhanced Intel® CoreTM
processor family.
2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits
[7:4], are used to identify the model of the processor within the processor’s family.
3. The Processor Type, specified in bits [13:12] indicates whether the processor is an
original OEM processor, an OverDrive processor, or a dual processor (capable of being
used in a dual processor system).
4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8]
of the EAX register after the CPUID instruction is executed with a 1 in the EAX register,
and the generation field of the Device ID register accessible through Boundary Scan.
5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4]
of the EAX register after the CPUID instruction is executed with a 1 in the EAX register,
and the model field of the Device ID register accessible through Boundary Scan.
6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Error!
Reference source not found. for the processor stepping ID number in the CPUID
information.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after
the CPUID instruction is executed with a 2 in the EAX register. Refer to the Intel Processor
Identification and the CPUID Instruction Application Note (AP-485) and the Wolfdale Family
Processor Family BIOS Writer’s Guide (BWG) for further information on the CPUID instruction.

Component Identification Information
16 Intel® Core™2 Duo Processor
Specification Update
Table 1. Intel®Core™2 Duo Processor Identification Information
S-Spec Core
Stepping L2 Cache
Size
(bytes) Processor
Signature Processor Number Speed Core/Bus Package Notes
SLAPC M0 3 MB 10676h E7200 2.53 GHz /
1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14
SLAVN M0 3 MB 10676h E7200 2.53 GHz /
1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13
SLAVP M0 3 MB 10676h E7300 2.66 GHz /
1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13
SLAPB M0 3 MB 10676h E7300 2.66 GHz /
1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14
SLAQR C0 6 MB
(2 x 3MB) 10676h E8190 2.66 GHz / 1333 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13
SLAPP C0 6 MB
(2 x 3MB) 10676h E8200 2.66 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
SLAPN C0 6 MB
(2 x 3MB) 10676h E8300 2.83 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
SLAPL C0 6 MB
(2 x 3MB) 10676h E8400 3.00 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
SLAPK C0 6 MB
(2 x 3MB) 10676h E8500 3.16 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
SLB9Y R0 3 MB 1067Ah E7400 2.80 GHz /
1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13
SLGW3 R0 3 MB 1067Ah E7400 2.80 GHz /
1066 MHz 775-land LGA 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13
SLB9Z R0 3 MB 1067Ah E7500 2.93 GHz /
1066 MHz 775-land LGA 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13
SLGTD R0 3 MB 1067Ah E7600 3.06 GHz /
1066 MHz 775-land LGA 1, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13
SLB9J E0 6 MB
(2 x 3MB) 1067Ah E8400 3.00 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
SLB9K E0 6 MB
(2 x 3MB) 1067Ah E8500 3.16 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
SLB9L E0 6 MB
(2 x 3MB) 1067Ah E8600 3.33 GHz / 1333 MHz 775-land LGA 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13
NOTES:
1. These processors support the 775_VR_CONFIG_06 specifications
2. These parts support Intel® 64
3. These parts support Execute Disable Bit Feature
4. These parts support Intel® Virtualization Technology (Intel® VT)
5. These parts have Intel® Trusted Execution Technology (Intel® TXT) enabled
6. These parts have PROCHOT# enabled

Component Identification Information
Intel® Core™2 Duo Processor
Specification Update 17
7. These parts have THERMTRIP# enabled
8. These parts support Thermal Monitor 2 (TM2) feature
9. These parts have PECI enabled
10.These parts have Enhanced Intel SpeedStep® Technology (EIST) enabled
11.These parts have Extended HALT State (C1E) enabled
12.These parts have Extended Stop Grant State (C2E) enabled.
13.These parts have Deeper Sleep State (C4E) enabled
14.These parts do not have LGA cover

Errata
18 Intel® Core™2 Duo Processor
Specification Update
Errata
AW1. EFLAGS Discrepancy on Page Faults after a Translation Change
Problem: This erratum is regarding the case where paging structures are modified to
change a linear address from writable to non-writable without software
performing an appropriate TLB invalidation. When a subsequent access to
that address by a specific instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG,
DEC, INC, NEG, NOT, OR, ROL/ROR, SAL/SAR/SHL/SHR, SHLD, SHRD, SUB,
XOR, and XADD) causes a page fault, the value saved for EFLAGS may
incorrectly contain the arithmetic flag values that the EFLAGS register would
have held had the instruction completed without fault. This can occur even if
the fault causes a VM exit or if its delivery causes a nested fault.
Implication: None identified. Although the EFLAGS value saved may contain incorrect
arithmetic flag values, Intel has not identified software that is affected by this
erratum. This erratum will have no further effects once the original instruction
is restarted because the instruction will produce the same results as if it had
initially completed without a page fault.
Workaround: If the page fault handler inspects the arithmetic portion of the saved EFLAGS
value, then system software should perform a synchronized paging structure
modification and TLB invalidation.
Status: For the steppings affected, see the Summary Tables of Changes.
AW2. INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain
Conditions
Problem: The INVLPG instruction may not completely invalidate Translation Look-aside
Buffer (TLB) entries for large pages (2M/4M) when both of the following
conditions exist:
•Address range of the page being invalidated spans several Memory
Type Range Registers (MTRRs) with different memory types specified
•INVLPG operation is preceded by a Page Assist Event (Page Fault (#PF) or an
access that results in either A or D bits being set in a Page Table Entry (PTE))
Implication: Stale translations may remain valid in TLB after a PTE update resulting in
unpredictable system behavior. Intel has not observed this erratum with any
commercially available software.
Workaround: Software should ensure that the memory type specified in the MTRRs is the
same for the entire address range of the large page.
Status: For the steppings affected, see the Summary Tables of Changes.

Errata
Intel® Core™2 Duo Processor
Specification Update 19
AW3. Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
Problem: When data of Store to WT memory is used by two subsequent loads of one
thread and another thread performs cacheable write to the same address the
first load may get the data from external memory or L2 written by another
core, while the second load will get the data straight from the WT Store.
Implication: Software that uses WB to WT memory aliasing may violate proper store
ordering.
Workaround: Do not use WB to WT aliasing.
Status: For the steppings affected, see the Summary Tables of Changes.
AW4. Non-Temporal Data Store May be Observed in Wrong Program Order
Problem: When non-temporal data is accessed by multiple read operations in one
thread while another thread performs a cacheable write operation to the same
address, the data stored may be observed in wrong program order (i.e. later
load operations may read older data).
Implication: Software that uses non-temporal data without proper serialization before
accessing the non-temporal data may observe data in wrong program order.
Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 3A, section “Buffering of Write Combining
Memory Locations” will operate correctly.
Status: For the steppings affected, see the Summary Tables of Changes.
AW5. Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
Problem: If code segment limit is set close to the end of a code page, then due to this
erratum the memory page Access bit (A bit) may be set for the subsequent
page prior to general protection fault on code segment limit.
Implication: When this erratum occurs, a non-accessed page which is present in memory
and follows a page that contains the code segment limit may be tagged as
accessed.
Workaround: Erratum can be avoided by placing a guard page (non-present or non-
executable page) as the last page of the segment or after the page that
includes the code segment limit.
Status: For the steppings affected, see the Summary Tables of Changes.
AW6. Updating Code Page Directory Attributes without TLB Invalidation May
Result in Improper Handling of Code #PF
Problem: Code #PF (Page Fault exception) is normally handled in lower priority order
relative to both code #DB (Debug Exception) and code Segment Limit

Errata
20 Intel® Core™2 Duo Processor
Specification Update
Violation #GP (General Protection Fault). Due to this erratum, code #PF may
be handled incorrectly, if all of the following conditions are met:
•A PDE (Page Directory Entry) is modified without invalidating the
corresponding TLB (Translation Look-aside Buffer) entry
•Code execution transitions to a different code page such that both
oThe target linear address corresponds to the modified PDE
oThe PTE (Page Table Entry) for the target linear address has an
A (Accessed) bit that is clear
•One of the following simultaneous exception conditions is present
following the code transition
oCode #DB and code #PF
oCode Segment Limit Violation #GP and code #PF
Implication: Software may observe either incorrect processing of code #PF before code
Segment Limit Violation #GP or processing of code #PF in lieu of code #DB.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AW7. Storage of PEBS Record Delayed Following Execution of MOV SS or STI
Problem: When a performance monitoring counter is configured for PEBS (Precise Event
Based Sampling), overflow of the counter results in storage of a PEBS record
in the PEBS buffer. The information in the PEBS record represents the state
of the next instruction to be executed following the counter overflow. Due to
this erratum, if the counter overflow occurs after execution of either MOV SS
or STI, storage of the PEBS record is delayed by one instruction.
Implication: When this erratum occurs, software may observe storage of the PEBS record
being delayed by one instruction following execution of MOV SS or STI. The
state information in the PEBS record will also reflect the one instruction delay.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AW8. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask
01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions.
Due to this erratum, if only a small number of MMX instructions (including
EMMS) are executed immediately after the last FP instruction, a FP to MMX
transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX
may be lower than expected. The degree of undercounting is dependent on
the occurrences of the erratum condition while the counter is active. Intel has
not observed this erratum with any commercially available software.