Intel 6 SERIES User manual

Document Number: 325208
2nd Generation Intel®Core™
Processor Family with
Intel®6 Series Chipset
Development Kit
User Guide
March 2011

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
2 Document Number: 325208-001
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About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 3
Contents
1About This Document ................................................................................................... 7
1.1 Content Overview...................................................................................................7
1.2 Text Conventions....................................................................................................7
1.3 Glossary of Terms and Acronyms .............................................................................9
1.4 Related Documents and Information.......................................................................14
1.5 Development Kit Technical Support ........................................................................15
1.5.1 Online Support..........................................................................................15
1.5.2 Additional Technical Support.......................................................................15
2Getting Started........................................................................................................... 16
2.1 Development Kit Contents.....................................................................................16
2.2 Additional Required Hardware Not Included In This Kit .............................................16
2.3 Additional Required Software Not Included in this Kit................................................17
2.4 Workspace Preparation..........................................................................................18
2.5 System Setup ......................................................................................................18
2.6System Power-Up.................................................................................................19
2.7 System Power-Down.............................................................................................19
2.8 System BIOS .......................................................................................................19
2.8.1 Configuring the BIOS.................................................................................20
2.8.2 Programming BIOS Using a Bootable USB Device..........................................20
3Development Kit Features.......................................................................................... 22
3.1 Processor Support ................................................................................................24
3.1.1 Clock Requirements...................................................................................25
3.1.2 Processor Voltage Regulator .......................................................................25
3.1.2.1 SVID Supported in Intel®MVP-7 Voltage Regulator .......................25
3.1.3 Power Management and Key Signals............................................................25
3.1.4 Memory Support .......................................................................................26
3.1.5 Graphics Support ......................................................................................27
3.1.5.1 Internal Graphics Support...........................................................27
3.1.5.2 External Graphics Support ..........................................................28
3.1.5.3 Direct Media Interface (DMI)-2 Interface......................................28
3.1.6 Intel®Flexible Display Interface (Intel®FDI)................................................28
3.1.7 Processor Thermals ...................................................................................29
3.1.8 Processor Active Cooling ............................................................................29
3.2PCH Support ........................................................................................................29
3.2.1 Introduction to the Intel®6 Series Chipset...................................................29
3.2.2 Key Power Management Signals..................................................................29
3.2.3 PCIe* Support ..........................................................................................30
3.2.4 On-Board LAN...........................................................................................32
3.2.5 Soft Audio and Modem...............................................................................33
3.2.5.1 Realtek* Audio Card Support ......................................................33
3.2.6 SATA Storage ...........................................................................................34
3.2.7 Displays ...................................................................................................34
3.2.7.1 DP/HDMI Support ......................................................................36
3.2.7.2 DMC Support.............................................................................37

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
4 Document Number: 325208-001
3.2.7.3 Switchable Graphics...................................................................37
3.2.8 USB Connectors ........................................................................................38
3.2.8.1 USB2.0.....................................................................................38
3.2.9 LPC Super I/O (SIO)/LPC Slot.....................................................................40
3.2.10 Serial Port, IrDA........................................................................................40
3.2.11 System Management Controller (SMC)/Keyboard Controller (KBC)..................40
3.2.12 SPI ..........................................................................................................41
3.2.12.1 Multi-BIOS Support....................................................................41
3.2.12.2 Clocks ......................................................................................42
3.2.12.3 CPU_ITP Clock and XDP Clock .....................................................43
3.2.13 Real Time Clock ........................................................................................44
3.3 Debug Interfaces..................................................................................................45
3.3.1 Processor and PCH Debug ..........................................................................45
3.4Chassis................................................................................................................45
3.5 Power Supply Solutions, Usage, and Recommendations ............................................45
3.5.1 Power Supply Solutions..............................................................................45
3.5.2 Power Supply Usage and Recommendation ..................................................46
3.6 Power Management ..............................................................................................47
3.6.1 Power Management States.........................................................................47
4Development Board Summary.................................................................................... 48
4.1 Features..............................................................................................................48
4.2 Connectors ..........................................................................................................51
4.2.1 Back Panel Connectors...............................................................................51
4.3 Configuration Settings...........................................................................................52
4.3.1 Configuration Jumpers/Switches .................................................................52
4.4 Power On and Reset Button ...................................................................................53
4.5LEDs ...................................................................................................................54
5Quick Start ................................................................................................................. 56
5.1 Required Peripherals.............................................................................................56
5.2 Instructions to Flash BIOS to SPI ...........................................................................56
5.3 H8 Programming ..................................................................................................56
5.4 Key Jumpers........................................................................................................57
Figures
Figure 1. Development Board Block Diagram ........................................................22
Figure 2. Side View of Stacked SODIMM Slots.......................................................27
Figure 3. PCIe* Port Mapping – Schematic Snapshot .............................................31
Figure 4. On-Board LAN Block Diagram ................................................................33
Figure 5. Back Panel Connectors..........................................................................35
Figure 6. Display Ports On-Board.........................................................................36
Figure 7 Mini PCIe Connector Soldered In Place of DMC .........................................37
Figure 8. Switchable Graphics with eDP from PCH .................................................38
Figure 9. Clock (Integrated Mode) Block Diagram..................................................43
Figure 10. Block Diagram of GDXC and XDP Clock on the Development Board..........43
Figure 11. Layout Snapshot for Reworks for GDXC and XDP Clock Options On-Board 44
Figure 12. Development Board Components – Top View.........................................48
Figure 13. Development Board Components - Bottom View ....................................50
Figure 14. Back Panel Connectors........................................................................51
Figure 15. Jumpers for Programming SPI and H8 ..................................................58

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 5
Tables
Table 1. Text Conventions ....................................................................................7
Table 2. Terms ....................................................................................................9
Table 3. Acronyms .............................................................................................11
Table 4. Related Documents and Information........................................................15
Table 5. Development Board Feature Description ..................................................22
Table 6. CFG[6] and [5] Straps Combined and Used for PEG Interface Configuration.28
Table 7. Other PEG Interface Straps ....................................................................28
Table 8. PCIe* Ports...........................................................................................30
Table 9. Reworks for Different Port Mappings........................................................32
Table 10. Selection of I/O Voltage for the Intel®High Definition Audio.....................33
Table 11. SATA Ports..........................................................................................34
Table 12. USB Port Mapping................................................................................39
Table 13. USB2.0 Ports.......................................................................................40
Table 14. Jumper Settings for SPI Programming....................................................41
Table 15. Multi-BIOS Implementation ..................................................................42
Table 16. Development Board Power Management States ......................................47
Table 17. Development Board Components List - Top View.....................................49
Table 18. Development Board Components List - Bottom View ...............................50
Table 19. Back Panel Connectors.........................................................................51
Table 20. Configuration Jumper/Switches .............................................................52
Table 21. Power On and Reset Button ..................................................................54
Table 22. Other Development Board Switches.......................................................54
Table 23. Development Board LEDs .....................................................................54
Table 24. H8 Programming Jumpers ....................................................................57
Table 25. Key Jumpers.......................................................................................58

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
6 Document Number: 325208-001
Revision History
Document
Number Revision Number Description Revision Date
325208 001 Initial release. March 2011

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 7
1About This Document
This guide describes the use of the 2nd Generation Intel®Core™ Processor Family with
Intel®6 Series Chipset Development Kit. The document has been written for OEMs,
system evaluators, and embedded system developers, and assumes basic familiarity
in the fundamental concepts involved with installing and configuring hardware for a
personal computer system. The document defines all jumpers, headers, LED functions,
their locations on the development kit, and other subsystem features and POST codes.
For the latest information about the 2nd Generation Intel®Core™ Processor Family
with Intel®6 Series Chipset development board design collateral, please visit the
Intel®Embedded Design Center.
1.1 Content Overview
This manual is arranged into the following sections:
•About This Document contains a description of conventions used in this document.
The last few sections explain how to obtain literature and contact customer
support.
•Getting Started describes the contents of the development kit and explains the
basics steps necessary to get the board running. This section also includes
information on how to update the BIOS.
•Development Kit Features describes details on the hardware features of the
development board. It explains the Power Management and Testability features.
•Development Board Summary provides a list of major board components and
connectors. It gives a description of jumper settings and functions. The section
also explains the use of the programming headers.
•Add-In Cards contains information on add-in cards available from Intel that can be
used with the development board.
1.2 Text Conventions
The notations listed in Table 1 may be used throughout this document.
Table 1. Text Conventions
Notation Definition
# The pound symbol (#) appended to a signal name indicates that the signal
is active low (e.g., PRSNT1#).
Variables Variables are shown in italics. Variables must be replaced with correct
values.
Instructions Instruction mnemonics are shown in uppercase. When you are
programming, instructions are not case-sensitive. You may use either

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
8 Document Number: 325208-001
Notation Definition
uppercase or lowercase.
Numbers
Hexadecimal numbers are represented by a string of hexadecimal digits
followed by the character H. A zero prefix is added to numbers that begin
with A through F. (For example, FF is shown as 0FFH.) Decimal and binary
numbers are represented by their customary notations (i.e., 255 is a
decimal number and 1111 is a binary number; in some cases, the letter B
is added for clarity).
Units of Measure
A
Gbyte
Gb
GT
Kbyte
KΩ
mA
Mbyte
MHz
ms
MT
mW
ns
pF
W
V
µA
µF
µs
µW
The following abbreviations are used to represent units of measure:
amps, amperes
gigabytes
gigabits
giga transfers
kilobytes
kilo-ohms
milliamps, mill amperes
megabytes
megahertz
milliseconds
Mega Transfers
milliwatts
nanoseconds
picofarads
watts
volts
microamps, microamperes
microfarads
microseconds
microwatts
Signal Names
Signal names are shown in uppercase. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number, while the group is represented by the signal name
followed by a variable (n). For example, the lower chip-select signals are
named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#.
A pound symbol (#) appended to a signal name identifies an active-low
signal. Port pins are represented by the port abbreviation, a period, and
the pin number (e.g., P1.0).

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 9
1.3 Glossary of Terms and Acronyms
Table 2 defines conventions and terminology used throughout this document.
Table 2. Terms
Term Definition
Aggressor A network that transmits a coupled signal to another network.
Anti-etch Any plane-split, void or cutout in a VCC or GND plane.
Bus Agent A component or group of components that, when combined, represent a
single load on the AGTL+ bus.
Crosstalk
The reception on a victim network of a signal imposed by aggressor
network(s) through inductive and capacitive coupling between the
networks.
Backward Crosstalk - Coupling that creates a signal in a victim network
that travels in the opposite direction as the aggressor’s signal.
Forward Crosstalk - Coupling that creates a signal in a victim network that
travels in the same direction as the aggressor’s signal.
Even Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch in the same direction that the victim is switching.
Odd Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch to the direction opposite the victim’s switching.
Duck Bay 3 PCI Express* interposer card that provides Express-card support for the
development board
Flight Time
Flight time is a term in the timing equation that includes the signal
propagation delay, any effects the system has on the TCO (time from
clock-in to data-out) of the driver, plus any adjustments to the signal at
the receiver needed to ensure the setup time of the receiver. More
precisely, flight time is defined as:
The time difference between a signal at the input pin of a receiving agent
crossing the switching voltage (adjusted to meet the receiver
manufacturer’s conditions required for AC timing specifications; i.e.,
ringback, etc.) and the output pin of the driving agent crossing the
switching voltage when the driver is driving a test load used to specify the
driver’s AC timings.
Maximum and Minimum Flight Time - Flight time variations are caused by
many different parameters. The more obvious causes include variation of
the board dielectric constant, changes in load condition, crosstalk, power
noise, variation in termination resistance, and differences in I/O buffer
performance as a function of temperature, voltage, and manufacturing
process. Some less obvious causes include effects of Simultaneous
Switching Output (SSO) and packaging effects.
Maximum flight time is the largest acceptable flight time a network will
experience under all conditions.
Minimum flight time is the smallest acceptable flight time a network will
experience under all conditions.
Gen 2 PCI Express Generation 2

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
10 Document Number: 325208-001
Term Definition
Infrared Data
Assoc.
The Infrared Data Association (IrDA) has outlined a specification for serial
communication between two devices via a bidirectional infrared data port.
The CRB has such a port and it is located on the rear of the platform
between the two USB connectors.
Intel®MVP 7.0 The Intel®Mobile Voltage Positioning specification for the 2nd generation Intel®Core™ Processor Family. It is a DC-DC converter module that
supplies the required voltage and current to a single processor.
Inter-Symbol
Interference
Inter-symbol interference is the effect of a previous signal (or transition)
on the interconnect delay. For example, when a signal is transmitted
down a line and the reflections due to the transition have not completely
dissipated, the following data transition launched onto the bus is affected.
ISI is dependent upon frequency, time delay of the line, and the reflection
coefficient at the driver and receiver. ISI may impact both timing and
signal integrity.
Mott Canyon IV This Add-in card enables Intel®High Definition Audio functionality.
Network The network is the trace of a Printed Circuit Board (PCB) that completes
an electrical connection between two or more components.
Overshoot The maximum voltage observed for a signal at the device pad, measured
with respect to VCC.
Pad The electrical contact point of a semiconductor die to the package
substrate. A pad is only observable in simulations.
Pin The contact point of a component package to the traces on a substrate, such as the motherboard. Signal quality and timings may be measured at
the pin.
Power-Good
“Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal)
indicates that all of the system power supplies and clocks are stable.
PWRGOOD should go active at a predetermined time after system
voltages are stable and should go inactive as soon as any of these
voltages fail their specifications.
Ringback The voltage to which a signal changes after reaching its maximum absolute value. Ringback may be caused by reflections, driver oscillations,
or other transmission line phenomena.
RJ45 A type of registered jack.
System Bus The System Bus is the microprocessor bus of the processor.
Setup Window The time between the beginning of Setup to Clock (TSU_MIN) and the arrival of a valid clock edge. This window may be different for each type of
bus agent in the system.
Simultaneous
Switching Output
Simultaneous Switching Output (SSO) effects are differences in electrical
timing parameters and degradation in signal quality caused by multiple
signal outputs simultaneously switching voltage levels in the opposite
direction from a single signal or in the same direction. These are called
odd mode and even mode switching, respectively. This simultaneous
switching of multiple outputs creates higher current swings that may
cause additional propagation delay (“push-out”) or a decrease in
propagation delay (“pull-in”). These SSO effects may impact the setup
and/or hold times and are not always taken into account by simulations.
System timing budgets should include margin for SSO effects.