Intel 6 SERIES User manual

Document Number: 325208
2nd Generation Intel®Core™
Processor Family with
Intel®6 Series Chipset
Development Kit
User Guide
March 2011

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
2 Document Number: 325208-001
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Copyright © 2011, Intel Corporation. All Rights Reserved.

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 3
Contents
1About This Document ................................................................................................... 7
1.1 Content Overview...................................................................................................7
1.2 Text Conventions....................................................................................................7
1.3 Glossary of Terms and Acronyms .............................................................................9
1.4 Related Documents and Information.......................................................................14
1.5 Development Kit Technical Support ........................................................................15
1.5.1 Online Support..........................................................................................15
1.5.2 Additional Technical Support.......................................................................15
2Getting Started........................................................................................................... 16
2.1 Development Kit Contents.....................................................................................16
2.2 Additional Required Hardware Not Included In This Kit .............................................16
2.3 Additional Required Software Not Included in this Kit................................................17
2.4 Workspace Preparation..........................................................................................18
2.5 System Setup ......................................................................................................18
2.6System Power-Up.................................................................................................19
2.7 System Power-Down.............................................................................................19
2.8 System BIOS .......................................................................................................19
2.8.1 Configuring the BIOS.................................................................................20
2.8.2 Programming BIOS Using a Bootable USB Device..........................................20
3Development Kit Features.......................................................................................... 22
3.1 Processor Support ................................................................................................24
3.1.1 Clock Requirements...................................................................................25
3.1.2 Processor Voltage Regulator .......................................................................25
3.1.2.1 SVID Supported in Intel®MVP-7 Voltage Regulator .......................25
3.1.3 Power Management and Key Signals............................................................25
3.1.4 Memory Support .......................................................................................26
3.1.5 Graphics Support ......................................................................................27
3.1.5.1 Internal Graphics Support...........................................................27
3.1.5.2 External Graphics Support ..........................................................28
3.1.5.3 Direct Media Interface (DMI)-2 Interface......................................28
3.1.6 Intel®Flexible Display Interface (Intel®FDI)................................................28
3.1.7 Processor Thermals ...................................................................................29
3.1.8 Processor Active Cooling ............................................................................29
3.2PCH Support ........................................................................................................29
3.2.1 Introduction to the Intel®6 Series Chipset...................................................29
3.2.2 Key Power Management Signals..................................................................29
3.2.3 PCIe* Support ..........................................................................................30
3.2.4 On-Board LAN...........................................................................................32
3.2.5 Soft Audio and Modem...............................................................................33
3.2.5.1 Realtek* Audio Card Support ......................................................33
3.2.6 SATA Storage ...........................................................................................34
3.2.7 Displays ...................................................................................................34
3.2.7.1 DP/HDMI Support ......................................................................36
3.2.7.2 DMC Support.............................................................................37

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2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
4 Document Number: 325208-001
3.2.7.3 Switchable Graphics...................................................................37
3.2.8 USB Connectors ........................................................................................38
3.2.8.1 USB2.0.....................................................................................38
3.2.9 LPC Super I/O (SIO)/LPC Slot.....................................................................40
3.2.10 Serial Port, IrDA........................................................................................40
3.2.11 System Management Controller (SMC)/Keyboard Controller (KBC)..................40
3.2.12 SPI ..........................................................................................................41
3.2.12.1 Multi-BIOS Support....................................................................41
3.2.12.2 Clocks ......................................................................................42
3.2.12.3 CPU_ITP Clock and XDP Clock .....................................................43
3.2.13 Real Time Clock ........................................................................................44
3.3 Debug Interfaces..................................................................................................45
3.3.1 Processor and PCH Debug ..........................................................................45
3.4Chassis................................................................................................................45
3.5 Power Supply Solutions, Usage, and Recommendations ............................................45
3.5.1 Power Supply Solutions..............................................................................45
3.5.2 Power Supply Usage and Recommendation ..................................................46
3.6 Power Management ..............................................................................................47
3.6.1 Power Management States.........................................................................47
4Development Board Summary.................................................................................... 48
4.1 Features..............................................................................................................48
4.2 Connectors ..........................................................................................................51
4.2.1 Back Panel Connectors...............................................................................51
4.3 Configuration Settings...........................................................................................52
4.3.1 Configuration Jumpers/Switches .................................................................52
4.4 Power On and Reset Button ...................................................................................53
4.5LEDs ...................................................................................................................54
5Quick Start ................................................................................................................. 56
5.1 Required Peripherals.............................................................................................56
5.2 Instructions to Flash BIOS to SPI ...........................................................................56
5.3 H8 Programming ..................................................................................................56
5.4 Key Jumpers........................................................................................................57
Figures
Figure 1. Development Board Block Diagram ........................................................22
Figure 2. Side View of Stacked SODIMM Slots.......................................................27
Figure 3. PCIe* Port Mapping – Schematic Snapshot .............................................31
Figure 4. On-Board LAN Block Diagram ................................................................33
Figure 5. Back Panel Connectors..........................................................................35
Figure 6. Display Ports On-Board.........................................................................36
Figure 7 Mini PCIe Connector Soldered In Place of DMC .........................................37
Figure 8. Switchable Graphics with eDP from PCH .................................................38
Figure 9. Clock (Integrated Mode) Block Diagram..................................................43
Figure 10. Block Diagram of GDXC and XDP Clock on the Development Board..........43
Figure 11. Layout Snapshot for Reworks for GDXC and XDP Clock Options On-Board 44
Figure 12. Development Board Components – Top View.........................................48
Figure 13. Development Board Components - Bottom View ....................................50
Figure 14. Back Panel Connectors........................................................................51
Figure 15. Jumpers for Programming SPI and H8 ..................................................58

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2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 5
Tables
Table 1. Text Conventions ....................................................................................7
Table 2. Terms ....................................................................................................9
Table 3. Acronyms .............................................................................................11
Table 4. Related Documents and Information........................................................15
Table 5. Development Board Feature Description ..................................................22
Table 6. CFG[6] and [5] Straps Combined and Used for PEG Interface Configuration.28
Table 7. Other PEG Interface Straps ....................................................................28
Table 8. PCIe* Ports...........................................................................................30
Table 9. Reworks for Different Port Mappings........................................................32
Table 10. Selection of I/O Voltage for the Intel®High Definition Audio.....................33
Table 11. SATA Ports..........................................................................................34
Table 12. USB Port Mapping................................................................................39
Table 13. USB2.0 Ports.......................................................................................40
Table 14. Jumper Settings for SPI Programming....................................................41
Table 15. Multi-BIOS Implementation ..................................................................42
Table 16. Development Board Power Management States ......................................47
Table 17. Development Board Components List - Top View.....................................49
Table 18. Development Board Components List - Bottom View ...............................50
Table 19. Back Panel Connectors.........................................................................51
Table 20. Configuration Jumper/Switches .............................................................52
Table 21. Power On and Reset Button ..................................................................54
Table 22. Other Development Board Switches.......................................................54
Table 23. Development Board LEDs .....................................................................54
Table 24. H8 Programming Jumpers ....................................................................57
Table 25. Key Jumpers.......................................................................................58

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
6 Document Number: 325208-001
Revision History
Document
Number Revision Number Description Revision Date
325208 001 Initial release. March 2011

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 7
1About This Document
This guide describes the use of the 2nd Generation Intel®Core™ Processor Family with
Intel®6 Series Chipset Development Kit. The document has been written for OEMs,
system evaluators, and embedded system developers, and assumes basic familiarity
in the fundamental concepts involved with installing and configuring hardware for a
personal computer system. The document defines all jumpers, headers, LED functions,
their locations on the development kit, and other subsystem features and POST codes.
For the latest information about the 2nd Generation Intel®Core™ Processor Family
with Intel®6 Series Chipset development board design collateral, please visit the
Intel®Embedded Design Center.
1.1 Content Overview
This manual is arranged into the following sections:
•About This Document contains a description of conventions used in this document.
The last few sections explain how to obtain literature and contact customer
support.
•Getting Started describes the contents of the development kit and explains the
basics steps necessary to get the board running. This section also includes
information on how to update the BIOS.
•Development Kit Features describes details on the hardware features of the
development board. It explains the Power Management and Testability features.
•Development Board Summary provides a list of major board components and
connectors. It gives a description of jumper settings and functions. The section
also explains the use of the programming headers.
•Add-In Cards contains information on add-in cards available from Intel that can be
used with the development board.
1.2 Text Conventions
The notations listed in Table 1 may be used throughout this document.
Table 1. Text Conventions
Notation Definition
# The pound symbol (#) appended to a signal name indicates that the signal
is active low (e.g., PRSNT1#).
Variables Variables are shown in italics. Variables must be replaced with correct
values.
Instructions Instruction mnemonics are shown in uppercase. When you are
programming, instructions are not case-sensitive. You may use either

About This Document
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
8 Document Number: 325208-001
Notation Definition
uppercase or lowercase.
Numbers
Hexadecimal numbers are represented by a string of hexadecimal digits
followed by the character H. A zero prefix is added to numbers that begin
with A through F. (For example, FF is shown as 0FFH.) Decimal and binary
numbers are represented by their customary notations (i.e., 255 is a
decimal number and 1111 is a binary number; in some cases, the letter B
is added for clarity).
Units of Measure
A
Gbyte
Gb
GT
Kbyte
KΩ
mA
Mbyte
MHz
ms
MT
mW
ns
pF
W
V
µA
µF
µs
µW
The following abbreviations are used to represent units of measure:
amps, amperes
gigabytes
gigabits
giga transfers
kilobytes
kilo-ohms
milliamps, mill amperes
megabytes
megahertz
milliseconds
Mega Transfers
milliwatts
nanoseconds
picofarads
watts
volts
microamps, microamperes
microfarads
microseconds
microwatts
Signal Names
Signal names are shown in uppercase. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number, while the group is represented by the signal name
followed by a variable (n). For example, the lower chip-select signals are
named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#.
A pound symbol (#) appended to a signal name identifies an active-low
signal. Port pins are represented by the port abbreviation, a period, and
the pin number (e.g., P1.0).

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2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 9
1.3 Glossary of Terms and Acronyms
Table 2 defines conventions and terminology used throughout this document.
Table 2. Terms
Term Definition
Aggressor A network that transmits a coupled signal to another network.
Anti-etch Any plane-split, void or cutout in a VCC or GND plane.
Bus Agent A component or group of components that, when combined, represent a
single load on the AGTL+ bus.
Crosstalk
The reception on a victim network of a signal imposed by aggressor
network(s) through inductive and capacitive coupling between the
networks.
Backward Crosstalk - Coupling that creates a signal in a victim network
that travels in the opposite direction as the aggressor’s signal.
Forward Crosstalk - Coupling that creates a signal in a victim network that
travels in the same direction as the aggressor’s signal.
Even Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch in the same direction that the victim is switching.
Odd Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch to the direction opposite the victim’s switching.
Duck Bay 3 PCI Express* interposer card that provides Express-card support for the
development board
Flight Time
Flight time is a term in the timing equation that includes the signal
propagation delay, any effects the system has on the TCO (time from
clock-in to data-out) of the driver, plus any adjustments to the signal at
the receiver needed to ensure the setup time of the receiver. More
precisely, flight time is defined as:
The time difference between a signal at the input pin of a receiving agent
crossing the switching voltage (adjusted to meet the receiver
manufacturer’s conditions required for AC timing specifications; i.e.,
ringback, etc.) and the output pin of the driving agent crossing the
switching voltage when the driver is driving a test load used to specify the
driver’s AC timings.
Maximum and Minimum Flight Time - Flight time variations are caused by
many different parameters. The more obvious causes include variation of
the board dielectric constant, changes in load condition, crosstalk, power
noise, variation in termination resistance, and differences in I/O buffer
performance as a function of temperature, voltage, and manufacturing
process. Some less obvious causes include effects of Simultaneous
Switching Output (SSO) and packaging effects.
Maximum flight time is the largest acceptable flight time a network will
experience under all conditions.
Minimum flight time is the smallest acceptable flight time a network will
experience under all conditions.
Gen 2 PCI Express Generation 2

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2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
10 Document Number: 325208-001
Term Definition
Infrared Data
Assoc.
The Infrared Data Association (IrDA) has outlined a specification for serial
communication between two devices via a bidirectional infrared data port.
The CRB has such a port and it is located on the rear of the platform
between the two USB connectors.
Intel®MVP 7.0 The Intel®Mobile Voltage Positioning specification for the 2nd generation Intel®Core™ Processor Family. It is a DC-DC converter module that
supplies the required voltage and current to a single processor.
Inter-Symbol
Interference
Inter-symbol interference is the effect of a previous signal (or transition)
on the interconnect delay. For example, when a signal is transmitted
down a line and the reflections due to the transition have not completely
dissipated, the following data transition launched onto the bus is affected.
ISI is dependent upon frequency, time delay of the line, and the reflection
coefficient at the driver and receiver. ISI may impact both timing and
signal integrity.
Mott Canyon IV This Add-in card enables Intel®High Definition Audio functionality.
Network The network is the trace of a Printed Circuit Board (PCB) that completes
an electrical connection between two or more components.
Overshoot The maximum voltage observed for a signal at the device pad, measured
with respect to VCC.
Pad The electrical contact point of a semiconductor die to the package
substrate. A pad is only observable in simulations.
Pin The contact point of a component package to the traces on a substrate, such as the motherboard. Signal quality and timings may be measured at
the pin.
Power-Good
“Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal)
indicates that all of the system power supplies and clocks are stable.
PWRGOOD should go active at a predetermined time after system
voltages are stable and should go inactive as soon as any of these
voltages fail their specifications.
Ringback The voltage to which a signal changes after reaching its maximum absolute value. Ringback may be caused by reflections, driver oscillations,
or other transmission line phenomena.
RJ45 A type of registered jack.
System Bus The System Bus is the microprocessor bus of the processor.
Setup Window The time between the beginning of Setup to Clock (TSU_MIN) and the arrival of a valid clock edge. This window may be different for each type of
bus agent in the system.
Simultaneous
Switching Output
Simultaneous Switching Output (SSO) effects are differences in electrical
timing parameters and degradation in signal quality caused by multiple
signal outputs simultaneously switching voltage levels in the opposite
direction from a single signal or in the same direction. These are called
odd mode and even mode switching, respectively. This simultaneous
switching of multiple outputs creates higher current swings that may
cause additional propagation delay (“push-out”) or a decrease in
propagation delay (“pull-in”). These SSO effects may impact the setup
and/or hold times and are not always taken into account by simulations.
System timing budgets should include margin for SSO effects.

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March 2011 User Guide
Document Number: 325208-001 11
Term Definition
Stub The branch from the bus trunk terminating at the pad of an agent.
Trunk The main connection, excluding interconnect branches, from one end.
System
Management Bus A two-wire interface through which various system components may communicate.
Undershoot The minimum voltage extending below VSS observed for a signal at the
device pad.
VCC (CPU core) VCC (CPU core) is the core power for the processor. The system bus is
terminated to VCC (CPU core).
Victim A network that receives a coupled crosstalk signal from another network
is called the victim network.
Table 3 defines acronyms used throughout this document.
Table 3. Acronyms
Acronym Definition
AC Audio Codec
ACPI Advanced Configuration and Power Interface
ADD2 Advanced Digital Display 2
ADD2N Advanced Digital Display 2 Normal
AIC Add-In Card
AMC Audio/Modem Codec.
Intel®AMT Intel® Advanced Management Technology
ASF Alert Standard Format
AMI* American Megatrends Inc.* (BIOS developer)
ATA Advanced Technology Attachment (disk drive interface)
ATX Advance Technology Extended (motherboard form factor)
BGA Ball Grid Array
BIOS Basic Input/Output System
BLI Backlight Inverter
BPM Break Point Monitor
CK-SSCD Spread Spectrum Differential Clock
CMC Common Mode Choke
CMOS Complementary Metal-Oxide-Semiconductor
CPU Central Processing Unit (processor)
DDI Digital Display Interface
DDR Double Data Rate

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2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
12 Document Number: 325208-001
Acronym Definition
DMC Display Mini PCIe connector
DMI Direct Media Interface
DP Display Port
DPST Display Power Saving Technology
EC Embedded Controller
ECC Error Correcting Code
eDP Embedded Display Port
EEPROM Electrically Erasable Programmable Read-Only Memory
EHCI Enhanced Host Controller Interface
EM2 Eaglemont 2 card
EMA Extended Media Access
EMI Electro Magnetic Interference
eSATA External Serial Advanced Technology Attachment
ESD Electrostatic Discharge
EV Engineering Validation
EVMC Electrical Validation Margining Card
ERB Early Engineering Reference Board
FCBGA Flip Chip Ball Grid Array
FCIM Full Clock Integration Mode
FDD Floppy Disk Drive
FDI Flexible Display Interface
FIFO First In First Out - describes a type of buffer
FIR Fast Infrared
FPIO Front Panel IO
FS Full-speed. Refers to USB
FSB Front Side Bus
FWH Firmware Hub
GFX Graphics
GMCH Graphics Memory Controller Hub
GPIO General Purpose IO
Intel®HDA Intel®High Definition Audio
HDMI High Definition Media Interface
HPD Hot Plug Detect
HS High Speed. Refers to USB

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2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 13
Acronym Definition
ICH I/O Controller Hub
IDE Integrated Drive Electronics
Intel® MVP Intel®Mobile Voltage Positioning
IP/IPv6 Internet Protocol/Internet Protocol version 6
IrDA Infrared Data Association
ISI Inter-Symbol Interference
ITP In- Target Probe
KBC Keyboard Controller
LAI Logic Analyzer Interface
LAN Local Area Network
LED Light Emitting Diode
LOM LAN on Motherboard
LPC Low Pin Count (often used in reference to LPC bus)
LS Low-speed. Refers to USB.
LVDS Low Voltage Differential Signaling
MC Modem Codec
MDC Mobile Daughter Card
ME Manageability Engine
MHz Megahertz
MPI Metalized Particle Interconnect
OC Over current
ODD Optical Disc Drive
OS Operating System
OEM Original Equipment Manufacturer
PCB Printed Circuit Board
PCIe* PCI Express*
PCH Platform Controller Hub
PCM Pulse Code Modulation
PECI Platform Environment Control Interface
PEG PCI Express* Graphics
PGA Pin Grid Array
PLC Platform LAN Connect
PLL Phase Locked Loop
POST Power On Self Test

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2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
14 Document Number: 325208-001
Acronym Definition
PWM Pulse width modulation
RAID Redundant Array of Inexpensive Disks
rPGA Reduced pitch Pin Grid Array
RTC Real Time Clock
SATA Serial ATA
SIO Super Input/Output
SKU Stock Keeping Unit
SMC System Management Controller
SMBus System Management Bus
SO-DIMM Small Outline Dual In-line Memory Module
SOIC Small-Outline Integrated Circuit
SPD Serial Presence Detect
SPI Serial Peripheral Interface
SPWG Standard Panels Working Group - http://www.spwg.org/
SSO Simultaneous Switching Output
SUT System Under Test
STR Suspend To RAM
TCO Total Cost of Ownership
TCP Transmission Control Protocol
TPM Trusted Platform Module
TDM Time Division Multiplexed
TDR Time Domain Reflectometry
UDP User Datagram Protocol
UHCI Universal Host Controller Interface
USB Universal Serial Bus
VGA Video Graphics Adapter
VID Voltage Identification
VREG or VR Voltage Regulator
XDP eXtended Debug Port
1.4 Related Documents and Information
Table 4 provides a summary of available Intel classified documents and information
related to this development kit. To obtain, please contact your Intel representative.

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2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 15
Table 4. Related Documents and Information
Document Document
Number
[Cougar Point-M] Mobile Chipset I/O Buffer Information Specification (IBIS)
/ FASE Models 431974
[Huron River] Platform, Emerald Lake Fab 2 Customer Reference Board
Schematic 431433
[Huron River] Platform, Emerald Lake Fab 2 Customer Reference Board File 451503
[Huron River] Platform, Emerald Lake Customer Reference Board Cadence /
OrCad Symbol Files 431414
[Huron River] Platform Power Sequence Product Specification 437432
[Huron River] Platform Design Guide 436735
2nd Generation Intel®Core™ Processor Family Mobile External Design
Specification (EDS), Volume 1 and 2 445463/
445465
Intel®6 Series Chipset and Intel®C200 Series Chipset External Design
Specification (EDS) 443554
Note: The items listed in the above table are Intel classified; please contact your Intel
representative.
1.5 Development Kit Technical Support
1.5.1 Online Support
Intel’s web site (http://www.intel.com/) provides up-to-date technical information and
product support.
1.5.2 Additional Technical Support
If you require additional technical support, please contact your Intel representative or
local distributor.

Getting Started
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
16 Document Number: 325208-001
2Getting Started
2.1 Development Kit Contents
The following hardware, software and documentation are included in the kit. Check for
damage that may have occurred during shipment. Contact your sales representative if
any items are missing or damaged.
•Letter to the Customer
oInformation regarding website to download:
oSystem BIOS
oBIOS installation utilities
oChipset drivers
oIntel Embedded Graphics Drivers
oIntel®Active Management Technology (Intel®AMT) software installation
kit
•Development Kit User Guide (this document)
•Pre-assembled development system, which includes:
oDevelopment board
oChassis and mounting screws (installed)
o2nd generation Intel®Core™ processor
oProcessor thermal solution and CPU back plate
•Intel®6 Series Chipset (installed)
•Intel®6 Series Chipset heatsink (installed)
•One type 2032, 3V lithium coin cell battery (installed)
•One 1GB DDR3 SO-DIMM
•One power supply
•One SATA hard disk drive
•One SATA DVD-ROM drive
•SATA cabling (data and power)
Current drivers required for this development are available at
http://platforms.intel.com.
2.2 Additional Required Hardware Not Included In
This Kit
The following additional hardware may be necessary to successfully set up and
operate the motherboard:

Getting Started
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 17
•VGA Monitor: Any standard VGA or multi-resolution monitor may be used. The
setup instructions in this section assume the use of a standard VGA monitor, TV,
or flat panel monitor.
•Keyboard: The development kit can support either a PS/2* or USB style
keyboard.
•Mouse: The development kit can support either a PS/2 or USB style mouse.
•Hard Disk Drives (HDDs) and Optical Disc Drives (ODD): Up to six SATA
drives and two IDE devices (master and slave) may be connected to the
development kit. An optical disc drive may be used to load the OS. All these
storage devices may be attached to the board simultaneously.
•Video Adapter: Integrated video is output from the VGA connector on the back
panel of the development kit. Alternately, an on-board HDMI connector, on-board
DP connector or LVDS displays can be used for desired display options. Check the
BIOS and the graphics driver, where appropriate, for the proper video output
settings.
•Network Adapter: A Gigabit network interface is provided on the board. The
network interface will not be operational until after all the necessary drivers have
been installed. A standard PCI/PCI Express* adapter may be used in conjunction
with, or in place of, the on-board network adapter.
You must supply appropriate network cables to utilize the LAN connector or any other
installed network cards.
•Other Devices and Adapters: The development kit functions much like a
standard desktop computer motherboard. Most PC-compatible peripherals can be
attached and configured to work with the development kit.
•Add-In Cards: The following add-in cards are mentioned throughout this
document and are used to enable different features on the board. They are not
provided with the board. Please contact your Intel representative for more
information on the functionality and availability of these cards.
oEaglemont card
oMott Canyon 4 card
oElk Creek card
oADD 2 card
oSaddle String 3 card
2.3 Additional Required Software Not Included in this
Kit
The following additional software may be necessary to operate this system:
•Operating System: The user must supply any needed operating system
installation files and licenses. A recent version of the Linux-based operating
system Fedora will be loaded into the SATA drive.
•Application Software: The user must supply any needed application software.

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2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
18 Document Number: 325208-001
2.4 Workspace Preparation
The development kit is shipped as an open system to provide flexibility in changing
hardware configurations and peripherals in a lab environment. Because the board is
not in a protective chassis, the user is required to take the following safety
precautions in handling and operating the board.
•The power supply cord is the main disconnect device to main power (AC power). A
power outlet should be readily accessible.
•To avoid shock, ensure that the power cord is connected to a properly wired and
grounded receptacle.
•Ensure that any equipment to which this product will be attached is also
connected to properly wired and grounded receptacles.
•Use a flame-retardant work surface and take note of the closest fire extinguisher
and emergency exits.
•Ensure a static-free work environment before removing any components from
their anti-static packaging. Wear an electrostatic discharge (ESD) wrist strap when
handling the development board or other development kit components. The
development board is susceptible to ESD damage, and such damage may cause
product failure or unpredictable operation.
2.5 System Setup
Please complete the steps outlined below to ensure the successful setup and operation
of your development kit system.
The following items should already be completed in the kit (i.e., no user procedure
required):
•Place one or more DDR3 SO-DIMMs in memory sockets, populating J4V1 and/or
J4U1.
•Place the quad-core Intel®Core™ i7-2710QE processor in socket U3E1 and lock in
place. Make sure to align the chip to the pin 1 marking. The kit includes a second
CPU for evaluation — the dual-core Intel®Core™ i5-2510E processor.
•Install the MPI socket and place the chipset at U7F1
•Attach the heat sink/fan for the processor at U3E1 and plug the fan power cable
into J3B1.
•Install the configuration jumpers as shown in Table 24 of this document. Refer to
Table 19 for a complete list of jumper settings.
•Verify presence of RTC battery in battery holder at BT5G1.
•Plug a mobile ATX AC brick into J1F2. Optionally plug in a battery pack into J1H1
or J1H2. Do not mix mobile and desktop power configurations.
•Attach a hard drive in J8J1.
The following steps need to be completed by the user:
1. Connect a PS/2 keyboard in J1A1 (bottom) or a USB keyboard in one of the
USB connectors.
2. Connect a PS/2 mouse in J1A1 (top) or a USB mouse in one of the USB
connectors.

Getting Started
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
March 2011 User Guide
Document Number: 325208-001 19
3. If internal graphics is not used, plug a PCIe* graphics card in the PCIe x16
slot J5C1 and connect a monitor to the card.
4. Connect an Ethernet* cable (optional), one end of the cable to the
motherboard, the other end to a live Ethernet hub.
5. Connect the monitor to the VGA connector. Also plug the monitor’s power
cable into an outlet.
2.6 System Power-Up
Having completed the steps outlined above, you are now ready to power up the
development kit:
1. Press the power button located at SW1E1.
2. As the system boots, press F2 to enter the BIOS setup screen.
3. Check time, date, and configuration settings. The default settings should be
sufficient for most users with the exception of Intel SpeedStep®Technology.
This feature is disabled by default and can be enabled in setup.
4. The PCIe hot plug support has to be enabled in setup if hot plug detect is
required.
5. Save and exit the BIOS setup.
The system boots and is ready for use.
Note: Fan/heatsink installation is discussed in Section 8.
Install operating system and necessary drivers:
Depending on the operating system chosen, drivers for components included in this
development kit can be found in http://edc.intel.com/Platforms/Core-QM67-
HM65/#sdrvutil. Please note that not all drivers are supported across all operating
systems.
2.7 System Power-Down
There are three options for powering-down the development board:
•Use OS-controlled shutdown through the Windows* Start menu (or equivalent)
•Press the power button on the motherboard at SW1E1 to begin power-down.
•If the system is hung, it is possible to asynchronously shut the system down by
holding the power button down continuously for 4 seconds.
Note: Powering-down the board by shutting off power at the ATX power supply is not
recommended.
2.8 System BIOS
A version of the AMI*BIOS is pre-loaded on the development board.

Getting Started
2nd Generation Intel®Core™ Processor with Intel®6 Series Chipset Development Kit
User Guide March 2011
20 Document Number: 325208-001
2.8.1 Configuring the BIOS
The default BIOS settings may need to be modified to enable or disable various
features of the development board. The BIOS settings are configured through a menu-
driven user interface, which is accessible during the Power On Self Test (POST). Press
the F2 key or Delete during POST to enter the BIOS interface.
For AMI BIOS POST codes, visit: http://www.ami.com.
For BIOS updates, please contact your Intel representative or visit
http://edc.intel.com/Platforms/Core-QM67-HM65/#sdrvutil.
2.8.2 Programming BIOS Using a Bootable USB Device
The flash chips that store the BIOS and BIOS extensions on the development board
are connected to the SPI bus and are soldered down. One method of programming
these devices is through software utilities described below. The software files and
utilities needed to program the BIOS are contained on the included CD-ROM.
Follow these steps to program the system BIOS using a bootable USB device:
1. Prepare the workspace as outlined in Section 2.4.
2. Set up the system as outlined in Section 2.5.
3. Unplug the hard disk drive (HDD) SATA cable from the board at connector
J6J3 so that the board will boot from the bootable USB key.
4. Copy the following files and utilities to a bootable USB device, preferably a
USB flash memory stick.
BIOS Image Files:
ospifull.bin
BIOS programming software utilities:
ofpt.exe (DOS SPI flash utility)
ofparts.txt (helper file)
MAC Address programming software utility:
oeeupdate.exe
oOther helper files contained on the included CD-ROM
5. Record the 12-digit MAC address of the board from the sticker near the CPU.
6. Insert the bootable USB key into one of the USB ports on the development
board.
7. Switch on the power supply (to “1”).
8. Press the power (PWR) button on the development board.
9. Wait for the system to boot from the USB key to a DOS prompt.
10. From the DOS prompt (C:>), run the following:
ofpt –f spifull.bin
Make sure there are no warnings or errors.
11. From DOS, run the following to reprogram the MAC address:
oeeupdate /nic=1 /mac=xxxxxxxxxxxx
owhere xxxxxxxxxxxx is the MAC address from the sticker