Intel PENTIUM P6000 SPECIFICATION 20 User manual

Document Number: 323874-002
Intel® Pentium® P6000 and U5000
Mobile Processor Series
Specification Update
June 2010
Revision 002

2xxx
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life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,
not across different processor families. See http://www.intel.com/products/processor_number for details.
The processor may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to
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Specification Update 3
Contents
Preface......................................................................................................................5
Summary Tables of Changes......................................................................................7
Identification Information.......................................................................................15
Errata......................................................................................................................17
Specification Changes..............................................................................................45
Specification Clarifications ......................................................................................46
Documentation Changes.......................................................................................... 47

4Specification Update
Revision History
§
Revision Description Revision
Date
-001 • Initial release May 2010
-002 • Added P6000 sku information June 2010

Specification Update 5
Preface
Preface
This document is an update to the specifications contained in the Affected Documents
table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system
manufacturers and software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification
update and are no longer published in other documents. This document may also
contain information that was not previously published.
Affected Documents
Related Documents
NOTES:
1. Documentation changes for the Intel® 64 and IA-32 Architecture Software Developer's Manual Volumes
1, 2A, 2B, 3A, and 3B will be posted in a separate document, the Intel® 64 and IA-32 Architecture
Software Developer's Manual Documentation Changes. Follow the link http://developer.intel.com/
products/processor/manuals/index.htm to access this documentation.
Document Title Document Number
Location
Intel Pentium P6000 and U5000 Mobile Processor Series Datasheet 323873
Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series
Datasheet - Volume 1 and Volume 2 322812, 322813
Document Title Document Number/
Location
AP-485, Intel® Processor Identification and the CPUID
Instruction http://www.intel.com/ design/processor/applnots/
241618.htm
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 1: Basic Architecture
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A: Instruction Set Reference Manual A-M
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B: Instruction Set Reference Manual N-Z
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A: System Programming Guide
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B: System Programming Guide
Intel®64 and IA-32 Intel Architecture Optimization Reference
Manual
Intel®64 and IA-32 Architectures Software Developer’s Manual
Documentation Changes (see note 1)
http://www.intel.com/
products/processor/manuals/
index.htm
ACPI Specifications www.acpi.info

Preface
6Specification Update
Nomenclature
Errata are design defects or errors. These may cause the Arrandale Processor behavior
to deviate from published specifications. Hardware and software designed to be used
with any given stepping must assume that all errata documented for that stepping are
present on all devices.
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics,e.g., core speed, L3 cache size, package
type, etc. as described in the processor identification information table. Read all notes
associated with each S-Spec number.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These will be incorporated in any new release of the
specification.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially-available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
§

Specification Update 7
Summary Tables of Changes
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the processor. Intel may fix
some of the errata in a future stepping of the component, and account for the other
outstanding issues through documentation or specification changes as noted. These
tables uses the following notations:
Codes Used in Summary Tables
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Change bar to left of table row indicates this erratum is either new or modified from the
previous version of the document.
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:

Summary Tables of Changes
8Specification Update
A = Dual-Core Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Dual-Core Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
I = Dual-Core Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1-MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology on 90-nm process
technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800-MHz system bus (1-MB and 2-MB L2 cache versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8-MB L3 cache
V = Mobile Intel® Celeron® processor on 0.13 micron process in Micro-FCPGA package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90-nm process with 2-MB L2 cache and Intel® processor A100 and
A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533-MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel® Celeron® processor in 478-pin package
AD = Intel® Celeron® D processor on 65-nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65-nm process
AF = Dual-Core Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® processor 5100 series
AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology
AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and
E4000 sequence
AJ = Quad-Core Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor
Q6000 sequence
AL = Dual-Core Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor

Specification Update 9
Summary Tables of Changes
AO = Quad-Core Intel® Xeon® processor 3200 series
AP = Dual-Core Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AT = Intel®Celeron®processor 200 series
AU = Intel® Celeron® Dual Core processor T1400
AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000 series
AW = Intel® Core™ 2 Duo processor E8000 series
AX = Quad-Core Intel® Xeon® processor 5400 series
AY = Dual-Core Intel® Xeon® processor 5200 series
AZ= Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-nm process
AAA= Quad-Core Intel® Xeon® processor 3300 series
AAB= Dual-Core Intel® Xeon® E3110 processor
AAC= Intel® Celeron® dual-core processor E1000 series
AAD = Intel® Core™2 Extreme processor QX9775
AAE = Intel® Atom™ processor Z5xx series
AAF = Intel® Atom™ processor 200 series
AAG = Intel® Atom™ processor N series
AAH = Intel® Atom™ processor300 series
AAI = Intel® Xeon® Processor 7400 series
AAJ = Intel® Core™ i7 processor and Intel® Core™ i7 Extreme Edition processor
AAK= Intel® Xeon® processor 5500 series
AAL = Intel® Pentium Dual-Core processor E5000 series
AAN = Intel® Core™ i7-800 and i5-700 desktop processor series
AAO = Intel® Xeon® Processor 3400 Series
AAP = Intel® Core™ i7-900 Mobile Processor Extreme Edition Series, Intel® Core™ i7-800 and i7-700 Mobile
Processor Series
AAT = Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series (Arrandale)
AAU = Intel® Core™ i5-600, i3-500 desktop processor series and Intel® Pentium® Processor G6950
AAZ = Intel® Celeron® P4000 and U3000 Mobile Processor Series (Arrandale)
BG = Intel® Pentium® P6000 and U5000 Mobile Processor Series (Arrandale)

Summary Tables of Changes
10 Specification Update
Errata (Sheet 1 of 4)
Number Steppings Status ERRATA
C-2 K-0
BG1 X X No Fix The Processor May Report a #TS Instead of a #GP Fault
BG2 X X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types
May Use an Incorrect Data Size or Lead to Memory-Ordering
Violations
BG3 X X No Fix Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions and
May Push the Wrong Address onto the Stack
BG4 X X No Fix Performance Monitor SSE Retired Instructions May Return
Incorrect Values
BG5 X X No Fix Premature Execution of a Load Operation Prior to Exception
Handler Invocation
BG6 X X No Fix MOV To/From Debug Registers Causes Debug Exception
BG7 X X No Fix Incorrect Address Computed For Last Byte of FXSAVE/
FXRSTOR Image Leads to Partial Memory Update
BG8 X X No Fix Values for LBR/BTS/BTM Will Be Incorrect after an Exit from
SMM
BG9 X X No Fix Single Step Interrupts with Floating Point Exception Pending
May Be Mishandled
BG10 X X No Fix Fault on ENTER Instruction May Result in Unexpected Values
on Stack Frame
BG11 X X No Fix IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception
BG12 X X No Fix General Protection Fault (#GP) for Instructions Greater than
15 Bytes May Be Preempted
BG13 X X No Fix General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
BG14 X X No Fix LBR, BTS, BTM May Report a Wrong Address When an
Exception/Interrupt Occurs in 64-bit Mode
BG15 X X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space
Results in Hang
BG16 X X No Fix Corruption of CS Segment Register during RSM While
Transitioning from Real Mode to Protected Mode
BG17 X X No Fix Performance Monitoring Events for Read Miss to Level 3
Cache Fill Occupancy Counter May Be Incorrect
BG18 X X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts
Inaccurately
BG19 X X No Fix #GP on Segment Selector Descriptor That Straddles Canonical Boundary May Not Provide Correct Exception Error
Code
BG20 X X No Fix Improper Parity Error Signaled in the IQ Following Reset
When a Code Breakpoint Is Set on a #GP Instruction