Intel PENTIUM P6000 SPECIFICATION 20 User manual

Document Number: 323874-002
Intel® Pentium® P6000 and U5000
Mobile Processor Series
Specification Update
June 2010
Revision 002

2xxx
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The processor may contain design defects or errors known as errata which may cause the product to deviate from published
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Specification Update 3
Contents
Preface......................................................................................................................5
Summary Tables of Changes......................................................................................7
Identification Information.......................................................................................15
Errata......................................................................................................................17
Specification Changes..............................................................................................45
Specification Clarifications ......................................................................................46
Documentation Changes.......................................................................................... 47

4Specification Update
Revision History
§
Revision Description Revision
Date
-001 • Initial release May 2010
-002 • Added P6000 sku information June 2010

Specification Update 5
Preface
Preface
This document is an update to the specifications contained in the Affected Documents
table below. This document is a compilation of device and documentation errata,
specification clarifications and changes. It is intended for hardware system
manufacturers and software developers of applications, operating systems, or tools.
Information types defined in Nomenclature are consolidated into the specification
update and are no longer published in other documents. This document may also
contain information that was not previously published.
Affected Documents
Related Documents
NOTES:
1. Documentation changes for the Intel® 64 and IA-32 Architecture Software Developer's Manual Volumes
1, 2A, 2B, 3A, and 3B will be posted in a separate document, the Intel® 64 and IA-32 Architecture
Software Developer's Manual Documentation Changes. Follow the link http://developer.intel.com/
products/processor/manuals/index.htm to access this documentation.
Document Title Document Number
Location
Intel Pentium P6000 and U5000 Mobile Processor Series Datasheet 323873
Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series
Datasheet - Volume 1 and Volume 2 322812, 322813
Document Title Document Number/
Location
AP-485, Intel® Processor Identification and the CPUID
Instruction http://www.intel.com/ design/processor/applnots/
241618.htm
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 1: Basic Architecture
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 2A: Instruction Set Reference Manual A-M
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 2B: Instruction Set Reference Manual N-Z
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 3A: System Programming Guide
Intel®64 and IA-32 Architectures Software Developer’s Manual,
Volume 3B: System Programming Guide
Intel®64 and IA-32 Intel Architecture Optimization Reference
Manual
Intel®64 and IA-32 Architectures Software Developer’s Manual
Documentation Changes (see note 1)
http://www.intel.com/
products/processor/manuals/
index.htm
ACPI Specifications www.acpi.info

Preface
6Specification Update
Nomenclature
Errata are design defects or errors. These may cause the Arrandale Processor behavior
to deviate from published specifications. Hardware and software designed to be used
with any given stepping must assume that all errata documented for that stepping are
present on all devices.
S-Spec Number is a five-digit code used to identify products. Products are
differentiated by their unique characteristics,e.g., core speed, L3 cache size, package
type, etc. as described in the processor identification information table. Read all notes
associated with each S-Spec number.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in any new release of the specification.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications will
be incorporated in any new release of the specification.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These will be incorporated in any new release of the
specification.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially-available. Under these circumstances,
errata removed from the specification update are archived and available upon request.
Specification changes, specification clarifications and documentation changes are
removed from the specification update when the appropriate changes are made to the
appropriate product specification or user documentation (datasheets, manuals, etc.).
§

Specification Update 7
Summary Tables of Changes
Summary Tables of Changes
The following tables indicate the errata, specification changes, specification
clarifications, or documentation changes which apply to the processor. Intel may fix
some of the errata in a future stepping of the component, and account for the other
outstanding issues through documentation or specification changes as noted. These
tables uses the following notations:
Codes Used in Summary Tables
Stepping
X: Errata exists in the stepping indicated. Specification Change or
Clarification that applies to this stepping.
(No mark)
or (Blank box): This erratum is fixed in listed stepping or specification change
does not apply to listed stepping.
Page
(Page): Page location of item in this document.
Status
Doc: Document change or update will be implemented.
Plan Fix: This erratum may be fixed in a future stepping of the product.
Fixed: This erratum has been previously fixed.
No Fix: There are no plans to fix this erratum.
Row
Change bar to left of table row indicates this erratum is either new or modified from the
previous version of the document.
Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:

Summary Tables of Changes
8Specification Update
A = Dual-Core Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Dual-Core Intel® Xeon® processor 2.80 GHz
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
I = Dual-Core Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1-MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology on 90-nm process
technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800-MHz system bus (1-MB and 2-MB L2 cache versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8-MB L3 cache
V = Mobile Intel® Celeron® processor on 0.13 micron process in Micro-FCPGA package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90-nm process with 2-MB L2 cache and Intel® processor A100 and
A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533-MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel® Celeron® processor in 478-pin package
AD = Intel® Celeron® D processor on 65-nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65-nm process
AF = Dual-Core Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® processor 5100 series
AH = Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology
AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and
E4000 sequence
AJ = Quad-Core Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 Quad processor
Q6000 sequence
AL = Dual-Core Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor

Specification Update 9
Summary Tables of Changes
AO = Quad-Core Intel® Xeon® processor 3200 series
AP = Dual-Core Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AT = Intel®Celeron®processor 200 series
AU = Intel® Celeron® Dual Core processor T1400
AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000 series
AW = Intel® Core™ 2 Duo processor E8000 series
AX = Quad-Core Intel® Xeon® processor 5400 series
AY = Dual-Core Intel® Xeon® processor 5200 series
AZ= Intel® Core™2 Duo processor and Intel® Core™2 Extreme processor on 45-nm process
AAA= Quad-Core Intel® Xeon® processor 3300 series
AAB= Dual-Core Intel® Xeon® E3110 processor
AAC= Intel® Celeron® dual-core processor E1000 series
AAD = Intel® Core™2 Extreme processor QX9775
AAE = Intel® Atom™ processor Z5xx series
AAF = Intel® Atom™ processor 200 series
AAG = Intel® Atom™ processor N series
AAH = Intel® Atom™ processor300 series
AAI = Intel® Xeon® Processor 7400 series
AAJ = Intel® Core™ i7 processor and Intel® Core™ i7 Extreme Edition processor
AAK= Intel® Xeon® processor 5500 series
AAL = Intel® Pentium Dual-Core processor E5000 series
AAN = Intel® Core™ i7-800 and i5-700 desktop processor series
AAO = Intel® Xeon® Processor 3400 Series
AAP = Intel® Core™ i7-900 Mobile Processor Extreme Edition Series, Intel® Core™ i7-800 and i7-700 Mobile
Processor Series
AAT = Intel® Core™ i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series (Arrandale)
AAU = Intel® Core™ i5-600, i3-500 desktop processor series and Intel® Pentium® Processor G6950
AAZ = Intel® Celeron® P4000 and U3000 Mobile Processor Series (Arrandale)
BG = Intel® Pentium® P6000 and U5000 Mobile Processor Series (Arrandale)

Summary Tables of Changes
10 Specification Update
Errata (Sheet 1 of 4)
Number Steppings Status ERRATA
C-2 K-0
BG1 X X No Fix The Processor May Report a #TS Instead of a #GP Fault
BG2 X X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and
Crossing Page Boundaries with Inconsistent Memory Types
May Use an Incorrect Data Size or Lead to Memory-Ordering
Violations
BG3 X X No Fix Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher Priority Interrupts/Exceptions and
May Push the Wrong Address onto the Stack
BG4 X X No Fix Performance Monitor SSE Retired Instructions May Return
Incorrect Values
BG5 X X No Fix Premature Execution of a Load Operation Prior to Exception
Handler Invocation
BG6 X X No Fix MOV To/From Debug Registers Causes Debug Exception
BG7 X X No Fix Incorrect Address Computed For Last Byte of FXSAVE/
FXRSTOR Image Leads to Partial Memory Update
BG8 X X No Fix Values for LBR/BTS/BTM Will Be Incorrect after an Exit from
SMM
BG9 X X No Fix Single Step Interrupts with Floating Point Exception Pending
May Be Mishandled
BG10 X X No Fix Fault on ENTER Instruction May Result in Unexpected Values
on Stack Frame
BG11 X X No Fix IRET under Certain Conditions May Cause an Unexpected
Alignment Check Exception
BG12 X X No Fix General Protection Fault (#GP) for Instructions Greater than
15 Bytes May Be Preempted
BG13 X X No Fix General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
BG14 X X No Fix LBR, BTS, BTM May Report a Wrong Address When an
Exception/Interrupt Occurs in 64-bit Mode
BG15 X X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space
Results in Hang
BG16 X X No Fix Corruption of CS Segment Register during RSM While
Transitioning from Real Mode to Protected Mode
BG17 X X No Fix Performance Monitoring Events for Read Miss to Level 3
Cache Fill Occupancy Counter May Be Incorrect
BG18 X X No Fix Performance Monitor Event SEGMENT_REG_LOADS Counts
Inaccurately
BG19 X X No Fix #GP on Segment Selector Descriptor That Straddles Canonical Boundary May Not Provide Correct Exception Error
Code
BG20 X X No Fix Improper Parity Error Signaled in the IQ Following Reset
When a Code Breakpoint Is Set on a #GP Instruction

Specification Update 11
Summary Tables of Changes
BG21 XXNoFix
An Enabled Debug Breakpoint or Single Step Trap May Be
Taken after MOV SS/POP SS Instruction If It Is Followed by
an Instruction That Signals a Floating Point Exception
BG22 X X No Fix IA32_MPERF Counter Stops Counting during On-Demand
TM1
BG23 X X No Fix The Memory Controller tTHROT_OPREF Timings May Be
Violated during Self-Refresh Entry
BG24 X X No Fix Synchronous Reset of IA32_APERF/IA32_MPERF Counters
on Overflow Does Not Work
BG25 X X No Fix Disabling Thermal Monitor While Processor is Hot, Then Re-
enabling, May Result in Stuck Core Operating Ratio
BG26 X X No Fix Writing the Local Vector Table (LVT) When an Interrupt is
Pending May Cause an Unexpected Interrupt
BG27 X X No Fix xAPIC Timer May Decrement Too Quickly Following an
Automatic Reload While in Periodic Mode
BG28 X X No Fix Changing the Memory Type for an In-Use Page Translation
May Lead to Memory-Ordering Violations
BG29 X X No Fix Infinite Stream of Interrupts May Occur If an ExtINT Delivery Mode Interrupt is Received While All Cores in Deep
Power Down Technology (code name C6 state)
BG30 X X No Fix Two xAPIC Timer Event Interrupts May Unexpectedly Occur
BG31 X X No Fix EOI Transaction May Not Be Sent If Software Enters Core Deep Power Down Technology (code name C6 state) during
an Interrupt Service Routine
BG32 X X No Fix FREEZE_WHILE_SMM Does Not Prevent Event from Pending
PEBS during SMM
BG33 X X No Fix APIC Error “Received Illegal Vector” May Be Lost
BG34 X X No Fix DR6 May Contain Incorrect Information When the First
Instruction after a MOV SS,r/m or POP SS Is a Store
BG35 X X No Fix An Uncorrectable Error Logged in IA32_CR_MC2_STATUS
May Also Result in a System Hang
BG36 X X No Fix IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly
Initialized
BG37 X X No Fix Performance Monitor Counter INST_RETIRED.STORES May
Count Higher Than Expected
BG38 X X No Fix Sleeping Cores May Not Be Woken Up on Logical Cluster Mode Broadcast IPI Using Destination Field Instead of
Shorthand
BG39 X X No Fix Faulting Executions of FXRSTOR May Update State
Inconsistently
BG40 X X No Fix Performance Monitor Event EPT.EPDPE_MISS May Be
Counted While EPT Is Disable
BG41 X X No Fix Memory Aliasing of Code Pages May Cause Unpredictable
System Behavior
Errata (Sheet 2 of 4)
Number Steppings Status ERRATA
C-2 K-0

Summary Tables of Changes
12 Specification Update
BG42 X X No Fix Performance Monitor Counters May Count Incorrectly
BG43 X X No Fix Performance Monitor Event Offcore_response_0 (B7H) Does
Not Count NT Stores to Local DRAM Correctly
BG44 X X No Fix Back-to-Back Uncorrected Machine Check Errors May
Overwrite IA32_MC3_STATUS.MSCOD
BG45 X X No Fix Corrected Errors with a Yellow Error Indication May Be
Overwritten by Other Corrected Errors
BG46 X X No Fix Performance Monitor Events DCACHE_CACHE_LD and
DCACHE_CACHE_ST May Overcount
BG47 X X No Fix Performance Monitor Events INSTR_RETIRED and
MEM_INST_RETIRED May Count Inaccurately
BG48 X X No Fix A Page Fault May Not Be Generated When the PS Bit Is Set
to “1” in a PML4E or PDPTE
BG49 X X No Fix BIST Results May Be Additionally Reported after a
GETSEC[WAKEUP] or INIT-SIPI Sequence
BG50 X X No Fix Pending x87 FPU Exceptions (#MF) May Be Signaled Earlier
Than Expected
BG51 X X No Fix Multiple Performance Monitor Interrupts are Possible on
Overflow of IA32_FIXED_CTR2
BG52 X X No Fix LBRs May Not be Initialized During Power-On Reset of the
Processor
BG53 X X No Fix
LBR, BTM or BTS Records May Have Incorrect Branch From
Information After an Enhanced Intel SpeedStep®
Technology Transition, T-states, C1E, or Adaptive Thermal
Throttling
BG54 X X No Fix DPRSLPVR Signal May Be Incorrectly Asserted on Transition
between Low Power C-states
BG55 X X No Fix Performance Monitoring Events STORE_BLOCKS.NOT_STA
and STORE_BLOCKS.STA May Not Count Events Correctly
BG56 X X No Fix Storage of PEBS Record Delayed Following Execution of MOV
SS or STI
BG57 X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX
May Not Count Some Transitions
BG58 X X No Fix LER MSRs May Be Unreliable
BG59 X X No Fix MCi_Status Overflow Bit May Be Incorrectly Set on a Single
Instance of a DTLB Error
BG60 X X No Fix Debug Exception Flags DR6.B0-B3 Flags May Be Incorrect
for Disabled Breakpoints
BG61 X X No Fix Critical ISOCH Traffic May Cause Unpredictable System
Behavior When Write Major Mode Enabled
BG62 X X No Fix A String Instruction That Re-maps a Page May Encounter an
Unexpected Page Fault
Errata (Sheet 3 of 4)
Number Steppings Status ERRATA
C-2 K-0

Specification Update 13
Summary Tables of Changes
BG63 X X No Fix MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent
Core Configurations
BG64 X X No Fix PCI Express* x16 Port Logs Bad TLP Correctable Error When
Receiving a Duplicate TLP
BG65 X X No Fix PCI Express x16 Root Port Incorrectly NAK's a Nullified TLP
BG66 X X No Fix PCI Express Graphics x16 Receiver Error Reported When
Receiver with L0s Enabled and Link Retrain Performed
BG67 X Fixed Internal Parity Error May Be Incorrectly Signaled during
Deep Power Down Technology (code name C6 state) Exit
BG68 X X No Fix PMIs during Core Deep Power Down Technology (code name
C6 state) Transitions May Cause the System to Hang
BG69 X X No Fix 2-MB Page Split Lock Accesses Combined with Complex
Internal Events May Cause Unpredictable System Behavior
BG70 X X No Fix Extra APIC Timer Interrupt May Occur during a Write to the
Divide Configuration Register
BG71 X Fixed 8259 Virtual Wire B Mode Interrupt May Be Dropped When it Collides With Interrupt Acknowledge Cycle From the
Preceding Interrupt
BG72 X Fixed CPUID Incorrectly Reports a C-State as Available When this
State is Unsupported
BG73 X X No Fix The Combination of a Page-Split Lock Access and Data Accesses That Are Split across Cacheline Boundaries May
Lead to Processor Livelock
BG74 X Fixed Processor Hangs on Package Deep Power Down technology (code named Deep Power Down Technology (code name C6)
State Exit
BG75 X X No Fix A Synchronous SMI May Be Delayed
BG76 X X No Fix
FP Data Operand Pointer May Be Incorrectly Calculated After
an FP Access Which Wraps a 4-Gbyte Boundary in Code That
Uses 32-Bit Address Size in 64-bit ModeFP Data Operand
Pointer May Be Incorrectly Calculated After an FP Access
Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
BG77 X X No Fix PCI Express Cards May Not Train to x16 Link Width
BG78 X X No Fix The APIC Timer Current Count Register May Prematurely
Read 0x0 While the Timer Is Still Running
BG79 X X No Fix CKE May go Low Within tRFC(min) After a PD Exit
BG80 X X No Fix Under Certain Low Temperature Conditions, Some Uncore
Performance Monitoring Events May Report Incorrect Results
Errata (Sheet 4 of 4)
Number Steppings Status ERRATA
C-2 K-0

Summary Tables of Changes
14 Specification Update
§
Specification Changes
Number Specification Changes
None for this revision of this specification update.
Specification Clarifications
Number Specification Clarifications
None for this revision of this specification update.
Documentation Changes
Number Documentation Changes
None for this revision of this specification update.

Specification Update 15
Identification Information
Identification Information
Component Identification via Programming
Interface
The Intel® Pentium® P6000 and U5000 Mobile Processor Series stepping can be
identified by the following processor signatures:
NOTES:
1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to
indicate whether the processor belongs to the Intel386®, Intel486®, Pentium®, Pentium Pro®, Pentium®
4, or Intel® Core™ processor family.
2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to
identify the model of the processor within the processor’s family.
3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM processor,
an OverDrive®processor, or a dual processor (capable of being used in a dual processor system).
4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register
after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device
ID register accessible through Boundary Scan.
5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register
after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID
register accessible through Boundary Scan.
6. The Stepping ID in bits [3:0] indicates the revision number of that model. See above table for the
processor stepping ID number in the CPUID information.
When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended
Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID
value in the EAX register. Note that the EDX processor signature value after reset is
equivalent to the processor signature output value in the EAX register.
Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX
registers after the CPUID instruction is executed with a 2 in the EAX register.
Intel® Pentium® P6000 and U5000 Mobile Processor Series can be identified by the
following register contents:
NOTES:
1. The Vendor ID corresponds to Bits 15:0 of the Vendor ID Register located at offset 00–01h in the PCI
function 0 configuration space.
2. The Device ID corresponds to Bits 15:0 of the Device ID Register located at Device 0 offset 02–03h in
the PCI function 0 configuration space.
3. The Revision Number corresponds to Bits 7:0 of the Revision ID Register located at offset 08h in the PCI
function 0 configuration space.
4. Correct Host Device ID requires firmware support.
Reserved Extended
Family1Extended
Model2Reserved Processor
Type3Family
Code4Model Number5Stepping ID6
31:28 27:20 19:16 15:14 13:12 11:8 7:4 3:0
00000000b 0010b 00b 0110 0101b xxxxb
Processor Stepping Vendor ID1Device ID2Revision ID3
C-2 8086h 0044h 12h
K-0 8086h 0044h 18h

Identification Information
16 Specification Update
Component Marking Information
The processor stepping can be identified by the following component markings:
NOTES:
1. Core Tjmax = 105°C, Graphics Tjmax = 100°C
2. Core Tjmax = 90°C, Graphics Tjmax = 85°C
3. Standard voltage with 35W TDP
4. Ultra low voltage with 18W TDP
5. The core frequency reported in the processor brand string is rounded to 2 decimal digits. (For example, core frequency of
2.6666, repeating 6, is reported as @2.67 in brand string. Core frequency of 2.5333, is reported as @2.53 in brand
string.)
6. Intel® GPMT is supported. GPMT frequency runs at 366 MHz.
7. This part supports C1, C1E, C3 and Deep Power Down Technology (code name C6 state)
8. This part supports C1, C1E and C3
§
Figure 1-1.Intel® Pentium® Mobile processor PGA Component Markings
Figure 1-2.Intel® Pentium® Mobile processor BGA Component Markings
Table 1-1. Processor Identification
QDF16/
S-Spec
Number
Processor
Number
Stepping/
Processor
Signature/Host
Device ID/ Host
Revision ID
L3 Cache
(MB)
Frequency Max Intel® Turbo Boost Technology
Frequency
LFM Frequency
Package
Notes
Core Base (GHz)
Graphics Base (MHz)
DDR3 (MT/s)
Single Core Turbo
Dual Core Turbo
Graphics Turbo
SLBWB P6000 C-2/
20652h/
0044h/12h 3MB
Core: 1.86 GHz
Gfx: 500 MHz
DDR3: 1066/800
MT/s
Core1: NA
Core2: NA
Gfx: 667 MHz 933 MHz PGA 2,3,5,
6,8
SLBUH U540
0
K-0/
20655h/
0044h/18h 3MB Core: 1.2 GHz
Gfx: 166 MHz
DDR3: 800 MT/s
Core1: NA
Core2: NA
Gfx: 500 MHz 667 MHz BGA 1,4,5,
6,7
yFor PGA
–GRP1LINE1 (limited to 18 char, 13 pt font): INTEL{M}{C}’YY
–GRP2LINE1 (limited to 15 char, 13 pt font): PROC#
–GRP3LINE1: (limited to 1 (ex) char, 15 pt font): {e4}
–GRP4LINE1 (limited to 9 char, 13 pt font): SSPEC
–GRP4LINE2 (limited to 9 char, 13 pt font): {FPO}
yFor BGA
–GRP1LINE1 (limited to 23 char, 13 pt font): i{M}{C}’YY SSPEC PROC#
–GRP2LINE1: (limited to 1 (ex) char, 15 pt font): {e1}
–GRP3LINE1 (limited to 12 char, 13 pt font): {FPO}

Specification Update 17
Errata
Errata
BG1. The Processor May Report a #TS Instead of a #GP Fault
Problem: A jump to a busy TSS (Task-State Segment) may cause a #TS (invalid TSS exception)
instead of a #GP fault (general protection exception).
Implication: Operation systems that access a busy TSS may get invalid TSS fault instead of a #GP
fault. Intel has not observed this erratum with any commercially-available software.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BG2. REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types May Use an Incorrect Data Size
or Lead to Memory-Ordering Violations
Problem: Under certain conditions as described in the Software Developers Manual section “Out-
of-Order Stores For String Operations in Pentium® 4, Intel Xeon, and P6 Family
Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to this
erratum fast string REP MOVS/REP STOS instructions that cross page boundaries from
WB/WC memory types to UC/WP/WT memory types, may start using an incorrect data
size or may observe memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the new page
memory type:
•UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
•WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
•WT there may be a memory ordering violation.
Workaround:Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status: For the steppings affected, see the Summary Tables of Changes.

Errata
18 Specification Update
BG3. Code Segment Limit/Canonical Faults on RSM May Be Serviced before Higher
Priority Interrupts/Exceptions and May Push the Wrong Address onto the
Stack
Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to
code execution, a #GP (General Protection Exception) fault is generated after all higher
priority Interrupts and exceptions are serviced. Due to this erratum, if RSM (Resume
from System Management Mode) returns to execution flow that results in a Code
Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher
priority Interrupt or Exception (e.g., NMI (Non-Maskable Interrupt), Debug
break(#DB), Machine Check (#MC), etc.). If the RSM attempts to return to a non-
canonical address, the address pushed onto the stack for this #GP fault may not match
the non-canonical address that caused the fault.
Implication: Operating systems may observe a #GP fault being serviced before higher priority
Interrupts and Exceptions. Intel has not observed this erratum on any commercially-
available software.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BG4. Performance Monitor SSE Retired Instructions May Return Incorrect Values
Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is used to track
retired SSE instructions. Due to this erratum, the processor may also count other types
of instructions resulting in higher than expected values.
Implication: Performance Monitoring counter SIMD_INST_RETIRED may report count higher than
expected.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.

Specification Update 19
Errata
BG5. Premature Execution of a Load Operation Prior to Exception Handler
Invocation
Problem: If any of the below circumstances occur, it is possible that the load portion of the
instruction will have executed before the exception handler is entered.
•If an instruction that performs a memory load causes a code segment limit
violation.
•If a waiting X87 floating-point (FP) instruction or MMX™ technology (MMX)
instruction that performs a memory load has a floating-point exception pending.
•If an MMX or SSE/SSE2/SSE3/SSSE3 extensions (SSE) instruction that performs a
memory load and has either CR0.EM=1 (Emulation bit set), or a floating-point Top-
of-Stack (FP TOS) not equal to 0, or a DNA exception pending.
Implication: In normal code execution where the target of the load operation is to write back
memory there is no impact from the load being prematurely executed, or from the
restart and subsequent re-execution of that instruction by the exception handler. If the
target of the load is to uncached memory that has a system side-effect, restarting the
instruction may cause unexpected system behavior due to the repetition of the side-
effect. Particularly, while CR0.TS [bit 3] is set, a MOVD/MOVQ with MMX/XMM register
operands may issue a memory load before getting the DNA exception.
Workaround:Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when
accessing side-effect memory and by ensuring that all code is written such that a code
segment limit violation cannot occur as a part of reading from side-effect memory.
Status: For the steppings affected, see the Summary Tables of Changes.
BG6. MOV To/From Debug Registers Causes Debug Exception
Problem: When in V86 mode, if a MOV instruction is executed to/from a debug registers, a
general-protection exception (#GP) should be generated. However, in the case when
the general detect enable flag (GD) bit is set, the observed behavior is that a debug
exception (#DB) is generated instead.
Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to
execute a MOV on debug registers in V86 mode, a debug exception will be generated
instead of the expected general-protection fault.
Workaround:In general, operating systems do not set the GD bit when they are in V86 mode. The
GD bit is generally set and used by debuggers. The debug exception handler should
check that the exception did not occur in V86 mode before continuing. If the exception
did occur in V86 mode, the exception may be directed to the general-protection
exception handler.
Status: For the steppings affected, see the Summary Tables of Changes.

Errata
20 Specification Update
BG7. Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR Image Leads
to Partial Memory Update
Problem: A partial memory state save of the 512-byte FXSAVE image or a partial memory state
restore of the FXRSTOR image may occur if a memory address exceeds the 64-KB limit
while the processor is operating in 16-bit mode or if a memory address exceeds the
4-GB limit while the processor is operating in 32-bit mode.
Implication: FXSAVE/FXRSTOR will incur a #GP fault due to the memory limit violation as expected
but the memory state may be only partially saved or restored.
Workaround:Software should avoid memory accesses that wrap around the respective 16-bit and
32-bit mode memory limits.
Status: For the steppings affected, see the Summary Tables of Changes.
BG8. Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM
Problem: After a return from SMM (System Management Mode), the CPU will incorrectly update
the LBR (Last Branch Record) and the BTS (Branch Trace Store), hence rendering their
data invalid. The corresponding data if sent out as a BTM on the system bus will also be
incorrect.
Note: This issue would only occur when one of the 3 above-mentioned debug support
facilities are used.
Implication: The value of the LBR, BTS, and BTM immediately after an RSM operation should not be
used.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
BG9. Single Step Interrupts with Floating Point Exception Pending May Be
Mishandled
Problem: In certain circumstances, when a floating point exception (#MF) is pending during
single-step execution, processing of the single-step debug exception (#DB) may be
mishandled.
Implication: When this erratum occurs, #DB will be incorrectly handled as follows:
•#DB is signaled before the pending higher priority #MF (Interrupt 16)
•#DB is generated twice on the same instruction
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.