Laird SSD40NBT Quick setup guide

SSD40NBT
HARDWARE INTEGRATION GUIDE
VERSION 4.5
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REVISION HISTORY
Version
Revision Date
Change Description
1.0 07/29/11 Initial Release Version (after preliminary versions)
Finalized mechanical drawings. Revisions to pin table (I/O)
1.1
08/03/11
Corrected Control Signal Timing diagram and text
1.2
08/05/11
Changed Power Type column of Pin Definitions table
1.3
08/28/11
Added PCM Timing information
1.4 10/06/11
Added Wi-Fi/BT power consumption numbers
Added note regarding the need for an external clock (pin 47)
Updated antenna port information
Added Appendix A: Schematic
Added SSD30AG/SSD40NBT Pin Comparison table
Added BT/AUX antenna port note
1.5
10/27/11
Added PCM defaults.
1.6 12/01/11
General edits including:
Revisions to pin table
Finalized Specifications data
Added “Integration Considerations” section
1.7 12/02/11
Updated the MSD40NBT schematic.
Updated Current Consumption numbers in the Specifications table.
Added series resistors information to the “Integration Considerations” section
Added product image
1.8
01/03/12
Updated Specification table
1.9
02/08/12
Add pin note and power notes
1.10
02/17/12
Updated Transmit Power numbers in the Specs table
2.0 4/17/12
Add AS/NZS (Australia, New Zealand) certifications
Changed the name of Pin 20
Updated AS/NZS links
2.2
6/29/12
Updated BT Transmit Power
2.3
7/11/12
Updated schematic, Certifications, Typical Receiver Sensitivity
2.4
8/15/12
Updated Operating Temperature
3.0 Updated format (converted to Laird)
Added “Note” with Figure 3
4.0 1/29/13 Updated Receive Sensitivity data
Re-added MIC frequency band and operating channel information.
4.1 1/30/13
Updated 5Ghz channel data and frequency data
Updated Operating Temperature data
4.2
17 May 2013
Added BT Priority Important note to the Block Diagram.
4.3 11 Oct 2013 Removed references to summitdata.com
Update mechanical drawing
4.4
26 Feb 2014
Added BT SIG certification section
4.5 25 March 2014 Added note regarding the following pins: CHIP_PWD_L, SYS_RST_L, BT_RST_L,
VDDIO_DR

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CONTENTS
SSD40NBT ..................................................................................................................................................... 1
Revision History............................................................................................................................................ 2
Contents ....................................................................................................................................................... 3
Scope............................................................................................................................................................. 4
Operational Description.............................................................................................................................. 4
Block Diagram.............................................................................................................................................. 5
Specifications ............................................................................................................................................... 6
Recommended Operating Conditions and DC Electrical Characteristics ............................................... 11
SDIO Timing Requirements .................................................................................................................. 12
UART Timing Requirements ................................................................................................................. 13
PCM Interface Timing .......................................................................................................................... 13
Control Signal Timing Requirements .................................................................................................... 18
Pin Definitions............................................................................................................................................ 19
SSD30AG and SSD40NBT Pin Comparison Table.................................................................................. 22
Electrical Considerations ...................................................................................................................... 23
Integration Considerations................................................................................................................... 25
Mechanical Specifications ......................................................................................................................... 26
Mounting................................................................................................................................................. 27
Recommendations: .............................................................................................................................. 28
RF Layout Design Guidelines..................................................................................................................... 29
Regulatory.................................................................................................................................................. 30
Certified Antennas ................................................................................................................................... 30
Documentation Requirements.................................................................................................................. 31
FCC ..................................................................................................................................................... 31
Industry Canada................................................................................................................................... 32
European Union................................................................................................................................... 33
Bluetooth SIG Approvals ........................................................................................................................... 36
Subsystem Combinations ......................................................................................................................... 36
Assumptions ............................................................................................................................................ 36
Additional Assistance ............................................................................................................................... 37
Appendix A: Schematic.............................................................................................................................. 38

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Scope
This document describes key hardware aspects of the Laird SSD40NBT radio module. This document is
intended to assist device manufacturers and related parties with the integration of this radio into their host
devices. Data in this document are drawn from a number of sources and include information found in the
Broadcom BCM4329data sheet issued in June of 2009.
Please contact Laird or visit the Laird to obtain the most recent version of this document:
http://www.lairdtech.com/Products/Embedded-Wireless-Solutions/Summit-Wi-Fi-Radio-Modules/SDC-
SSD40NBT/
OPERATIONAL DESCRIPTION
This device is an SDC-SSD40NBT radio module which supports IEEE
802.11a/b/g/n standards via an SDIO (Secure Digital Input/Output)
interface and Bluetooth version 2.1 via a serial UART (Universal
Asynchronous Receiver/Transmitter) interface. The radio operates in
unlicensed portions of the 2.4 GHz and 5 GHz radio frequency spectrum.
The device is compliant with IEEE 802.11a, 802.11b,802.11g, and
802.11n standards using Direct Sequence Spread Spectrum (DSSS),
Orthogonal Frequency Division Multiplexing (OFDM), and supports
Bluetooth 2.1 using Frequency Hopping Spread Spectrum (FHSS). The
device supports all 802.11a, 802.11b, 802.11g, 802.11n, and Bluetooth
data rates and automatically adjusts data rates and operational modes based on various environmental
factors.
When operating on channels in the UNII-2 and UNII-2 Extended bands that are in the 5GHz portion of the
frequency spectrum and are subject to Dynamic Frequency Selection requirements, the SDC-SSD40NBT fully
conforms to applicable regulatory requirements. In the event that specified types of radar are detected by the
network infrastructure, the SDC-SSD40NBT fully conforms to commands from the infrastructure for radar
avoidance.
The SDC-SSD40NBTis a System in Package (SiP) Quad Flat pack, No leads (QFN) module and interfaces to host
devices via a 56-padedge connector. The device is based on the Broadcom BCM4329chip which is an
integrated device providing a Media Access Controller (MAC), a Physical Layer Controller (PHY or baseband
processor), and fully integrated dual-band radio transceiver. To maximize operational range, the SDC-
SSD40NBT incorporates a 5 GHz power amplifier (PA) to increase transmit power. The frequency stability for
both 2.4 GHz (802.11b and 802.11g) and 5 GHz (802.11a) operation is +/- 20 ppm.
The SSD40NBT has its own RF shielding and does not require shielding provided by the host device into which
it is installed in order to maintain compliance with applicable regulatory standards. As such, the device may
be tested in a standalone configuration via an extender card.
The device buffers all data inputs so that it will comply with all applicable regulations even in the presence of
over-modulated input from the host device. Similarly, the SDC-SSD40NBT incorporates power regulation to
comply with all applicable regulations even when receiving excess power from the host device.
The SDC-SSD40NBT provides two diplexed antenna interfaces to support dual band transmit and receive
diversity. Supported host device antenna types include dipole and monopole antennas.
Note: When using a single antenna, it must be connected to the AUX port. BT does not function on the
Main port alone.

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Regulatory operational requirements are included with this document and may be incorporated into the
operating manual of any device into which the SDC-SSD40NBT is installed. The SDC-SSD40NBT is designed
for installation into mobile devices such as vehicle mount data terminals (which typically operate at distances
greater than 20 cm from the human body) and portable devices such as handheld data terminals (which
typically operate at distances less than 20 cm from the human body). See “Documentation Requirements” for
more information.
BLOCK DIAGRAM
Figure 1: Block Diagram
Note: Transmitter frequencies for Wi-Fi are 2412-2462 MHz and 5180-5805 MHz. Transmitter
frequencies for BT are 2402-2480 MHz.
Note: BT functions on the AUX port and not on the Main port. For Wi-Fi and BT single-antenna
implementations, the AUX port must be used.
IMPORTANT: When BT is transmitting high priority traffic (such as during a scan and/or when
sending audio traffic) Wi-Fi receive is sent to the main antenna port (even when set to
AUX only) .
When high priority transmission ends, Wi-Fi receive functionality returns to the AUX port (when set
to AUX only). For optimal Wi-Fi performance, we recommend that you populate both the Main
and the AUX ports with an antenna.

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SPECIFICATIONS
Table 1: Specifications
Feature
Description
Physical Interface
0.4mm pitch QFN (Quad Flat Pack, No Leads)
Wi-Fi Interface
1-bit or 4-bit Secure Digital I/O
Bluetooth Interface
Host Controller Interface (HCI) using High Speed UART
Main Chip
Broadcom BCM4329
Input Voltage Requirements
3.3 VDC ± 10% (core)
I/O Signaling Voltage
1.8 to 3.3 VDC ± 10%
Average Current Consumption,
VDDIO = 3.3 volts
(At maximum transmit power
setting)
Note:
Standby refers to the radio
operating in PM1 powersave
mode.
802.11a
(with BT in standby)
Transmit: 282 mA (931 mW)
Receive: 92 mA (304 mW)
Standby: TBD
802.11b
(with BT in standby)
Transmit: 314 mA (1036 mW)
Receive: 92 mA (304 mW)
Standby: TBD
802.11g
(with BT in standby)
Transmit: 288 mA (950 mW)
Receive: 92 mA (304 mW)
Standby: TBD
802.11n
(2.4 GHz) (with BT in standby)
Transmit: 292 mA (964 mW)
Receive: 92 mA (304 mW)
Standby: TBD
802.11n
(5 GHz) (with BT in standby)
Transmit: 270 mA (891 mW)
Receive: 92 mA (304 mW)
Standby: TBD
Bluetooth (with Wi-Fi in standby)
Transmit: TBD
Receive: TBD
Operating Temperature
-30° to 80°C (-22° to 176°F)
Operating Humidity
10 to 90% (non-condensing)
Storage Temperature
-30° to 85°C (-22° to 185°F)
Storage Humidity
10 to 90% (non-condensing)
Maximum Electrostatic Discharge
8 kV
Length
15.0 mm (0.59”)
Width
15.0 mm (0.59”)
Thickness
2.50 mm (0.1”)

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Feature
Description
Weight
1.0 g (0.04 oz.)
Mounting
See the “Mounting” section for more information.
Wi-Fi Media
Direct Sequence-Spread Spectrum (DSSS)
Complementary Code Keying (CCK)
Orthogonal Frequency Divisional Multiplexing (OFDM)
Bluetooth Media
Frequency Hopping Spread Spectrum (FSSS)
Wi-Fi Media Access Protocol
Carrier sense multiple access with collision avoidance (CSMA/CA)
Network Architecture Types
Infrastructure and ad hoc
Wi-Fi Standards
IEEE 802.11a, 802.11b, 802.11d, 802.11e, 802.11g, 802.11h,
802.11i, 802.11n
Bluetooth Standards
Bluetooth version 2.1 with Enhanced Data Rate
Wi-Fi Data Rates Supported
802.11a (OFDM) 6, 9, 12, 18, 24, 36, 48, 54 Mbps
802.11b (DSSS, CCK) 1, 2, 5.5, 11 Mbps
802.11g (OFDM) 6, 9, 12, 18, 24, 36, 48, 54 Mbps
802.11n (OFDM, MCS 0-7) 6.5, 7.2, 13.0, 14.4, 19.5, 21.7, 26.0,
28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2 Mbps
Modulation
BPSK @ 1, 6, 6.5, 7.2 and 9 Mbps
QPSK @ 2, 12, 13, 14.4,18, 19.5 and 21.7 Mbps
CCK @ 5.5 and 11 Mbps
16-QAM @ 24, 26, 28.9, 36, 39 and 43.3 Mbps
64-QAM @ 48, 52, 54, 57.8, 58.5, 65, and 72.2 Mbps
802.11n Spatial Streams
1 (Single Input, Single Output)
Bluetooth Data Rates Supported
1, 2, 3 Mbps
Bluetooth Modulation
GFSK@ 1 Mbps
Pi/4-DQPSK@ 2 Mbps
8-DPSK@ 3 Mbps
Regulatory Domain Support
FCC (Americas, Parts of Asia, and Middle East)
ETSI (Europe, Middle East, Africa, and Parts of Asia)
MIC (Japan) (formerly TELEC)
KC (Korea) (formerly KCC)
2.4 GHz Frequency Bands
ETSI
2.4 GHz to 2.483 GHz
FCC
2.4 GHz to 2.473 GHz
MIC
2.4 GHz to 2.495 GHz
KCC
2.4 GHz to 2.483 GHz
2.4 GHz Operating Channels
ETSI: 13 (3 non-overlapping)
FCC: 11 (3 non-overlapping)
MIC 14 (4 non-overlapping)
KCC: 13 (3 non-overlapping)

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Feature
Description
5 GHz Frequency Bands
ETSI
5.15 GHz to 5.35 GHz
5.47 GHz to 5.725 GHz
FCC
5.15 GHz to 5.35 GHz
5.47 GHz to 5.725 GHz
5.725 GHz to 5.82 GHz
MIC
(Japan)
5.15 GHz to 5.35 GHz
KC
5.15 GHz to 5.35 GHz
5.725 GHz to 5.82 GHz
5 GHz Operating Channels
ETSI: 19 non-overlapping
FCC: 23 non-overlapping
MIC (Japan): 8 non-overlapping
KC: 12 non-overlapping
Transmit Power
Note:
Transmit power varies
according to individual country
regulations. All values nominal,
+/-2 dBm.
Note:
Laird 40 series radios
support a single spatial stream
and 20 MHz channels only.
802.11a
6 Mbps
16 dBm (40 mW)
54 Mbps
14 dBm (25 mW)
802.11b
1 Mbps
17 dBm (50 mW)
11 Mbps
16 dBm (40 mW)
802.11g
6 Mbps
15 dBm (32 mW)
54 Mbps
13 dBm (20mW)
802.11n
(2.4 GHz)
6.5 Mbps (MCS0)
15 dBm (32 mW)
65 Mbps (MCS7)
11 dBm (13 mW)
802.11n
(5 GHz)
6.5 Mbps (MCS0)
16 dBm (40 mW)
65 Mbps (MCS7)
13 dBm (20 mW)
Bluetooth
1 Mbps
0 dBm (1mW)
2 Mbps
0 dBm (1mW)
3 Mbps
0 dBm (1mW)
Typical Receiver Sensitivity
Note:
All values nominal, +/-3
dBm.
802.11a:
6 Mbps -90 dBm
24 Mbps -84 dBm
54 Mbps -75 dBm (PER <= 10%)
802.11b:
1 Mbps -96 dBm
11 Mbps -89 dBm (PER <= 10%)
802.11g:
6 Mbps -90 dBm

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Feature
Description
24 Mbps -84 dBm
54 Mbps -74 dBm (PER <= 10%)
802.11n (2.4 GHz)
MCS0 Mbps -90 dBm
MCS4 Mbps -79 dBm
MCS7 Mbps -72 dBm
802.11n (5 GHz)
MCS0 Mbps
MCS4 Mbps
-89 dBm
-79 dBm
MCS7 Mbps -71 dBm
Bluetooth:
1 Mbps TBD
2 Mbps TBD
3 Mbps TBD
Operating Systems Supported
Windows Mobile 6.5
Windows Mobile 6.1
Windows Mobile 6.0
Windows Mobile 5.0
Windows Embedded CE 7.0
Windows Embedded CE 6.0 R3
Windows Embedded CE 6.0 R2
Windows Embedded CE 6.0
Windows Embedded CE 5.0
Linux, 2.6.x, 3.x.x kernel
Security
Standards
Wireless Equivalent Privacy (WEP)
Wi-Fi Protected Access (WPA)
IEEE 802.11i (WPA2)
Encryption
Wireless Equivalent Privacy (WEP, RC4 Algorithm)
Temporal Key Integrity Protocol (TKIP, RC4 Algorithm)
Advanced Encryption Standard (AES, Rijndael Algorithm)
Encryption Key Provisioning
Static (40-bit and 128-bit lengths)
Pre-Shared (PSK)
Dynamic
802.1X Extensible Authentication Protocol Types
EAP-FAST
EAP-TLS
EAP-TTLS
PEAP-GTC
PEAP-MSCHAPv2
PEAP-TLS
LEAP

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Feature
Description
Compliance
ETSI Regulatory Domain
EN 300 328 (Wi-Fi®)
EN 300 328 v1.7.1 (BT 2.1)
EN 301 489-1
EN 301 489-17
EN 301 893
EN 60950-1
EU 2002/95/EC (RoHS)
FCC Regulatory Domain
FCC 15.247 DTS – 802.11b/g (Wi-Fi) – 2.4 GHz & 5.8 GHz
FCC 15.407 UNII – 802.11a (Wi-Fi) – 2.4 GHz & 5.4 GHz
FCC 15.247 DSS – BT 2.1
Industry Canada
RSS-210 – 802.11a/b/g/n (Wi-Fi) – 2.4 GHz, 5.8 GHz, 5.2 GHz, and 5.4 GHz
RSS-210 – BT 2.1
AS/NZS
AS/NZS 4268:2008 +A1:2010 (RLAN device)
AS/NZS 4268:2008 +A1:2010 (BT device)
Certifications
Wi-Fi Alliance
802.11a, 802.11b, 802.11g , 802.11n
WPA Enterprise
WPA2 Enterprise
Cisco Compatible Extensions
(Version 4)
Bluetooth SIG Qualification
Warranty
Limited Lifetime
All specifications are subject to change without notice
Note: The BCM4329 has an internal power-on (POR) circuit. The device will be held in reset for a
maximum of 110 ms after VDDC and VDDIO have both passed the 0.6V threshold. Wait at least
110 ms after VDDC and VDDIO are available before initiating SDIO accesses. The external reset
signals are logically ORed with this POR. SO if either the internal POR or one of the external resets
are asserted, the device will be reset.

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RECOMMENDED OPERATING CONDITIONS AND DC ELECTRICAL CHARACTERISTICS
Table 2: Recommended Operating Conditions and DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VCC DC Supply Voltage 3.0 3.3 3.6 V
VDD_IO DC Supply Voltage (I/O) 1.8 - 3.3 V
VIL Low Level Input Voltage (VDDO = 3.3V) - - 0.8 V
V
IH
High Level Input Voltage (VDDO = 3.3V) 2.0 - - V
V
IL
Low Level Input Voltage (VDDO = 1.8V) - - 0.6 V
V
IH
High Level Input Voltage (VDDO = 1.8V) 1.1 - - V
V
OL
Low Level Output Voltage (100 µA load) - - 0.2 V
V
OH
High Level Output Voltage (-100 µA load) VDDIO – 0.2V - - V
IIL Low Current Input - 0.3 - µA
I
IH
High Current Input - 0.3 - µA
IOL Low Current Output
(VDDO = 3.3V, V
OL
= 0.4V) - - 3.0 mA
IOH High Current Output
(VDDO = 3.3V, V
OH
= 2.9V) - - 3.0 mA
C
IN
Input Capacitance - - 5 pF
BT UART Baud Rate 9600 bps
115.2 Kbps
(default coming
out of reset)
4 Mbps
bps/
Kbps/
Mbps

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SDIO Timing Requirements
Figure 2 and Table 3 illustrate SDIO default mode timing.
Figure 2: SDIO Default Mode Timing
Note: Timing is based on CL ≤40pF load on CMD and Data.
Table 3: SDIO Timing Requirements
Symbol
Parameter
Min
Typ
Max
Unit
SDIO CLK (All values are referred to minimum VIH and maximum VIL*)
fPP Frequency – Data Transfer mode 0 - 25 MHz
fOD Frequency – Identification mode 0 - 400 kHz
tWL Clock low time 10 - - ns
tWH Clock high time 10 - - ns
tTLH Clock rise time - - 10 ns
tTHL Clock low time - - 10 ns
Inputs: CMD, DAT (referenced to CLK)
tISU Input setup time 5 - - ns
tIH Input hold time 5 - - ns
Outputs: CMD, DAT (referenced to CLK)
tODLY Output delay time – Data Transfer mode 0 - 14 ns
tODLY Output delay time – Identification mode 0 - 50 ns
* min(Vih) = 0.7 x VDDIO and max(ViL) = 0.2 x VDDIO.

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UART Timing Requirements
Figure 3 displays UART timing.
Figure 3: UART Timing Requirements
Notes: The UART 4-wire interface supports Bluetooth 2.1 HCI Specification.
PCM data frames are sent MSB first.
Table 4: UART Timing Requirements
Reference
Description
Min.
Typ.
Max.
Unit
1 Delay time, BT_UART_CTS_N low to
UART_TXD valid - - 24 Baudout cycles
2 Setup time, BT_UART_CTS_N high
before midpoint of stop bit - - 10 ns
3 Delay time, midpoint of stop bit to
BT_UART_RTS_N high - - 2 Baudout cycles
PCM Interface Timing
PCM Defaults
Short Frame Sync, Master Mode
Short Frame Sync, Slave Mode
Long Frame Sync, Master Mode
Long Frame Sync, Slave Mode
PCM Defaults
SCO Routing PCM Interface Rate 512
Clock Mode Master Sample Interval 8khz
Sync Mode Master 16 bit mono
Frame Type Short

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Frame Sync, Master Mode
Figure 4: Short Frame Sync, Master Mode
Table 5: Short Frame Sync, Master Mode
Reference
Description
Min.
Typ.
Max.
Unit
1 PCM bit clock frequency 128 - 2048 kHz
2 PCM bit clock high time 128 - - ns
3 PCM bit clock low time 209 - - ns
4 Delay from BT_PCM_CLK rising edge to
BT_PCM_SYNC high - - 50 ns
5 Delay from BT_PCM_CLK rising edge to
BT_PCM_SYNC low - - 50 ns
6 Delay from BT_PCM_CLK rising edge to
data valid on BT_PCM_OUT - - 50 ns
7 Setup time for BT_PCM_IN before
BT_PCM_CLK falling edge 50 - - ns
8 Hold time for BT_PCM_IN after
BT_PCM_CLK falling edge 10 - - ns
9
Delay from falling edge of
BT_PCM_CLK during last bit period to
BT_PCM_OUT becoming high
impedance
- - 50 ns

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Short Frame Sync, Slave Mode
Figure 5: Short Frame Sync, Slave Mode
Table 6: Short Frame Sync, Slave Mode
Reference
Description
Min.
Typ.
Max.
Unit
1 PCM bit clock frequency 128 - 2048 kHz
2 PCM bit clock high time 209 - - ns
3 PCM bit clock low time 209 - - ns
4 Setup time for BT_PCM_SYNC before falling edge of
BT_PCM_BCLK 50 - - ns
5 Hold time for BT_PCM_SYNC after falling edge of BT_PCM_CLK 10 - - ns
6 Hold time of BT_PCM_OUT after BT_PCM_CLK falling time - - 175 ns
7 Setup time for BT_PCM_IN before BT_PCM_CLK falling edge 50 - - ns
8 Hold time for BT_PCM_IN after BT_PCM_CLK falling edge 10 - - ns
9 Delay from falling edge of BT_PCM_CLK during last bit period
to BT_PCM_OUT becoming high impedance - - 100 ns

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Long Frame Sync, Master Mode
Figure 6: Long Frame Sync, Master Mode
Table 7: Long Frame Sync, Master Mode
Reference
Description
Min.
Typ.
Max.
Unit
1 PCM bit clock frequency 128 - 2048 kHz
2 PCM bit clock high time 209 - - ns
3 PCM bit clock low time 209 - - ns
4 Delay from BT_PCM_CLK rising edge to BT_PCM_SYNC high
during first bit time - - 50 ns
5 Delay from BT_PCM_CLK rising edge to BT_PCM_SYNC low
during third bit time - - 50 ns
6 Delay from BT_PCM_CLK rising edge to data valid on
BT_PCM_OUT - - 50 ns
7 Setup time for BT_PCM_IN before BT_PCM_CLK falling edge 50 - - ns
8 Hold time for BT_PCM_IN after BT_PCM_CLK falling edge 10 - - ns
9 Delay from falling edge of BT_PCM_CLK during last bit period to
BT_PCM_OUT becoming high impedance - - 50 ns

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Long Frame Sync, Slave Mode
Figure 7: Long Frame Sync, Slave Mode
Table 8: Long Frame Sync, Slave Mode
Reference
Description
Min.
Typ.
Max.
Unit
1 PCM bit clock frequency 128 - 2048 kHz
2 PCM bit clock high time 209 - - ns
3 PCM bit clock low time 209 - - ns
4 Setup time for BT_PCM_SYNC before falling edge of
BT_PCM_CLK during first bit time 50 - - ns
5
Hold time for BT_PCM_SYNC after falling edge of BT_PCM_CLK
during second bit period.
Note:
BT_PCM_SYNC may go low any time from second bit
period to last bit period.
10 - - ns
6 Delay from rising edge of BT_PCM_CLK or BT_PCM_SYNC
(whichever is later) to data valid for first bit on BT_PCM_OUT - - 50 ns
7 Hold time of BT_PCM_OUT after BT_PCM_CLK falling edge - - 175 ns
8 Setup time for BT_PCM_IN before BT_PCM_CLK falling edge 50 - - ns
9 Hold time for BT_PCM_IN after BT_PCM_CLK falling edge 10 - - ns
10
Delay from falling edge of BT_PCM_CLK or BT_PCM_SYNC
(whichever is later) during last bit in slot to BT_PCM_OUT
becoming high impedance
- - 100

SSD40NBT
Hardware Integration Guide, version 4.5
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Laird Technologies
Control Signal Timing Requirements
Figure 4 displays Control Signal timing.
Figure 8: Control Signal Timing WLAN = ON, Bluetooth = ON
Note: This radio has an integrated power-on reset circuit that resets all circuits to a known power-on
state. Individual resets can also be driven by BT_RST_N or SYS_RST_N (an active-low, external reset
signal which can be used to externally force the device into a power-on reset state).

SSD40NBT
Hardware Integration Guide, version 4.5
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Laird Technologies
Pin Definitions
WLAN
Bluetooth
WLAN/Bluetooth
Table 9: Pin Definitions
Pin #
Pin Name
I/O
Voltage
Reference
Description
1 GND - Ground
2 GND - Ground
3 GND - Ground
4 GND - Ground
5 ANT_2 I/O
Antenna 2 (Auxiliary)
50 ohm coplanar wave guide
to antenna or antenna connector.
IMPORTANT:
BT functions on the Auxiliary (AUX) port and
not
on the
Main port. For Wi-Fi and BT single-antenna
implementations, the AUX port
must
be used.
6 GND - Ground
7 GND - Ground
8 GND - Ground
9 GND - Ground
10 ANT_1 I/O
Antenna 1 (Main)
50 ohm coplanar wave guide
to antenna or antenna connector.
IMPORTANT:
BT functions on the AUX port and
not
on the Main port. For
Wi-Fi and BT single-antenna implementations, the AUX port
must
be used.
11 GND - Ground
12 GND - Ground
13 GND - Ground
14 GND - Ground
15 GND - Ground
16 GND - Ground
17 GND - Ground
18 GND - Ground
19 BT_PCM_OUT O VDDIO PCM data output

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Laird Technologies
Pin #
Pin Name
I/O
Voltage
Reference
Description
20 BT_WAKE_B I VDDIO
Bluetooth device wake-up: Signal from the host to the SDC-
SSD40NBT indicating that the host requires attention.
Asserted: Bluetooth device must wake-up or remain awake
Deasserted: Bluetooth device may sleep when sleep criteria
are met
The polarity of this signal is software configurable and can
be asserted high or low.
Note:
The default is low but this is only applicable for
specific Bluetooth Sleep mode settings. By default, the radio
has “No Sleep Mode Set”.
21 BT_HOST_WAKE_B O VDDIO
Host Wake-up
Signal from the SDC-SSD40NBT to the host indicating that
the radio requires attention.
Asserted: Host device must wake-up or remain awake.
Deasserted: Host device may sleep when sleep criteria are
met
The polarity of this signal is software configurable and can
be asserted high or low.
Note:
The default is low but this is only applicable for
specific Bluetooth Sleep mode settings. By default, the radio
has “No Sleep Mode Set”.
22 RSVD O VDDIO Bluetooth LED Activity Indicator;
active high.
23 VDD3_3 - 3.3V Power
24 GND - Ground
25 BT_UART_CTS_N I VDDIO Clear-to-send signal for the Bluetooth UART interface, active
low.
26 BT_UART_RTS_N O VDDIO Request-to-send signal for the Bluetooth UART interface,
active low.
27 BT_UART_TXD O VDDIO Bluetooth UART Serial Output.
28 BT_UART_RXD I VDDIO Bluetooth UART Serial Input.
29 BT_PCM_SYNC I/O VDDIO
PCM sync signal
Default master (output);
can be configured slave (input)
30 BT_PCM_IN I VDDIO PCM data input
31 BT_PCM_CLK I/O VDDIO PCM clock
32 VDDIO VDDIO
1.8/3.3V I/O Power
This is the reference pins for all I/O signaling pins;
it accepts 1.8VDC or 3.3VDC from the host.
33 RSVD O VDDIO Reserved for WLAN LED activity indicator.
34 RSVD O VDDIO Reserved for Wake on Wireless.