Laird BT800 series Quick setup guide

Bluetooth v4.0 Dual-Mode USB HCI Module
Hardware Integration Guide (HIG)
Version 0.2
BT800 Series
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REVISION HISTORY
Revision
Date
Changes
Version 0.1
7/8/2013
Preliminary
Version 0.2
10/07/13
Initial –KP only

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CONTENTS
Revision History ..........................................................................................................................2
Contents .....................................................................................................................................3
1Scope ....................................................................................................................................5
2Operational Description.........................................................................................................5
Features & Benefits ............................................................................................................................ 52.1
Application Areas.............................................................................................................................. 52.2
3Module picture ......................................................................................................................6
4Block Diagram and Descriptions ............................................................................................7
Main Chip: CSR8510A10 ................................................................................................................... 74.1
Antenna............................................................................................................................................... 74.2
Band Pass Filter ................................................................................................................................... 74.3 EEPROM ............................................................................................................................................... 74.4
Crystal .................................................................................................................................................. 74.5
5Specifications ........................................................................................................................8
6Pin definitions .......................................................................................................................9
7DC Electrical Characteristic..................................................................................................11
8RF Characteristics ................................................................................................................13
9Interface ..............................................................................................................................14
PIO (Programmable I/O Ports) ...................................................................................................... 149.1
WLAN Coexistence Interface........................................................................................................ 149.2
USB Interface .................................................................................................................................... 149.3
PCM Interface .................................................................................................................................. 159.4
GCI Interface.................................................................................................................................... 179.5
Slots and Sample Formats .............................................................................................................. 179.6
PCM Timing Information ................................................................................................................... 189.7
PCM Slave Timing ............................................................................................................................ 209.8
PCM Slave Mode Timing Parameters .......................................................................................... 209.9
PCM_CLK and PCM_SYNC Generation ...................................................................................... 229.10
PCM Configuration.......................................................................................................................... 229.11
Digital Audio Interface (I²S)............................................................................................................ 229.12
10 Power Control and Regulation .............................................................................................25
USB Linear Regulator ....................................................................................................................... 2510.1
High-voltage Linear Regulator ...................................................................................................... 2510.2
Low-voltage VDD_DIG Linear Regulator..................................................................................... 2610.3
Low-voltage VDD_RADIO Linear Regulator................................................................................ 2610.4
Low-voltage VDD_AUX Linear Regulator .................................................................................... 2610.5
Voltage Regulator Enable and Reset.......................................................................................... 2610.6
Power Sequencing .......................................................................................................................... 2610.7
11 Antenna performance ..........................................................................................................27
12 Mechanical Dimensions and Land Pattern ............................................................................29
13 Implementation note ...........................................................................................................30
PCB Layout on Host PCB ................................................................................................................ 30
13.1
14 Application Note for Surface Mount Modules.......................................................................32
Introduction ...................................................................................................................................... 3214.1
Shipping tray..................................................................................................................................... 3214.2
Reflow Parameters .......................................................................................................................... 3214.3
15 FCC and IC Regulatory .........................................................................................................34
Documentation Requirements ..................................................................................................... 3415.1

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16 European Union Regulatory .................................................................................................38
17 EU Declarations of Conformity.............................................................................................38
BT800 / BT810 / BT820 ....................................................................................................................... 3817.1
18 Ordering Information...........................................................................................................39
General Comments ........................................................................................................................ 3918.1
19 Bluetooth SIG Approvals ......................................................................................................40
TBC 40

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1SCOPE
This document describes key hardware aspects of the Laird BT800 Bluetooth HCI/HID module. This
document is intended to assist device manufacturers and related parties with the integration of this
module into their host devices. Data in this document are drawn from a number of sources including
data sheets for the CSR CSR8510.
Because the BT800 is currently in development stage, this document is preliminary and the information
in this document is subject to change. Please contact Laird Technologies or visit the Laird website at
www.Lairdtech.com to obtain the most recent version of this document.
2OPERATIONAL DESCRIPTION
The BT800 series of USB HCI devices are designed to meet the needs of OEMs adding robust Bluetooth
connectivity and using embedded Bluetooth stacks within these products.
Leveraging the market-leading CSR 8510 chipset, the BT800 series provides exceptionally low power
consumption with outstanding range. Supporting the latest Bluetooth v4.0 Specification with EDR
(Enhanced Data Rate), the Laird BT800 series enables OEMs to accelerate their development time for
leveraging either Classic Bluetooth or Bluetooth Low Energy (BLE) into their operating system based
devices.
With a tiny footprint as small as 8.5 x 13 mm, yet output power at 8 dBm, these modules are ideal for
applications where designers need high performance in minimal size. For maximum flexibility in systems
integration, the modules are designed to support a full speed USB interface plus GPIO and additionally
I2S and PCM audio interfaces.
These modules present an HCI interface and have native support for Windows and Linux Bluetooth
software stacks. All BT800 series devices are fully qualified as Bluetooth Controller Subsystem products.
This also allows designers to integrate their existing pre-approved Bluetooth Host and Profile subsystem
stacks to gain a Bluetooth END product approval for their products.
The BT800 series is engineered to provide excellent RF performance with integrated antenna and
additional band pass filters. It further reduces regulatory and testing requirements for OEMs and ensures
a hassle free development cycle. As an additional benefit of the BT8000 series, Laird has implemented
CSR’s HID (Human Interface Device) Proxy Mode enabling out of the box HID connectivity for pointing
devices and / or keyboard functionality, requiring zero host device software or configuration.
A fully featured, low-cost developer’s kit is available for prototyping, debug and integration testing of
the BT800 series modules and further reduces risk and time in development cycles.
Features & Benefits
2.1
Application Areas
2.2
Bluetooth v4.0 - Dual mode
-Classic Bluetooth and Bluetooth Low Energy
Compact footprint
2-wire and 3-wire Wi-Fi coexistence scheme
High antenna radiation gain and efficiency
Good interference rejection for multi-com system
(GSM/WCDMA)
Class 1 output –8 dBm
USB, GPIO, I2S, and PCM
Industrial Temperature Range
Medical devices
ePOS terminals
Barcode scanners
Industrial Cable Replacement
M2M Connectivity
Automotive Diagnostic Equipment
Personal Digital Assistants (PDA)
Bluetooth HID device (keyboard,
mouse, and joystick)

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64 k EEPROM support for HID Proxy mode
Bluetooth Controller subsystem
FCC, IC, CE, and MIC approvals
3MODULE PICTURE
TBA

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4BLOCK DIAGRAM AND DESCRIPTIONS
Figure 1: BT800 module block diagram
Main Chip: CSR8510A104.1
BT800 is based on CSR8510A10 dual mode chip. The chip is a single-chip radio with on chip LDO
regulators and baseband IC for Bluetooth 2.4 GHz systems including EDR to 3 Mbps. Dedicated signal
and baseband processing is included for full Bluetooth operation. The chip provides SPI/PCM and USB
interfaces. Up to 4 general purpose I/Os are available for general usage, such as Wi-Fi coexistence or
general indicators.
Antenna4.2
Antenna is a ceramic monopole chip antenna.
Band Pass Filter4.3
The band pass filter filters the out of band emissions from the transmitter to meet the specific regulations
for type approvals of various countries.
EEPROM4.4
There are 64 k bits EEPROM embedded on the BT800 module which can be used to store customizable
parameters, such as maximum TX power, PCM configuration, USB product ID, USB vendor ID and USB
product description. With that, the BT800 module can support HID/HCI Proxy Mode.
Crystal4.5
The embedded 26 MHz crystal is used for generating the clock for the entire module.

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5SPECIFICATIONS
CATEGORIES
FEATURE
IMPLEMENTATION
Wireless
Specification
Bluetooth®
V4.0 Dual Mode
Frequency
2.402 - 2.480 GHz
Max Transmit
Power
Class 1
+8dBm from antenna
Receive Sensitivity
-89dBm
Range
Circa 100 meters
Data Rates
Up to 3 Mbps (over the air)
Host Interface
USB
Full Speed USB 2.0
GPIO
4 configurable lines
(1.8V/3.3V configurable by VDD_PADS)
Operational
Modes
HCI
Host Controller Interface over USB
HID Proxy Mode
Human Interface Device
EEPROM
2-wire
64K bits
Coexistence
802.11 (Wi-Fi)
3 wire CSR schemes supported
(Unity-3;Unity-3e and Unity+)
Supply Voltage
Supply
5V +/-10% (Note:1)
Power
Consumption
Current
Idle (sleep) < TBC mA
Connectable & Discoverable < TBC mA
Antenna Option
Internal
Multilayer ceramic antenna with up to 41% efficiency.
Physical
Dimensions
8.5 x 13 x 1.6 mm (BT800 - Module)
9.3 x 13.05 x 2.3mm (BT810 –Module BG)
16 x 43 x 11 (BT820 –USB Dongle)
Environmental
Operating
-40C to +85C
Storage
-40C to +85C
Miscellaneous
Lead Free
Lead-free and RoHS compliant
Warranty
1 Year
Approvals
Bluetooth®
Controller Subsystem Approved
FCC / IC / CE /
MIC
All BT800 series
Note: Different DC power selections on BT800 are detailed in “

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Implementation note.”
6PIN DEFINITIONS
#
Pin Name
I/O
Supply
Domain
Description
1
SPI_PCM#_SEL
Input with weak
internal pull-down
VDD_PADS
High switches SPI/PCM lines to SPI,
Low switches SPI/PCM lines to
PCM/PIO
2
VDD_HOST
Power supply
(3.1V-3.6V)
USB system positive supply
3
GND
GND
-
Ground
4
USB+
Bidirectional
VDD_HOST
USB data plus with selectable
internal 1.5kΩpull-up resistor
5
USB-
Bidirectional
VDD_HOST
6
GND
GND
-
Ground
7
VREG_IN_USB
Power supply
Analogue
regulator
input
Input to USB regulator. Connect to
external
USB bus supply, e.g. USB_VBUS
8
VREG_EN_RST#
Input with strong
internal pull-down
VDD_PADS
Take high to enable internal
regulators. Also acts as active low
reset. Maximum voltage is
VDD_PADS.
Note: USB regulator is always
enabled and not controlled by
this pin
9
VREG_IN_HV
Analogue regulator
input / output
3.3V
Input to internal high-voltage
regulator to 1.8V regulator, 3.3V
output from USB regulator.
10
VREG_OUT_HV
Analogue regulator
input / output
1.8V
Output from internal high-voltage
to 1.8V regulator. Input to second
stage internal regulators.
11
GND
GND
-
Ground
12
GND
GND
-
Ground
13
GND
GND
-
Ground
14
GND
GND
-
Ground
15
GND
GND
-
Ground
16
GND
GND
-
Ground

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#
Pin Name
I/O
Supply
Domain
Description
17
N/C
-
-
This pin is reserved for future used.
No connection.
18
GND
GND
-
Ground
19
PCM_SYNC/
SPI_CS#/
PIO23
Bidirectional,
tri-state, with weak
internal pull-down
VDD_PADS
PCM synchronous data sync SPI
chip select, active low
Programmable input/output line
20
PCM_CLK/
SPI_CLK/
PIO24
Bidirectional,
tri-state, with weak
internal pull-down
VDD_PADS
PCM synchronous data clock
SPI clock
Programmable input/output line
21
PCM_IN/
SPI_MOSI/
PIO21
Input, tri-state, with
weak internal pull-
down
VDD_PADS
PCM synchronous data input
SPI data input
Programmable input/output line
22
PCM_OUT/
SPI_MISO/
PIO22
Output, tri-state, with
weak internal pull-
down
VDD_PADS
PCM synchronous data output
SPI data output
Programmable input/output line
23
PIO0/
WLAN_ACTIVE
Bidirectional,
tri-state, with weak
internal pull- down
VDD_PADS
Programmable input/output line
24
GND
GND
-
Ground
25
PIO1/
BT_PIRORITY
Bidirectional,
tri-state, with weak
internal pull- down
VDD_PADS
Programmable input/output line
26
PIO2/
BT_ACTIVE
Bidirectional,
tri-state, with weak
internal pull- down
VDD_PADS
Programmable input/output line
27
VDD_PADS
Power supply
(1.7V-3.6V)
Positive supply for digital I/O pads
28
PIO5
Bidirectional,
tri-state, with weak
internal pull- down
VDD_PADS
Programmable input/output line

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7DC ELECTRICAL CHARACTERISTIC
Table 1: Absolute maximum ratings
Rating
Min
Max
Unit
Storage temperature
-40
+85
⁰C
VREG_IN_USB
-0.2
5.75
V
VREG_IN_HV
-0.2
4.9
V
VDD_HOST
-0.2
3.7
V
VDD_PADS
-0.2
3.7
V
Other terminal voltages
VSS - 0.4V
VDD + 0.4 V
V
Table 2: Recommended operating conditions
Rating
Min
Max
Unit
Operating temperature
-40
+85
⁰C
VREG_IN_USB
4.5
5.5
V
VREG_IN_HV
3.1
3.6
V
VDD_HOST
3.1
3.6
V
VDD_PADS
1.7
3.6
V
Table 3: USB Linear Regulator
Rating
Min
Typ
Max
Unit
Input voltage (VREG_IN_USB)
4.5
5.0
5.5
V
Output voltage (VREG_IN_HV)
3.2
3.3
3.4
V
Output current
-
-
150
mA
Table 4: High-voltage Linear Regulator
Normal Operation
Min
Typ
Max
Unit
Input voltage (VREG_IN_HV)
3.1
3.3
3.6
V
Output voltage (VREG_OUT_HV)
1.75
1.85
1.95
V
Temperature coefficient
-200
-
200
ppm/⁰C
Output noise (frequency range 100Hz
to100kHz)
-
-
0.4
mV rms
Settling time (settling ti within 10% of
finalvalue)
-
-
5
µs
Output current
-
-
100
mA
Quiescent current (excluding load, Iload
<1mA)
30
40
60
µA
Low-power Mode
Quiescent current
14
18
23
µA

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(excluding load, Iload <100µA)
Table 5: Digital I/O Characteristics
Normal Operation
Min
Typ
Max
Unit
Input Voltage
VIL input logic level low
-0.4
-
0.4
V
VIH input logic level high
0.7 x
VDD
-
VDD +
0.4
V
Output Voltage
VOL output logic level low, IOL =
4.0mA
-
-
0.4
V
VOH output logic level high, IOL =
4.0mA
0.75 x
VDD
-
-
V
Input and Tristate Currents
Strong pull-up
-150
-40
-10
µA
Strong pull-down
10
40
150
µA
Weak pull-up
-5
-1.0
-0.33
µA
Weak pull-down
0.33
1.0
5.0
µA
CI input capacitance
1.0
-
5.0
pF
Table 6: Current Consumption
Normal Operation
Peak (8 dBm)
AVG
Unit
Idle
5
mA
USB Suspend
200
µA
Inguiry
73
51
mA
File Transfer
73
58
mA
LE Connected (Master)
74
mA
LE Scan (Master)
48
mA

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8RF CHARACTERISTICS
Table 7: Receiver Characteristics
RF Characteristics, VDD = 3.3V @ room
temperature unless otherwise specified
Min
Typ.
Max
BT. Spec.
Unit
Maximum RF Transmit Power
8
10
20
dBm
RF power variation over temperature
range
1.5
-
dB
RF power variation over supply voltage
range
0.2
-
dB
RF power variation over BT band
2
-
dB
RF power control range
-21
8
-
dBm
20 dB band width for modulated carrier
1000
kHz
ACP
F = F0 ± 2MHz
-20
F = F0 ± 3MHz
-40
F = F0 > 3MHz
-40
Drift rate
10
+/-25
kHz
ΔF
1avg
165
140<175
kHz
ΔF1
max
168
140<175
kHz
ΔF2avg / ΔF
1avg
0.9
>=0.8
Table 8: BDR and EDR receiver sensitivity
RF Characteristics, VDD = 3.3V @ room
temp.
Packet
type
Min
Typ
Max
BT. Spec.
Unit
Sensitivity for 0.1% BER
DH1
-89
-70
dBm
DH3
-89
dBm
DH5
-89
dBm
2-DH5
-92
dBm
3-DH5
-85
dBm
Sensitivity variation over BT band
All
2
dB
Sensitivity variation over temperature
range
All
TBD
dB

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9INTERFACE
PIO (Programmable I/O Ports)9.1
See the Device Terminal Functions section for the list of supplies to the PIOs.
PIO lines are configured through software to have either weak or strong pull-ups or pull-downs. All PIO
lines are configured as inputs with weak pull-downs at reset and have additional individual bus keeper
configuration.
WLAN Coexistence Interface9.2
Dedicated hardware is provided to implement a variety of WLAN coexistence schemes. There is
support for:
Channel skipping AFH
Priority signalling
Channel signalling
Host passing of channel instructions
The BT800 supports the WLAN coexistence schemes:
Unity-3
Unity-3e
Unity+
For more information see Bluetooth and IEEE 802.11 b/g Co-existence Solutions Overview.
USB Interface9.3
BT800 has a full-speed (12 Mbps) USB interface for communicating with other compatible digital devices.
The USB interface on BT800 acts as a USB peripheral, responding to requests from a master host
controller.
BT800 supports the Universal Serial Bus Specification, Revision v2.0 (USB v2.0 Specification) and USB
Battery Charging Specification, available from http://www.usb.org. For more information on how to
integrate the USB interface on BT800, see the Bluetooth and USB Design Considerations Application
Note.
As well as describing USB basics and architecture, the application note describes:
Power distribution for high and low bus-powered configurations
Power distribution for self-powered configuration, which includes USB VBUS monitoring
USB enumeration
Electrical design guidelines for power supply and data lines, as well as PCB tracks and effects of
ferrite beads
USB suspend modes and Bluetooth low-power modes:
Global suspend
Selective suspend, includes remote wake
Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend
Suspend mode current draw
PIO status in suspend mode

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Resume, detach and wake PIOs
Battery charging from USB: dead battery provision, charge currents, charging in suspend modes
and USB
VBUS voltage consideration
USB termination when interface is not in use
internal modules, certification and non-specification compliant operation
PCM Interface9.4
The audio PCM interface on the BT800 supports:
Continuous transmission and reception of PCM encoded audio data over Bluetooth.
Processor overhead reduction through hardware support for continual transmission and reception
of PCM data.
A bidirectional digital audio interface that routes directly into the baseband layer of the firmware.
It does not pass through the HCI protocol layer.
Hardware on BT800for sending data to and from a SCO connection.
Up to 3 SCO connections on the PCM interface at any one time.
PCM interface master, generating PCM_SYNC and PCM_CLK.
PCM interface slave, accepting externally generated PCM_SYNC and PCM_CLK.
Various clock formats including:
Long Frame Sync
Short Frame Sync
GCI timing environments
13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats.
Receives and transmits on any selection of 3 of the first 4 slots following PCM_SYNC.
The PCM configuration options are enabled by setting PSKEY_PCM_CONFIG32.
9.4.1 PCM Interface Master/Slave
When configured as the master of the PCM interface, BT800generates PCM_CLK and PCM_SYNC.
Figure 2: PCM Interface Master

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Figure 3: PCM Interface Slave
9.4.2 L ong Frame Sync
Figure 4: Long Frame Sync (Shown with 8-bit Companded Sample)
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or
samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When
BT800 is configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8 bits long.
When BT800 is configured as PCM Slave, PCM_SYNC is from 1 cycle PCM_CLK to half the PCM_SYNC
rate.
BT800 samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge.
PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on
the rising edge.
9.4.3 S hort Frame S y nc
In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is
always 1 clock cycle long.
Figure 5: Short Frame Sync (Shown with 16-bit Sample)

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As with Long Frame Sync, BT800 samples PCM_IN on the falling edge of PCM_CLK and transmits
PCM_OUT on the rising edge. PCM_OUT is configurable as high impedance on the falling edge of
PCM_CLK in the LSB position or on the rising edge.
9.4.4 Multi-slot Operation
More than 1 SCO connection over the PCM interface is supported using multiple slots. Up to 3 SCO
connections are carried over any of the first 4 slots.
Figure 6: Multi-slot Operation with 2 Slots and 8-bit Companded Samples
GCI Interface9.5
BT800 is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. The two 64 kbps B
channels are accessed when this mode is configured.
Figure 7: Multi-slot Operation
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz.
Slots and Sample Formats9.6
BT800 receives and transmits on any selection of the first 4 slots following each sync pulse. Slot durations
are either 8 or 16 clock cycles:
8 clock cycles for 8-bit sample formats.
16 clock cycles for 8-bit, 13-bit or 16-bit sample formats.
BT800 supports:

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13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats.
A sample rate of 8ksps.
Little or big endian bit order.
For 16-bit slots, the 3 or 8 unused bits in each slot are filled with sign extension, padded with zeros
or a programmable 3-bit audio attenuation compatible with some codecs.
Figure 8: 16-bit Slot Length and Sample Formats
PCM Timing Information 9.7
Table 9: PCM Timing information.
Symbol
Parameter
Min
Typ
Max
Unit
fmclk
PCM_CLK frequency
4MHz DDS generation.
Frequency selection is
programmable.
-
128
-
kHz
256
512
48MHz DDS generation.
Frequency selection is
programmable.
2.9
-
-
kHz
-
PCM_SYNC frequency for SCO connection
-
8
-
kHz
tmclkh
(a)
PCM_CLK high
4MHz DDS generation
980
-
-
ns
tmclkl a)
PCM_CLK low
4MHz DDS generation
730
-
-
ns
-
PCM_CLK jitter
48MHz DDS generation
-
-
21
ns
pk-p

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k
tdmclksy
nch
Delay time from
PCM_CLK high to
PCM_SYNC high
4MHz DDS generation
-
-
20
ns
48MHz DDS generation
-
-
40.83
ns
tdmclkpo
ut
Delay time from PCM_CLK high to valid PCM_OUT
-
-
20
ns
tdmclklsy
ncl
Delay time from
PCM_CLK low to
PCM_SYNC low (long
frame sync only)
4MHz DDS generation
-
-
20
ns
48MHz DDS generation
-
-
40.83
ns
(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.
Table 10: PCM Master Mode Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
tdmclkhsyncl
Delay time from
PCM_CLK high to
PCM_SYNC low
4MHz DDS generation
-
-
20
ns
48MHz DDS generation
-
-
40.83
ns
tdmclklpoutz
Delay time from PCM_CLK low to PCM_OUT
high impedance
-
-
20
ns
tdmclkhpout
z
Delay time from PCM_CLK high to PCM_OUT
high impedance
-
-
20
ns
tsupinclkl
Set-up time for PCM_IN valid to PCM_CLK low
20
-
-
ns
thpinclkl
Hold time for PCM_CLK low to PCM_IN invalid
0
-
-
ns
Figure 9: PCM Master Timing Long Frame Sync

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Figure 10: PCM Master Timing Short Frame Sync
PCM Slave Timing9.8
Symbol
Parameter
Min
Typ
Max
Unit
fsclk
PCM clock frequency (Slave mode:
input)
64
-
2048
kHz
fsclk
PCM clock frequency (GCI mode)
128
-
4096
kHz
tsclkl
PCM_CLK low time
200
-
-
ns
tsclkh
PCM_CLK high time
200
-
-
ns
PCM Slave Mode Timing Parameters9.9
Symbol
Parameter
Min
Ty
p
Max
Unit
thsclksync
h
Hold time from PCM_CLK low to PCM_SYNC high
2
-
-
ns
tsusclksyn
ch
Set-up time for PCM_SYNC high to PCM_CLK low
20
-
-
ns
tdpout
Delay time from PCM_SYNC or PCM_CLK, whichever is
later, to valid PCM_OUT data (long frame sync only)
-
-
15
ns
tdsclkhpo
ut
Delay time from CLK high to PCM_OUT valid data
-
-
15
ns
tdpoutz
Delay time from PCM_SYNC or PCM_CLK low, whichever
is later, to PCM_OUT data line high impedance
-
-
20
ns