Laird BT800 series Quick setup guide

Bluetooth v4.0 Dual-Mode USB HCI Module
Hardware Integration Guide
Version 1.5
BT800-ST
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REVISION HISTORY
Revision
Date
Changes
1.0
04 Sept 2013
Initial Release –Preliminary ST HIG
1.1
30 Sept 2014
Updated certification information (FCC, IC, CE, BT SIG)
1.2
07 Oct 2014
Updated Declaration of Conformity
1.3
14 Oct 2014
Removed X +/-1.3mm references
1.4
03 Dec 2014
Updated the Power Control and Regulation section.
1.5
02 July 2015
Added Tape/Reel (T/R) information

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CONTENTS
1Scope.......................................................................................................................................................4
2Operational Description ........................................................................................................................4
3Block Diagram and Descriptions...........................................................................................................5
4Specifications .........................................................................................................................................6
5Pin Definitions........................................................................................................................................7
6DC Electrical Characteristic....................................................................................................................9
7RF Characteristics .................................................................................................................................10
8Interface ...............................................................................................................................................11
8.1 PIO .................................................................................................................................................11
8.2 WLAN Coexistence Interface ..........................................................................................................11
8.3 USB Interface .................................................................................................................................12
8.4 PCM Interface ................................................................................................................................12
8.5 GCI Interface..................................................................................................................................14
8.6 Slots and Sample Formats...............................................................................................................15
8.7 PCM Timing Information .................................................................................................................16
8.8 PCM Slave Timing ..........................................................................................................................17
8.9 PCM Slave Mode Timing Parameters ..............................................................................................18
8.10 PCM_CLK and PCM_SYNC Generation ..........................................................................................19
8.11 PCM Configuration ........................................................................................................................20
8.12 Digital Audio Interface (I²S).............................................................................................................20
9Power Control and Regulation ...........................................................................................................22
9.1 USB Linear Regulator......................................................................................................................22
9.2 High-voltage Linear Regulator ........................................................................................................23
9.3 Voltage Regulator Enable and Reset ...............................................................................................23
9.4 Power Sequencing..........................................................................................................................23
10 Antenna Performance on BT800 ........................................................................................................24
11 Mechanical Dimensions and Land Pattern.........................................................................................26
11.1 BT800 Mechanical Drawing............................................................................................................26
11.2 BT800-ST Mechanical Drawing.......................................................................................................27
12 Implementation Note ..........................................................................................................................28
12.1 PCB Layout on Host PCB ................................................................................................................28
13 Application Note for Surface Mount Modules ..................................................................................30
13.1 Introduction ...................................................................................................................................30
13.2 Shipping Tray .................................................................................................................................30
13.3 Reflow Parameters .........................................................................................................................31
13.4 Tape/Reel (T/R) ...............................................................................................................................32
14 FCC and IC Regulatory .........................................................................................................................33
14.1 Documentation Requirements ........................................................................................................33
15 European Union Regulatory ...............................................................................................................36
15.1 EU Declarations of Conformity .......................................................................................................36
15.2 BT800 / BT800-ST / BT820..............................................................................................................36
16 Ordering Information..........................................................................................................................37
16.1 General Comments ........................................................................................................................37
17 Bluetooth SIG Approvals .....................................................................................................................37
17.1 Application Note: Subsystem Combinations ...................................................................................37
17.2 Additional Assistance .....................................................................................................................39

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1SCOPE
This document describes key hardware aspects of the Laird BT800 Bluetooth HCI/HID module. This document is
intended to assist device manufacturers and related parties with the integration of this module into their host
devices. Data in this document are drawn from a number of sources including data sheets for the CSR8510.
2OPERATIONAL DESCRIPTION
The BT800 series of USB HCI devices are designed to meet the needs of OEMs adding robust
Bluetooth connectivity and using embedded Bluetooth stacks within these products.
Leveraging the market-leading CSR8510 chipset, the BT800 series provides exceptionally low
power consumption with outstanding range. Supporting the latest Bluetooth v4.0 Specification
with EDR (Enhanced Data Rate), the Laird BT800 series enables OEMs to accelerate their
development time for leveraging either Classic Bluetooth or Bluetooth Low Energy (BLE) into
their operating system based devices.
With a tiny footprint as small as 8.5 x 13 mm, yet output power at 8 dBm, these modules are
ideal for applications where designers need high performance in minimal size. For maximum
flexibility in systems integration, the modules are designed to support a full speed USB
interface plus GPIO and additionally I2S and PCM audio interfaces.
These modules present an HCI interface and have native support for Windows and Linux Bluetooth software stacks.
All BT800 series devices are fully qualified as Bluetooth Controller Subsystem products. This also allows designers to
integrate their existing pre-approved Bluetooth Host and Profile subsystem stacks to gain a Bluetooth END product
approval for their products.
The BT800 series is engineered to provide excellent RF performance with integrated antenna and additional band
pass filters. It further reduces regulatory and testing requirements for OEMs and ensures a hassle free development
cycle. As an additional benefit of the BT800 series, Laird has implemented CSR’s HID (Human Interface Device) Proxy
Mode enabling out of the box HID connectivity for pointing devices and / or keyboard functionality, requiring zero
host device software or configuration.
A fully featured, low-cost developer’s kit is available for prototyping, debug, and integration testing of the BT800
series modules and further reduces risk and time in development cycles.
Note: Laird also offers a BT800-ST version which is a trace pin variant of the BT800 for use with an external
antenna.
Features and Benefits
Application Areas
Bluetooth v4.0 - Dual mode (Classic Bluetooth and BLE)
Compact footprint
2-wire and 3-wire Wi-Fi coexistence scheme
High antenna radiation gain and efficiency
Good interference rejection for multi-com system (GSM/WCDMA)
Class 1 output –8 dBm
USB, GPIO, I2S, and PCM
Industrial Temperature Range
64 k EEPROM support for HID Proxy mode
Bluetooth Controller subsystem
FCC, IC, CE, and MIC approvals
Medical devices
ePOS terminals
Barcode scanners
Industrial Cable Replacement
M2M Connectivity
Automotive Diagnostic Equipment
Personal Digital Assistants (PDA)
Bluetooth HID device (keyboard, mouse,
joystick)
BT800 module
BT820 USB dongle

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3BLOCK DIAGRAM AND DESCRIPTIONS
Figure 1: BT800 module block diagram
CS8510A10
(Main chip)
The BT800 is based on CSR8510A10 dual mode chip. The chip is a single-chip radio with on-chip
LDO regulators and baseband IC for Bluetooth 2.4 GHz systems including EDR to 3 Mbps.
Dedicated signal and baseband processing is included for full Bluetooth operation. The chip
provides SPI/PCM and USB interfaces. Up to four general purpose I/Os are available for general use
such as Wi-Fi coexistence or general indicators.
Note: The purpose of the SPI interface is to access the module’s inner settings such as selecting
different WLAN CO-EXIST scheme and enabling HID proxy mode. The SPI interface can also
be used to put the module in RF test mode. You cannot use the module over the SPI
interface for normal operation as the main host interface.
Antenna
Options
BT800 The antenna is a ceramic monopole chip antenna.
BT800-ST A trace pin variant of the BT800 for use with an external antenna.
Band Pass
Filter
The band pass filter filters the out-of-band emissions from the transmitter to meet the specific
regulations for type approvals of various countries.
EEPROM
There are 64 k bits EEPROM embedded on the BT800 module which can be used to store
customizable parameters, such as maximum TX power, PCM configuration, USB product ID, USB
vendor ID, and USB product description. With that, the BT800 module can support HID/HCI Proxy
mode.
Crystal
The embedded 26 MHz crystal is used for generating the clock for the entire module.

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4SPECIFICATIONS
Table 1: BT800 specifications
CATEGORIES
FEATURE
IMPLEMENTATION
Wireless Specification
Bluetooth®
V4.0 Dual Mode
Frequency
2.402 - 2.480 GHz
Maximum Transmit
Power
Class 1
+8 dBm from antenna
Receive Sensitivity
-89 dBm
Range
Circa 100 meters
Data Rates
Up to 3 Mbps (over the air)
Host Interface
USB
Full Speed USB 2.0
GPIO
Four configurable lines
(1.8V/3.3V configurable by VDD_PADS)
Operational Modes
HCI
Host Controller Interface over USB
HID Proxy Mode
Human Interface Device
EEPROM
2-wire
64 K bits
Coexistence
802.11 (Wi-Fi)
3 wire CSR schemes supported
(Unity-3;Unity-3e, and Unity+)
Supply Voltage
Supply
5V +/-10%
Note: See Implementation Note for details on different DC
power selections on the BT800.
Power Consumption
Current
Idle Mode ~5 mA
File Transfer ~58 mA
Antenna Option
Internal (BT800)
External (BT800-ST)
Multilayer ceramic antenna with up to 41% efficiency.
A trace pin variant of the BT800 for use with an external antenna.
Physical
Dimensions
8.5 x 13 x 1.75 mm (BT800 ) +/- 1.3mm (L/W)
8.5 x 13 x 1.7 mm (BT800-ST )
16 x 43 x 11 (BT820 –USB Dongle)
Environmental
Operating
-30C to +85C
Storage
-40C to +85C
Miscellaneous
Lead Free
Lead-free and RoHS compliant
Warranty
1 Year
Approvals
Bluetooth®
Controller Subsystem Approved
FCC / IC / CE
All BT800 series (BT800; BT800-ST)

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5PIN DEFINITIONS
Table 2: BT800 pin definitions
#
Pin Name
I/O
Supply
Domain
Description
If
Unused
1
SPI_PCM#_SEL
Input with weak
internal pull-down
VDD_PADS
High switches SPI/PCM lines to
SPI,
Low switches SPI/PCM lines to
PCM/PIO
*See Note 1.
NC
2
VDD_HOST
Power supply
(3.1V-3.6V)
USB system positive supply
N/A
3
GND
GND
-
Ground
GND
4
USB+
Bidirectional
VDD_HOST
USB data plus with selectable
internal 1.5kΩpull-up resistor
NC
5
USB-
Bidirectional
VDD_HOST
NC
6
GND
GND
-
Ground
GND
7
VREG_IN_USB
Power supply
Analogue
regulator
input
Input to USB regulator. Connect
to external USB bus supply
(USB_VBUS)
N/A
8
VREG_EN_RST#
Input with strong
internal pull-down
VDD_PADS
Take high to enable internal
regulators. Also acts as active
low reset. Maximum voltage is
VDD_PADS.
Note: USB regulator is always
enabled and not
controlled by this pin.
NC
9
VREG_IN_HV
Analogue regulator
input / output
3.3V
Input to internal high-voltage
regulator to 1.8V regulator,
3.3V output from USB
regulator.
N/A
10
VREG_OUT_HV
Analogue regulator
input / output
1.8V
Output from internal high-
voltage to 1.8V regulator. Input
to second stage internal
regulators.
N/A
11
GND
GND
-
Ground
GND
12
GND
GND
-
Ground
GND
13
GND
GND
-
Ground
GND
14
GND
GND
-
Ground
GND
15
GND
GND
-
Ground
GND
16
GND
GND
-
Ground
GND
17
RF
-
-
BT800- No connection
BT800-ST –Configured as RF
signal output (50 ohm)
-
18
GND
GND
-
Ground
GND

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#
Pin Name
I/O
Supply
Domain
Description
If
Unused
19
PCM_SYNC/
SPI_CS#/
PIO23
Bidirectional, tri-state,
with weak internal
pull-down
VDD_PADS
PCM synchronous data sync SPI
chip select, active low
Programmable input/output line
*See Note 1.
NC
20
PCM_CLK/
SPI_CLK/
PIO24
Bidirectional, tri-state,
with weak internal
pull-down
VDD_PADS
PCM synchronous data clock
SPI clock
Programmable input/output line
*See Note 1.
NC
21
PCM_IN/
SPI_MOSI/
PIO21
Input, tri-state, with
weak internal pull-
down
VDD_PADS
PCM synchronous data input
SPI data input
Programmable input/output line
*See Note 1.
NC
22
PCM_OUT/
SPI_MISO/
PIO22
Output, tri-state, with
weak internal pull-
down
VDD_PADS
PCM synchronous data output
SPI data output
Programmable input/output line
*See Note 1.
NC
23
PIO0/
WLAN_ACTIVE
Bidirectional, tri-state,
with weak internal
pull- down
VDD_PADS
Programmable input/output line
NC
24
GND
GND
-
Ground
GND
25
PIO1/
BT_PIRORITY
Bidirectional, tri-state,
with weak internal
pull- down
VDD_PADS
Programmable input/output line
NC
26
PIO2/
BT_ACTIVE
Bidirectional, tri-state,
with weak internal
pull- down
VDD_PADS
Programmable input/output line
NC
27
VDD_PADS
Power supply
(1.7V-3.6V)
Positive supply for digital I/O
pads
N/A
28
PIO5
Bidirectional, tri-state,
with weak internal
pull- down
VDD_PADS
Programmable input/output line
NC
Note 1: The purpose of the SPI interface is to access the module’s inner settings such as selecting different WLAN
CO-EXIST scheme and enabling HID proxy mode. The SPI interface can also be used to put the module in
RF test mode. You cannot use the module over the SPI interface for normal operation as the main host
interface.

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6DC ELECTRICAL CHARACTERISTIC
Table 3: Absolute maximum ratings
Rating
Min
Max
Unit
Storage temperature
-40
+85
⁰C
VREG_IN_USB
-0.2
5.75
V
VREG_IN_HV
-0.2
4.9
V
VDD_HOST
-0.2
3.7
V
VDD_PADS
-0.2
3.7
V
Other terminal voltages
VSS - 0.4V
VDD + 0.4 V
V
Table 4: Recommended operating conditions
Rating
Min
Max
Unit
Operating temperature
-30
+85
⁰C
VREG_IN_USB
4.5
5.5
V
VREG_IN_HV
3.1
3.6
V
VDD_HOST
3.1
3.6
V
VDD_PADS
1.7
3.6
V
Table 5: USB Linear Regulator
Rating
Min
Typ
Max
Unit
Input voltage (VREG_IN_USB)
4.5
5.0
5.5
V
Output voltage (VREG_IN_HV)
3.2
3.3
3.4
V
Output current
-
-
150
mA
Table 6: High-voltage Linear Regulator
Normal Operation
Min
Typ
Max
Unit
Input voltage (VREG_IN_HV)
3.1
3.3
3.6
V
Output voltage (VREG_OUT_HV)
1.75
1.85
1.95
V
Temperature coefficient
-200
-
200
ppm/⁰C
Output noise
(frequency range 100Hz to100kHz)
-
-
0.4
mV rms
Settling time (settling time
within 10% of final value)
-
-
5
µs
Output current
-
-
100
mA
Quiescent current
(excluding load, load <1mA)
30
40
60
µA
Low-power Mode
Quiescent current
(excluding load, load <100µA)
14
18
23
µA

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Table 7: Digital I/O Characteristics
Normal Operation
Min
Typ
Max
Unit
Input Voltage
VIL input logic level low
-0.4
-
0.4
V
VIH input logic level high
0.7 x
VDD
-
VDD +
0.4
V
Output Voltage
VOL output logic level low,
IOL = 4.0 mA
-
-
0.4
V
VOH output logic level high,
IOL = 4.0 mA
0.75 x
VDD
-
-
V
Input and Tristate Currents
Strong pull-up
-150
-40
-10
µA
Strong pull-down
10
40
150
µA
Weak pull-up
-5
-1.0
-0.33
µA
Weak pull-down
0.33
1.0
5.0
µA
CI input capacitance
1.0
-
5.0
pF
Table 8: Current Consumption
Normal Operation
Peak (8 dBm)
AVG
Unit
Idle
5
mA
USB Suspend
200
µA
Inquiry
73
51
mA
File Transfer
73
58
mA
LE Connected (Master)
74
mA
LE Scan (Master)
48
mA
7RF CHARACTERISTICS
Table 9: Receiver Characteristics
RF Characteristics, VDD = 3.3V @ room
temperature unless otherwise specified
Min
Typ.
Max
BT. Spec.
Unit
Maximum RF Transmit Power
8
10
20
dBm
RF power variation over temperature range
1.5
-
dB
RF power variation over supply voltage range
0.2
-
dB
RF power variation over BT band
2
-
dB
RF power control range
-21
8
-
dBm
20 dB band width for modulated carrier
1000
kHz
ACP
F = F0 ± 2MHz
-20
F = F0 ± 3MHz
-40

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RF Characteristics, VDD = 3.3V @ room
temperature unless otherwise specified
Min
Typ.
Max
BT. Spec.
Unit
F = F0 > 3MHz
-40
Drift rate
10
+/-25
kHz
ΔF
1avg
165
140<175
kHz
ΔF1
max
168
140<175
kHz
ΔF2avg / ΔF
1avg
0.9
>=0.8
Table 10: BDR and EDR receiver sensitivity
RF Characteristics, VDD = 3.3V @ room temp.
Packet Type
Min
Typ
Max
BT. Spec.
Unit
Sensitivity for 0.1% BER
DH1
-89
-70
dBm
DH3
-89
dBm
DH5
-89
dBm
2-DH5
-92
dBm
3-DH5
-85
dBm
Sensitivity variation over BT band
All
2
dB
Sensitivity variation over temperature range
All
TBD
dB
8INTERFACE
8.1 PIO
See the Device Terminal Functions section for the list of supplies to the PIOs (Programmable I/O ports).
PIO lines are configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines are
configured as inputs with weak pull-downs at reset and have additional individual bus-keeper configuration.
8.2 WLAN Coexistence Interface
Dedicated hardware is provided to implement a variety of WLAN coexistence schemes. There is support for:
Channel skipping AFH
Priority signaling
Channel signaling
Host passing of channel instructions
The BT800 supports the WLAN coexistence schemes:
Unity-3
Unity-3e
Unity+
For more information see BT800 WLAN Coexistence Schemes and LED Indication .

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8.3 USB Interface
BT800 has a full-speed (12 Mbps) USB interface for communicating with other compatible digital devices. The USB
interface on the BT800 acts as a USB peripheral, responding to requests from a master host controller.
BT800 supports the Universal Serial Bus Specification (USB v2.0 Specification) and USB Battery Charging
Specification, available from http://www.usb.org. For more information on how to integrate the USB interface on
BT800, see Figure 19 located in the following section: USB Dongle Design Example Using BT800.
As well as describing USB basics and architecture, the application note describes:
Power distribution for high and low bus-powered configurations
Power distribution for self-powered configuration, which includes USB VBUS monitoring
USB enumeration
Electrical design guidelines for power supply and data lines, as well as PCB tracks and effects of ferrite beads
USB suspend modes and Bluetooth low-power modes
Global suspend
Selective suspend, includes remote wake
Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend
Suspend mode current draw
PIO status in suspend mode
Resume, detach, and wake PIOs
Battery charging from USB: dead battery provision, charge currents, charging in suspend modes and USB
VBUS voltage consideration
USB termination when interface is not in use
Internal modules, certification and non-specification compliant operation
8.4 PCM Interface
The audio PCM interface on the BT800 supports:
Continuous transmission and reception of PCM encoded audio data over Bluetooth.
Processor overhead reduction through hardware support for continual transmission and reception of PCM
data.
A bidirectional digital audio interface that routes directly into the baseband layer of the firmware. It does not
pass through the HCI protocol layer.
Hardware on the BT800 for sending data to and from a SCO connection.
Up to three SCO connections on the PCM interface at any one time.
PCM interface master, generating PCM_SYNC and PCM_CLK.
PCM interface slave, accepting externally generated PCM_SYNC and PCM_CLK.
Various clock formats including:
-Long Frame Sync
-Short Frame Sync
GCI timing environments.
13-bit or 16-bit linear, 8-bit µ-law, or A-law companded sample formats.
Receives and transmits on any selection of three of the first four slots following PCM_SYNC.
The PCM configuration options are enabled by setting PSKEY_PCM_CONFIG32.
8.4.1 PCM Interface Master/Slave
When configured as the master of the PCM interface, the BT800 generates PCM_CLK and PCM_SYNC.

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Figure 2: PCM Interface Master
Figure 3: PCM Interface Slave
8.4.2 L ong Frame Sync
Figure 4: Long Frame Sync (shown with 8-bit Companded Sample)
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In
Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When the BT800 is configured
as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is eight bits long. When the BT800 is
configured as PCM Slave, PCM_SYNC is from one cycle PCM_CLK to half the PCM_SYNC rate.
BT800 samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT is
configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge.
8.4.3 S hort Frame S y nc
In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always one
clock cycle long.

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Figure 5: Short Frame Sync (Shown with 16-bit Sample)
As with Long Frame Sync, BT800 samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the
rising edge. PCM_OUT is configurable as high impedance on the falling edge of PCM_CLK in the LSB position or on
the rising edge.
8.4.4 Multi-Slot Operation
More than 1 SCO connection over the PCM interface is supported using multiple slots. Up to 3 SCO connections are
carried over any of the first 4 slots.
Figure 6: Multi-slot Operation with 2 Slots and 8-bit Companded Samples
8.5 GCI Interface
BT800 is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. The two 64 kbps B channels
are accessed when this mode is configured.
Figure 7: Multi-slot Operation
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8 kHz.

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8.6 Slots and Sample Formats
BT800 receives and transmits on any selection of the first four slots following each sync pulse. Slot durations are
either 8 or 16 clock cycles:
8 clock cycles for 8-bit sample formats.
16 clock cycles for 8-bit, 13-bit, or 16-bit sample formats.
BT800 supports:
13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats
A sample rate of 8 ksps
Little or big endian bit order
For 16-bit slots, the three or eight unused bits in each slot are filled with sign extension, padded with zeros or
a programmable 3-bit audio attenuation compatible with some codecs.
Figure 8: 16-bit Slot Length and Sample Formats

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8.7 PCM Timing Information
Table 11: PCM Timing information
Symbol
Parameter
Min
Typ
Max
Unit
fmclk
PCM_CLK frequency
4MHz DDS generation. Frequency
selection is programmable.
-
128
-
kHz
256
512
48MHz DDS generation.
Frequency selection is
programmable.
2.9
-
-
kHz
-
PCM_SYNC frequency for SCO connection
-
8
-
kHz
tmclkh (a)
PCM_CLK high
4MHz DDS generation
980
-
-
ns
tmclkl a)
PCM_CLK low
4MHz DDS generation
730
-
-
ns
-
PCM_CLK jitter
48MHz DDS generation
-
-
21
ns
pk-pk
tdmclksynch
Delay time from
PCM_CLK high to
PCM_SYNC high
4MHz DDS generation
-
-
20
ns
48MHz DDS generation
-
-
40.83
ns
tdmclkpout
Delay time from PCM_CLK high to valid PCM_OUT
-
-
20
ns
tdmclklsyncl
Delay time from
PCM_CLK low to
PCM_SYNC low (long
frame sync only)
4MHz DDS generation
-
-
20
ns
48MHz DDS generation
-
-
40.83
ns
(a) Assumes normal system clock operation. Figures vary during low-power modes, when system clock speeds are reduced.
Table 12: PCM Master Mode Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
tdmclkhsyncl
Delay time from
PCM_CLK high to
PCM_SYNC low
4MHz DDS generation
-
-
20
ns
48MHz DDS generation
-
-
40.83
ns
tdmclklpoutz
Delay time from PCM_CLK low to PCM_OUT
high impedance
-
-
20
ns
tdmclkhpoutz
Delay time from PCM_CLK high to PCM_OUT
high impedance
-
-
20
ns
tsupinclkl
Set-up time for PCM_IN valid to PCM_CLK low
20
-
-
ns
thpinclkl
Hold time for PCM_CLK low to PCM_IN invalid
0
-
-
ns

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Figure 9: PCM Master Timing Long Frame Sync
Figure 10: PCM Master Timing Short Frame Sync
8.8 PCM Slave Timing
Symbol
Parameter
Min
Typ
Max
Unit
fsclk
PCM clock frequency (Slave mode: input)
64
-
2048
kHz
fsclk
PCM clock frequency (GCI mode)
128
-
4096
kHz

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Symbol
Parameter
Min
Typ
Max
Unit
tsclkl
PCM_CLK low time
200
-
-
ns
tsclkh
PCM_CLK high time
200
-
-
ns
8.9 PCM Slave Mode Timing Parameters
Symbol
Parameter
Min
Typ
Max
Unit
thsclksynch
Hold time from PCM_CLK low to PCM_SYNC high
2
-
-
ns
tsusclksynch
Set-up time for PCM_SYNC high to PCM_CLK low
20
-
-
ns
tdpout
Delay time from PCM_SYNC or PCM_CLK, whichever is
later, to valid PCM_OUT data (long frame sync only)
-
-
15
ns
tdsclkhpout
Delay time from CLK high to PCM_OUT valid data
-
-
15
ns
tdpoutz
Delay time from PCM_SYNC or PCM_CLK low, whichever is
later, to PCM_OUT data line high impedance
-
-
20
ns
tsupinsclkl
Set-up time for PCM_IN valid to CLK low
20
-
-
ns
thpinsclkl
Hold time for PCM_CLK low to PCM_IN invalid
2
-
-
ns
Figure 11: PCM Slave Timing Long Frame Sync

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Figure 12: PCM Slave Timing Short Frame Sync
8.10 PCM_CLK and PCM_SYNC Generation
BT800 has two methods of generating PCM_CLK and PCM_SYNC in master mode:
Generating these signals by DDS from BT800internal 4MHz clock. Using this mode limits PCM_CLK to 128,
256 or 512 kHz and PCM_SYNC to 8 kHz.
Generating these signals by DDS from an internal 48MHz clock, which enables a greater range of frequencies
to be generated with low jitter but consumes more power. To select this second method set bit
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the
length of PCM_SYNC is either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in
PSKEY_PCM_CONFIG32.
Equation 8.1 describes PCM_CLK frequency when generated from the internal 48MHz clock:
Equation 8.1: PCM_CLK Frequency Generated Using the Internal 48MHz Clock
Set the frequency of PCM_SYNC relative to PCM_CLK using Equation 8.2:
Equation 8.2: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to
generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set SKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.

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8.11 PCM Configuration
Configure the PCM by using PSKEY_PCM_CONFIG32 and PSKEY_PCM_LOW_JITTER_CONFIG (See your PSKey file).
The default for PSKEY_PCM_CONFIG32 is 0x00800000 (for example: first slot following sync is active, 13-bit linear
voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no
tri-state of PCM_OUT).
8.12 Digital Audio Interface (I²S)
The digital audio interface supports the industry standard formats for I²S, left-justified or right-justified. The interface
shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table 13
lists these alternative functions. Figure 11 shows the timing diagram.
Table 13: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface.
PCM Interface
I²S Interface
PCM_OUT
SD_OUT
PCM_IN
SD_IN
PCM_SYNC
WS
PCM_CLK
SCK
Configure the digital audio interface using PSKEY_DIGITAL_AUDIO_CONFIG, see BlueCore Audio API Specification
and the PS Key file.
Figure 13: PCM Configuration