Lattice Semiconductor LatticeECP3 Versa User manual

November 2012
Revision: EB49_01.4
LatticeECP3™ Serial Protocol Board – Revision E
User’s Guide

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LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
Introduction
The LatticeECP3 Serial Protocol Board (referred to in this document as “SPB”) allows designers to investigate and
experiment with the features of the LatticeECP3 high-speed SERDES transceivers. The SPB is available for full
and detailed characterization of the high speed I/O channels and includes interfaces for some of the latest protocol
interconnections.
Important: This document (including the schematics in the appendix) describes LatticeECP3 Serial Protocol
Boards marked as Rev E. This marking can be seen on the silkscreen of the printed circuit board, under the Lattice
Semiconductor logo.
The features of the LatticeECP3 Serial Protocol Board can assist engineers with rapid-prototyping and testing their
specific designs. The board is an enhanced form-factor of the PCI Express add-in card specification. It allows for x4
PCI Express interconnection that is available for demonstration purposes with some non-standard form-factor
issues. The board has several debugging and analyzing features for complete evaluation of the LatticeECP3
device. This guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the
LatticeECP3 FPGA.
The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test
and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias.
The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces.
Figure 1. LatticeECP3 Serial Protocol Board - Revision E
Board Features
• PCI Express x4 edge connector interfaces
– Allow demonstration of PCI Express (x4) interfaces

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– x4 is non-compliant but will demonstrate x4 functionality with an open-frame motherboard
• Allow control of SERDES PCS registers using the Serial Client Interface (ORCAstra)
• Serial ATA interfaces for host and target configurations
• RJ45 interface to 10/100/1000 Ethernet
• On-board Boot Flash.
– 64M Serial SPI Flash
– Parallel Flash via MachXO™ Crossover PLD programming bridge
• Switches, LEDs, displays for demo purposes
• 32-Bit DDR memory
• Several debug and analysis connections
• Input connection for lab-power supply
• Power connections and power sources
• ispVM™ programming support
• On-board and external reference clock sources
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board.
Figure 2. Serial Protocol Board Outline Drawing

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LatticeECP3 Device
This board features a LatticeECP3 FPGA with a 1.2V core supply. It can accommodate all pin compatible
LatticeECP3 devices in the 1156-ball fpBGA (1mm pitch) package. A complete description of this device can be
found in the LatticeECP3 Family Data Sheet.
Note: The connections referenced in this document refer to the LFE3-95E-FF1156 device. Available I/Os and asso-
ciated sysIO™ banks may differ for other densities within this device family.
Applying Power to the Board
The LatticeECP3 Serial Protocol Board is ready to power on. The board can be supplied with power from an AC
wall-type transformer power supply shipped with the board. Or, it can be supplied from an benchtop supply via ter-
minal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host
board.
To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord
to J1 and plug wall-transformer into an AC wall outlet.
Power Supplies
(see Appendix A, Figure 20)
The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to
accept a main supply via the TB1 connection. This connection is provided to use with a benchtop supply adjusted
to provide a nominal +12V DC. An indicator (D1) will illuminate when 12V is applied to the board.
All input power sources and on-board power supplies are fused with surface mounted fuses and have green LEDs
to indicate power GOOD status of the intermediate supplies.
Table 1. Board Power Supply Fuses and Indicators LEDs (see Appendix A, Figure 20)
Fuse
Designator Function Power Good LED Designator Function
F1 12V Input Supply Fuse D1 12V Input Good Indicator
F2 1.5V Fuse D6 1.5V Good Indicator
F3 1.2V Core Fuse D3 1.2V Core Good Indicator
F4 3.3V Fuse D4 3.3V Good Indicator
F5 1.8V Fuse D7 1.8V Good Indicator
F6 1.2V Analog Supply D2 1.2V VCCA Good Indicator
F7 2.5V Fuse D5 2.5V Good Indicator
Power can be supplied with either a wall transformer pack, or another external source.
Table 2. External Board Supply Input Terminal (see Appendix A, Figure 20)
TB1 Screw terminal for 12V DC
Pin 1(square PCB pad) -> +12V DC
Pin 2 -> Ground
The above-mentioned supplies can be isolated from the on-board regulators by removal of the associated fuse.
Surface-mounted test loops are provided to apply alternative power sources to these supplies as required for test-
ing purposes.

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Table 3. Power Supply Test Connections
Test Point Designator Supply
LP1 2.5V
LP2 1.5V
LP3 3.3V
LP4 1.8V
LP5 1.2V VCCA
LP6 1.2V VCC Core
PCI Express Power Interface
Power can be sourced to the board via the PCB edge fingers (CN1). This interface allows the user to provide power
from a PCI Express host board.
Power Management
The evaluation board includes a Lattice ispPAC®-POWR1220AT8 programmable power management IC (U10).
This device controls the power sequence and monitors designated board supplies. The POWER GOOD indication
LEDS are controlled via this device.
The power management device is factory programmed to control the power supplies. A block diagram of the power
management is shown in Figure 3.
Figure 3. Power Management Block Diagram
VCC Core, +1.2v , 10A
3_3V, +3.3V, 2A
3.3VIN, +2.5V, 6A
1_5V, +1.5V, 2A
ispPAC
12V INPUT
PCIe Edge
12V Wall Adapter
12V Input Terminal
MOSFET
1_8V, +1.8V, 2A
1_2VA, +1.2V, 1.5A
2_5V, +2.5V, 1.5A
LDO
LDO
LDO
LDO
POL
POL
LDO
ETH_1_2V, +1.2V, 0.5A
Programming/FPGA Configuration
(see Appendix A, Figure 23)
A programming header is provided on the evaluation board, providing access to the LatticeECP3 JTAG port.
Note: An ispDOWNLOAD™ Cable is included with each ispLEVER®-Base or ispLEVER-Advanced design tool
shipment. Cables may also be purchased separately from Lattice.
ispVM Download Interface
J12 is an 10-pin JTAG connector used in conjunction with the ispVM USB download cable to program and control
the device.

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Table 4. Standard ispVM Programming Cable Configuration
Pin Description
Pin 1 VCC
Pin 2 TDO
Pin 3 TDI
Pin 4 PROGRAMN1
Pin 5 Enable used for alternate programming of the ispPAC-POWR1220AT8 device
Pin 6 TMS
Pin 7 GND
Pin 8 TCK
Pin 9 DONE1
Pin 10 INITN1
1. Denotes optional connection to programming cable.
After initial board setup, use the following procedure to program the evaluation board.
Instructions assume ispVM software has been installed on a local PC.
Connect the ispDOWNLOAD cable rainbow-colored flywires to the connector J12.
Pin 1 = red, 2 = brown, 3 = orange, 4 = open, 5 = open, 6 = purple, 7 = black, 8 = white, 9 = open, 10 = open.
Table 5. ispVM JTAG Connector (see Appendix A, Figure 23)
Pin Function Color
1PWR Red
2TDO Brown
3TDI Orange
5ISPEN Ye l l o w 1
6TMS Purple
7GND Black
8TCK White
1. Only connected for programming the ispPAC-POWR1220AT8 device.
NC NC NC
8910 76 32154
Programming the Daisy Chain
(see Appendix A, Figure 23)
This board includes three Lattice programmable (U1=LFE395, U17= LCMXO1200C, and U13 = POWR1220AT8)
devices that can be programmed in a daisy chain. The board also includes a mechanism to daisy chain other Lat-
tice evaluation boards that use the same connector standard.

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Figure 4. JTAG Chain
Buffer
LatticeECP3
TDI
TCK
TMS
TCK
ATDI
TMS
TDI
J12
ispEN
TDO TDI TDO TDI TDO
MachXO
Power
Manager II
ispVM
Cable
Daisy Chain
Off-Board
Board
Jumpers
TDI
J9
An alternative chain can be used when it is desired to only communicate with the ispPAC-POWR1220AT8 device.
This alternative method utilizes the ispEN pin to drive the TDISEL input. A logic “1 “driven on the TDISEL of the isp-
PAC-POWR1220AT8 will enable the ATDI input ignoring the TDI data of the board JTAG chain and receiving TDI
data directly from the ispVM input.
A 2x3 header(J41) completes the on-board JTAG chain between the LatticeECP3 FPGA, the MachXO1200 CPLD
and the ispPAC-POWR1220 devices. These jumpers must be in place for proper operation with ispVM.
Figure 5. ALL Devices in Chain Selection (J41)
JTAG daisy-chaining across multiple boards is provisioned on board by jumpers. Header J8 controls the data path
to and from the evaluation board TDO. The board is factory programmed with a jumper across pins 1 and 2 of J8. If
the user needs to build a JTAG daisy-chain to another Lattice evaluation board the user needs to place jumpers
between pins 1 and 3 and 2 and 4 respectively. This will alter the data path off-board via J9, which typically can be
connected to another ispVM connector of a Lattice Semiconductor evaluation board. J10 and J11 can also be used
for off-board daisy-chaining to wire AND the PROGRAMN and INITN pin respectively between the boards.
Download Procedure
Requirements:
• PC with ispVM System v.17.4 (or later) programming management software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option
to install these drivers is included as part of the ispVM System setup.
• ispDOWNLOAD Cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.)
JTAG Download
The LatticeECP3 device can be configured easily via its JTAG port. The device is SRAM-based; it must remain
powered on to retain its configuration when programmed in this fashion.
1. Connect the LatticeECP3 Serial Protocol Board to the appropriate power sources and power up board.
2. Connect the ispDOWNLOAD cable to the appropriate header. J12 is used for the 1x10 cable.
3. Start the ispVM System software.
4. Press the SCAN button located in the toolbar. The LatticeECP3 and the MachXO1200 devices will be automat-
ically detected.

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Figure 6. Main Downloading Window
5. Double-click the device to open the device information dialog. In the device information dialog, click the
Browse button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes.
6. Add the data file from the Browse dialog and select OK when complete.
7. To program only the LatticeECP3-95, place the LCMXO1200C and the ispPAC-POWR1220AT8 devices into
BYP
ASS and the LFE3-95 into Erase, Program, Verify mode, as shown below.
Figure 7.
Device Information Window

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Figure 8. Successful Programming Session
8. Click the green GO button. This will begin the download process into the device. Upon successful download,
the device will be operational.
Programming the Power Manager Device
The J12 header can be used to isolate and program the ispPAC-POWR1220AT8 Power Manager device. This
device can be isolated from the others on the chain using the optional ispEN connection from the ispVM program-
ming cable. Connecting ispEN to pin 5 on J12 and selecting the optional control in ispVM will isolate the Power
Manager. The connection is activated from the Options pull-down menu of the ispVM toolbar. The Cable and I/O
Port Setup dialog box is used to select the polarity of this connection to SET LOW.

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Figure 9. Setup for ISPEN Usage
Figure 10. Programming of ispPAC-POWR1220AT8 Power Manager Device
Note: The ispEN connection must be disconnected for complete programming of the other devices on the SPB.
Configuration Status Indicators
(see Appendix A, Figure 23)
These LEDs indicate the status of configuration to the FPGA.
• D8 (red) illuminated, this indicates that the programming was aborted or reinitialized driving the INITN output low.
• D11 (green) illuminated, this indicates the successful completion of configuration by releasing the open collector
DONE output pin.
• D12 (green) will flash indicating TDI activity.

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• D10 (red) illuminated, this indicates that PROGRAMN is low.
• D9 (red) illuminated, this indicates that GSRN is low.
PROGRAMN and GSRN
(see Appendix A, Figure 23)
• These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3) and GSRN (SW1).
Depressing the button drives a logic level “0” to the device.
CFG [2:0]
(see Appendix A, Figure 23)
• The FPGA CFG pins are set on the board for a particular programming mode via the SW2 DIP switch.
•JTAG programming is independent of the MODE pins and is always available to the user.
• Pushing in (depressing) the switch is ON and sets the value to 0.
Table 6. CFG Mode Selections
CFG2 CFG1 CFG0 Configuration Mode
0(ON) 0(ON) 0(ON) SPI Flash
0(ON) 1(OFF) 0(ON) SPIm
1(OFF) 0(ON) 1(OFF) Slave Serial
1(OFF) 1(OFF) 1(OFF) Slave Parallel
X
(don’t care)
X
(don’t care)
X
(don’t care) ispJTAG
On-Board Serial SPI Flash Memory
(see Appendix A, Figure 23)
• One Serial SPI (16-pin TSSOP 64M) Flash memory devices (U11) is on-board for non-volatile configuration
memory storage. Either a STMicro M25P64VMF16 or Macronix MX25L6405 device is populated on-board.
• The CFG [2:0] need to be [000] all depressed to read the Flash memory at power-up or after toggling the PRO-
GRAMN pin.
• J11 must have a jumper between pins 1 and 2.
Programming Serial SPI Flash Memory
The Serial SPI Flash memory device can be configured easily via its JTAG port. This mode enables the FPGA to
be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
1. Connect the evaluation board to the appropriate power sources and power up board.
2. Connect the ispDOWNLOAD cable to the appropriate header. J9 is used for the 1x10 cable.
3. Start the ispVM System software.
4. Press the Scan button located in the toolbar. The LFE3-9, LCMXO1200C and ispPOWR1220AT8 devices will
be automatically detected.
5. Double-click the Operation column for the LFE3-95 and the Device Dialog box shown below will open.
6. In the dialog box select the SPI Flash Programming Mode in the Device Access Option pull-down menu. This
will open the SPI Serial Flash Dialog box.

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Figure 11. Device Information Dialog Screen
7. The SPI Serial Flash Device dialog box will open. In this box select SPI Flash Erase, Program, Verify in the
Operation pull-down menu.
8. Select SPI Serial Flash in the Device Family pull-down menu, STMicro under the Vendor pull-down menu,
SPI-M2564 under the Device pull-down menu, and 16-lead SOIC under the Package submenu.
Figure 12. Select Device Dialog Box

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Figure 13. Sample SPI Serial Flash Device Dialog Box
9. Click OK in the SPI Flash Device Dialog box. Then click OK in Select Device dialog box. You will then return to
the main configuration screen. If you do not desire to load the LCMXO1200C and the ispPOWR1220 device,
these devices should be placed in Flash Bypass mode by double-clicking the Operation column and selecting
the Bypass operation shown below.
Figure 14. Flash Bypass for LCMXO1200C Device
10. From the main programming window, Select Go for the top toolbar. This will begin the SPI Serial Flash pro-
gramming.

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Figure 15. Programming Main Window
Figure 16. SPI Serial Flash Programming Status Window
Figure 17. Successful SPI Serial Flash Programming Session
On-Board Parallel SPI Flash Memory
(see Appendix A, Figure 25)
• A 16-bit parallel Flash device is also available. This board uses a Lattice MachXO Crossover PLD to act as a pro-
gramming bridge from the Flash device.
• The CFG [2:0] needs to be [111] all up.
• The ispVM System programming software can be used directly to program either the serial SPI Flash or the par-

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allel Flash devices. Application note AN8077, Parallel Flash Programming and FPGA Configuration,addresses
the use of the parallel Flash implementation.
On-Board Clock Capabilities
Dedicated SERDES Reference Clock Inputs
(see Appendix A, Figure 26)
• A 156.25 MHz, low-jitter (5x7.5mm surface mount) oscillator is included on-board.
– Connected via clock mux to PCSB_REFCLK
– Clock control CLOCK_CTRL_SEL0 is connected to both the FPGA (ball #A25) or the Crossover PLD (ball
#N6). Either of these sources selects the clock source of Y1 oscillator or J29 and J33 SMA inputs.
• A 125.00 MHz, low-jitter (5x7.5mm surface mount) oscillator is included on-board.
– Connected via clock mux to PCSC_REFCLK
– Clock control CLOCK_CTRL_SEL1 is connected to both the FPGA (ball #B25) or the Crossover PLD (ball
#M14). Either of these sources selects the clock source of Y2 oscillator or J30 and J34 SMA inputs.
***SMA connections J29 and J33 can provide an external clock source to PCSB. J29 is the true and J33 is the
compliment of the differential pair. The description markings on the evaluation board are incorrect.
***SMA connections J30 and J34 can provide an external clock source to PCSC. J30 is the true and J34 is the
compliment of the differential pair. The description markings on the evaluation board are incorrect.
User Defined General Purpose Clock Oscillator
(see Appendix A, Figure 31)
A 100 MHz oscillator is included on the board. It is fanned-out to several destinations on the board. They include
the following. This oscillator is used for general clocking and should be avoided for jitter sensitive applications.
Table 7. 100 MHz Clock Destinations
Clock Destination Evaluation Board Designation Destination Pin
Crossover PLD U17 A8
FPGA U1 B6
FPGA U1 H17-PCLKT0
FPGA U1 P30-RUM2_GPLLT_IN_A
(see Appendix A, Figure 33)
An auxiliary SMT oscillator area is included on the board. It includes a 5x7.5mm surface-mount pad for the addition
of any user-defined oscillator. This oscillator interconnects to FPGA ball numbers AB28 and AB29 that are specifi-
cally general purpose PLL inputs to the FPGA fabric.
(see Appendix A, Figure 33)
SMA inputs J38 and J39 are provided to drive any externally generated differential clock onto the board. These 50-
ohm terminated SMAs interconnect to FPGA ball numbers U28 and V28 that are specifically PCLKT3_0 and
PCLKC3_0 inputs to the FPGA fabric.
SERDES
Surface Mounted SMA Connections
(see Appendix A, Figure 26)

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DC coupled top-mounted SMA connectors connect to the one quad or four SERDES Tx and Rx channels. These
pins are directly coupled to the designated SMA connector creating a path for both input and output differential
data.
Table 8. SERDES SMA Test Connectors
Connector SERDES Signal FPGA Pin Connector SERDES Signal FPGA Pin
J13 PCSB_HDINP0 AL17 J21 PCSB_HDINP2 AL15
J14 PCSB_HDINN0 AK17 J22 PCSB_HDINN2 AK15
J15 PCSB_HDINP1 AL16 J23 PCSB_HDINP3 AL14
J16 PCSB_HDINN1 AK16 J24 PCSB_HDINN3 AK14
J17 PCSB_HDOUTP0 AP17 J25 PCSB_HDOUTP2 AP15
J18 PCSB_HDOUTN0 AN17 J26 PCSB_HDOUTN2 AN15
J19 PCSB_HDOUTP1 AP16 J27 PCSB_HDOUTP3 AP14
J20 PCSB_HDOUTN1 AN16 J28 PCSB_HDOUTN3 AN14
Serial ATA Channels
(see Appendix A, Figure 26)
High-speed connections are included to attach SATA-type cables to SERDES channels for board-to-board or loop-
back purposes. The connectors are configured using the 7-pin SATA specifications.
Figure 18. SATA Connector, Molex Part Number 67800-5050
Table 9. SERDES to SATA Connections
Host Target
CN1 Pin SERDES Pin FPGA Ball # CN2 Pin SERDES Pin FPGA Ball #
1 — GND 1 — GND
2PCSC_HDOUTP1 AP24 2PCSC_HDINP0 AL25
3PCSC_HDOUTN1 AN24 3PCSC_HDINN0 AK25
4 — GND 4 — GND
5PCSC_HDINP1 AL24 5PCSC_HDOUTP0 AP25
6PCSC_HDINN1 AK24 6PCSC_HDOUTN0 AN25
7 — GND 7 — GND
SERDES PCI Express Channels
(see Appendix A, Figure 26)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge
fingers (CN3) to fit directly into a PCI Express host receptacle. Power can be supplied directly from the PCI
Express host via the edge-finger connections.

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Table 10. x4 PCI Express Connections
CML Pin Name FPGA Pin PCI Express PCI Express
Edge Description
PCSA_HDOUTP_3 AP18 PERp0 A16 Integrated end point block transmit pair
PCSA_HDOUTN_3 AN18 PERn0 A17
PCSA_HDINP_3 AL18 PETp0 B14 Integrated end point block receive pair
PCSA_HDINN_3 AK18 PETn0 B15
PCSA_HDOUTP_2 AP19 PERp1 A21 Integrated end point block transmit pair
PCSA_HDOUTN_2 AN19 PERn1 A22
PCSA_HDINP_2 AL19 PETp1 B19 Integrated end point block receive pair
PCSA_HDINN_2 AK19 PETn1 B20
PCSA_HDOUTP_1 AP20 PERp2 A25 Integrated end point block transmit pair
PCSA_HDOUTN_1 AN20 PERn2 A26
PCSA_HDINP_1 AL20 PETp2 B23 Integrated end point block receive pair
PCSA_HDINN_1 AK20 PETn2 B24
PCSA_HDOUTP_0 AP21 PERp3 A29 Integrated End point block transmit pair
PCSA_HDOUTN_0 AN21 PERn3 A30
PCSA_HDINP_0 AL21 PETp3 B27 Integrated End point block receive pair
PCSA_HDINN_0 AK21 PETn3 B28
PCSA_REFCLKP AH19 PCIe_CLKp A13 Integrated End point block differential clock pair
PCSA_REFCLKN AH20 PCIe_CLKn A14
PCIE_PERSETN D23 PERSTN A11 Fundamental PCI Express reset
External SERDES Reference Clock Cleaner
(see Appendix A, Figure 27)
The Texas Instruments CDC7005 is a high-performance, low-phase noise, and low-skew clock synthesizer and jit-
ter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. It is
included on the evaluation board to demonstrate the use of an external clock cleaner as a means to reuse the
SERDES recovered clock for retransmitting. The interconnection from the FPGA brings a single-ended LVCMOS
clock from the SERDES to the CDC7005 input. The CDC7005 has an internal prescaler, phase frequency detector,
charge pump, operational amplifier, and a LVPECL clock buffer. Along with an external VCXO and loop filter, the
device completes a phase locked loop (PLL). Through the PLL operation, the VCXO input clock synchronizes with
the reference clock input and ultimately with all clock outputs. All LVPECL clock outputs are completely synchro-
nized in terms of phase and frequency with the reference clock input.
Table 11. Reference Clock Interconnections
CDC7005 Outputs 1156 fpBGA Inputs Notes
Y0/Y0b P46/P47 PCSB_REFCLKP/N AH15/AH16
Stuffing option R126/R127 must be fitted
with 0-ohm resistors for connection to the
FPGA reference clock input.
Y1/Y1b P3/P4 RLM1_GPLLT_INA/B Y28/Y27
Y2/Y2b P7/P8 RUM0_GDLLT_INA/B AJ34/AK34
CDC7005 Input 1156 fpBGA Output
REFIN P37 D22 LVC M OS
The jitter cleaning action depends on the PLL loop bandwidth. Up to the loop bandwidth, all noise (jitter) passes
through and above the loop bandwidth, all signal noise is cleaned. The ideal loop bandwidth is chosen such that
the reference clock source starts exceeding the VCXO noise floor. If the input has lot of jitter, then selecting a low

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loop bandwidth, jitter can be cleaned. For the CDC7005, a low loop (sub 10 Hz) bandwidth can be selected easily.
The CDC7005 itself adds a low noise to its outputs. For jitter cleaning operation, the noise performance of VCXO is
critical. So, with a proper loop bandwidth and applicable VCXO, the CDC7005 acts as a jitter cleaner. The evalua-
tion board is equipped with an Epson-Toyocom TCO2111-245.76MHZ VCXO that is packaged in a 13.9x9.8mm
SMT form-factor.
Table 12. CDC7005 Control and Status Signals
CDC7005 Pin Board Feature Description
1NPD SW5 Push-button that asserts LOW when depressed to power-down
CDC7005.
14 NRESET SW6 Push-button that asserts LOW when depressed to RESET CDC7005.
22 STATUS_VCXO D13 Amber LED - CDC7005 PLL locked when lit.
23 STATUS REF D14 Amber LED - CDC7005 valid clock on REF_IN when lit. > 3.5 MHz.
25 STATUS LOCK D15 Amber LED - CDC7005 valid VCXO clock on VCXO_IN when lit.
> 10 MHz
The serial interface of the CDC7005 is a simple SPI-compatible interface for writing to the registers of the device. It
consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. These pins from the CDC7005 are inter-
connected to the FPGA to allow for a controller to be built inside the FPGA.
Table 13. CDC7005 Serial Interconnections
CDC7005 1156 fpBGA Ball Number
CTRL_CLK 35 E23
CTRL_DATA 33 C23
CTRL_LE 36 E22
The TI CDC7005 can also be controlled via an interface to header J47. This header can be used in conjunction
with the TI programming software required for programming the internal control register of the CDC7005. TI. The
software package provides real-time GUI control to the device. The software runs under Windows98, NT, and 2000.
Info can be found at www.ti.com/lit/zip/scac037.
Table 14. External Programming Interface for TI CDC7005 Clock Cleaner (See Appendix A, Figure 27)
J47 Pin DB-25 Parallel Cable Description
1 2 Data
2 3 CLK
3 4 LE
418 Enable
519 GND
FPGA Test Pins
(see Appendix A, Figure 31)
General Purpose DIP Switch
(see Appendix A, Figure 31, SW14)
General-purpose FPGA pins are available for user applications. FPGA pins are connected to a switch (SW15) that
is a SPST-side actuated DIP switch. The switch is physically located on the secondary side of the board along the
back-panel edge. The switches are connected to logic level 0 when depressed toward the board and a 1 when
away from the board. The designated pins are connected according to the following table.

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Table 15. FPGA Test Pins (See Appendix A, Figure 33)
1156 fpBGA
Ball Number SW14 Switch Position
Y34 1
Y33 2
Y30 3
AA29 4
Y32 5
Y31 6
Y26 7
Y25 8
General-Purpose LEDs
(see Appendix A, Figure 31)
The LEDs on the evaluation board are connected to general-purpose FPGA I/O. The purpose of these LEDs is to
provide status for user designs. The LEDs must be included in the FPGA design.
Table 16. LED Definitions (See Appendix A, Figure 33)
Name 1156 fpBGA Ball Number PCB Designator LED Color
LED1 W32 D21 Red
LED2 W31 D24 Ye l l o w
LED3 V29 D25 Green
LED4 W28 D27 Blue
LED5 W30 D28 Blue
LED6 W29 D26 Green
LED7 W27 D23 Ye l l o w
LED8 W26 D22 Red
General-Purpose Header
(see Appendix A, Figure 31, J40)
A 2x9 header (J10) provides a general-purpose connection to communicate with general purpose FPGA I/Os.
Table 17. General Purpose Header Connections (See Appendix A, Figure 33)
Header Pin 1156 fpBGA Ball Number Header Pin 1156 fpBGA Ball Number
1GND 2GND
3A6 4E11
5A8 6J13
7A9 8K13
9A10 10 B11
11 B10 12 A11
13 J12 14 G12
15 K12 16 G11
17 C11 18 D11

20
LatticeECP3 Serial Protocol Board – Revision E
User’s Guide
17-Segment LED Display
(see Appendix A, Figure 33, D20)
General-purpose FPGA pins are connected to a 17-segment display according to Ta bl e 18. These pins can be
driven low to illuminate the display segments.
Table 18. 17-Segment LED Display
Segment 1156 fpBGA Ball Number
AB
C
D
G
FE DP
H
TSR
KMN
UP
AC30
BC29
CB31
DA31
EH25
FH26
GA30
HA29
KA27
MA26
NA28
PB28
RG25
SG26
TD25
UC25
DP D28
Logic Analyzer Probe
(see Appendix A, Figure 31, LA1)
An AMP/TYCO 767004 38-position .025 VERT SMD logic analyzer probe connection is provided for the user to uti-
lize for test points. This connection provides 34 general I/O signals to be observed on Logic Analyzer probes using
Mictor connections such as the Agilent 5346A.