Lattice Semiconductor LCMXO256C-S-EV User manual

April 2007
Revision: ebug14_01.4
MachXO™ Starter Evaluation Board
User’s Guide

2
MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
Introduction
The Lattice MachXO Starter Evaluation Board provides a convenient platform to evaluate, test and debug user
designs. The board features a Lattice MachXO256 cross-over programmable logic device in a 100-pin TQFP pack-
age, power input jacks, a 33MHz clock oscillator and I/O connections. The Lattice MachXO I/Os are connected to a
rich variety of interfaces, including switches (momentary and ON/OFF), LEDs, 0.10” headers and PCB test points.
Features
• Lattice MachXO device
• Prototyping area
• Access to 81 user I/Os
• Independent voltage control for core and I/O
• 33MHz on-board oscillator
• Status LEDs
• Input switches
• Pads for optional board expansion.
• AC adapter
• Lattice ispDOWNLOAD
®
cable, to download programming files to the MachXO device.
Software Support
• Lattice ispLEVER
®
design tools (release 5.0 SP1 or later) for HDL design targeting the MachXO device. The
MachXO device is supported in the ispLEVER-Starter software, available from www.latticesemi.com/starter.
• ispVM
®
System, for device programming. Available for download from www.latticesemi.com/software.
Electrical, Mechanical and Environmental Specifications
The nominal board dimensions are 2.875 inches by 3.375 inches. The environmental specifications are as follows:
• Operating temperature: 0ºC to 55ºC
• Storage temperature: -40ºC to 75ºC
• Humidity: < 95% without condensation
• VDC input (+/- 10%) up to 4A
Figure 1 shows the board outline.

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MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
Figure 1. MachXO Starter Outline
Resources relating to the Lattice MachXO Starter Evaluation Board, including user documentation updates and
sample programs, can be found at www.latticesemi.com/boards. Click on the appropriate link for the Lattice
MachXO Starter Evaluation Board.
Lattice MachXO Device
The MachXO Starter Evaluation Board features a Lattice MachXO device with a 3.3V DC core. The board is popu-
lated with a MachXO256 device in a plastic 100-pin TQFP package. The MachXO Starter Evaluation Board allows
for density migration to other Lattice MachXO densities in the 100 TQFP package, with either 3.3V or 1.2V cores. A
complete description of this device can be found in the Lattice MachXO Family Data Sheet on the Lattice web site
at www.latticesemi.com.
Device Core and I/O Voltage
Core Voltage
The MachXO is available with either 3.3V or 1.2V core voltage devices. Boards populated with a 3.3V DC core
device will allow operation of the core between 1.8V and 3.3V DC. The core voltage is fixed at 3.3V during manu-
facturing. The core voltage may be changed from the fixed 3.3V rail to the adjustable voltage rail by changing the 0
ohm resistor at R157 to R158.
Boards populated with a 1.2V core device operate at 1.2V only, with the core voltage supply fixed at 1.2V during
manufacturing. Refer to the board silkscreen outline in the appendix for component location.
Prototype
Area
MachXO I/O Access
MachXO I/O
Access
MachXO I/O
Access
Expansion
Header
Expansion
Header
3.3V LDO
1.2V LDO Adjustable
LDO
33MHz
Oscillator
Switches JTAG
Interface
DC Input
LED Bank
DIP
Switch

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MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
I/O Voltage
The Lattice MachXO device has two sysIO™ banks; each is capable of supporting multiple I/O standards. Each
sysIO bank has its own I/O supply voltage (V
CCIO
), which allows each I/O bank to be completely independent.
Refer to the Lattice MachXO Family Data Sheet for additional information about supported I/O standards. This data
sheet can be downloaded from www.latticesemi.com.
The MachXO Starter Evaluation Board allows individual control of each I/O bank capable of supporting V
CCIO
between 1.2V and 3.3V. The board includes 0 ohm resistors which allow the user to select 3.3V or an adjustable
voltage between 1.25V and 3.3V. During manufacturing, the V
CCIO
banks are set to 3.3V. The adjustable voltage
rail (ADJ) is fixed at 2.5V during manufacturing. Table 1 shows the required resistor population to set the appropri-
ate core and I/O voltages.
Table 1. Voltage Jumpers/Settings for V
CCIO
and VCC_CORE
Device Clocks
The MachXO Starter Evaluation Board provides a variety of ways to supply clock signals to the MachXO device.
These include a 33MHz on-board crystal oscillator, expansion connectors and 0.1” header pins. The on-board
oscillator is connected to MachXO pin 36, which is a dedicated clock input. The oscillator can be enabled/disabled
via pull up (R144) /down (R145), or through pin 44 of the MachXO. Dedicated clock inputs are also available on the
following pins: 38, 85 and 86. These pins are brought out to test points on the PCB, and to the expansion headers.
Device I/O Banks
MachXO I/O banks 0 and 1 are general purpose I/O banks connected to a combination of test pads, switches,
LEDs and two board expansion headers. The switches consist of two user defined push-button switches and an 8-
position DIP switch. Both types of switches are pulled up to the associated V
CCIO
voltage with 10K Ω resistors
(when in the up position) and connected to GND when activated (in the down position). LEDs are active (lit) when
the device I/O is low. Table 2 details the I/O banks 0 and 1 connections.
I/Os listed as GPIO (General Purpose I/O) are connected to 0.1” centered plated through hole, with an associated
GND hole and pads for a pull-up or pull-down resistor. The pull-up pads are located on the component side of the
PCB, and the pull-down pads on the solder side. These pads are sized for 0805 components. Each device I/O is
connected to a test point on the PCB. The PCB silkscreen is marked with the corresponding MachXO 100-TQFP
I/O pin.
3.3V ADJ 1.2V
VCC_CORE R157 (default
1
)R158 R156(default*)
V
CCIO0
R148 (default) R150 N/A
V
CCIO1
R151 (default) R152 N/A
1. Default resistor is based on device core I/O voltage, 3.3V for “C” devices, and
1.2V for “E” devices.
Table 2. Device I/O Connections
Pin # Pin Name Expansion Connect Function/PCB Connect
1PL2A J1-5 GPIO
2 PL2B J1-6 GPIO
3 PL3A J1-7 GPIO
4 PL3B J1-8 GPIO
5 PL3C J1-9 GPIO
6 PL3D J1-10 GPIO
7 PL4A J1-11 GPIO
8 PL4B J1-12 GPIO
9 PL5A J1-13 GPIO

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MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
11 PL5B J1-14 GPIO
13 PL5C J1-15 GPIO
14 PL5D/GSR_N J1-16 GPIO
15 PL6A J1-17 GPIO
16 PL6B/TSALL J1-18 GPIO
17 PL7A J1-19 GPIO
18 PL7B J1-20 GPIO
19 PL7C J1-21 GPIO
20 PL7D J1-22 GPIO
21 PL8A J1-23 GPIO
22 PL8B J1-24 GPIO
23 PL9A J1-25 GPIO
27 PL9B J1-36 GPIO
29 PB2A J1-37 GPIO
30 PB2B J1-38 GPIO
32 PB2C J1-39 GPIO
34 PB2D J1-40 GPIO
36 PCLKT1_1/PB3A J1-41 Y1
37 PB3B J1-42 GPIO
38 PCLKT1_0/PB3C J1-43 GPIO
39 PB3D J1-44 GPIO
43 PB5A J2-21 GPIO
44 PB4B J2-22 OSC_EN
45 PB4C J2-37 SW2
46 PB4D J2-23 SW3
47 PB5A J2-24 GPIO
48 SLEEPN J2-25 GPIO/SW
1
49 PB5C J2-26 GPIO
50 PB5D J2-20 GPIO
51 PR9B J2-19 GPIO
52 PR9A J2-18 GPIO
53 PR8B J2-17 GPIO
54 PR8A J2-16 GPIO
55 PR7D J2-38 SW1-8
56 PR7C J2-39 SW1-7
57 PR7B J2-40 SW1-6
58 PR7A J2-41 SW1-5
59 PR6B J2-42 SW1-4
61 PR6A J2-43 SW1-3
63 PR5D J2-44 SW1-2
64 PR5C J2-45 SW1-1
65 PR5B J2-46 LED D9
66 PR5A J2-47 LED D8
67 PR4B J2-48 LED D7
Table 2. Device I/O Connections (Continued)
Pin # Pin Name Expansion Connect Function/PCB Connect

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MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
Expansion Header
The MachXO Starter board includes two Samtec board-to-board connector footprints (connectors not included) for
expansion purposes. All MachXO I/O pins, JTAG signals and board voltages are connected to these pads. Refer to
Table 3 for MachXO connections to the expansion headers. Programming pins can be referenced in the Program-
ming Headers sections of this guide. Power connections are listed in Table 3.
Table 3. Expansion Connector Power Connections
The connectors are Samtec part number QTH-030-01-F-D-A. Mating connectors are Samtec part number QSH-
030-01. A mechanical drawing with placement dimensions is available from Lattice.
68 PR4A J2-49 LED D6
69 PR3D J2-50 LED D5
70 PR3C J2-51 LED D4
71 PR3B J2-52 LED D3
72 PR3A J2-53 LED D2
73 PR2B J2-54 LED D1
76 PR2A J2-15 GPIO
77 PT5C J2-14 GPIO
78 PT5B J2-13 GPIO
79 PT5A J2-12 GPIO
80 PT4F J2-11 GPIO
81 PT4E J2-10 GPIO
82 PT4D J2-9 GPIO
83 PT4C J2-8 GPIO
85 PCLKT0_1/PT4B J2-7 GPIO
86 PCLKT0_0/PT4A J2-6 GPIO
87 PT3D J2-5 GPIO
89 PT3C J1-45 GPIO
91 PT3B J1-46 GPIO
94 PT3A J1-47 GPIO
95 PT2F J1-48 GPIO
96 PT2E J1-49 GPIO
97 PT2D J1-50 GPIO
98 PT2C J1-51 GPIO
99 PT2B J1-52 GPIO
100 PT2A J1-53 GPIO
1. By shorting R201 with a 0 ohm resistor.
Power
Supply Expansion Connector Pin
3.3V J2-1,J2-2,J2-3,J2-4, J2-55,J2-56,J2-57, J2-58,J2-59,J2-60
ADJ J1-1,J1-2,J1-3,J1-4
1.2V J1-26,J1-27,J1-28, J1-29,J1-30
GND
J1-31,J1-54,J1-55, J1-56,J1-57,J1-58, J1-59,J1-60, J2-27,
J2-28,J2-29,J2-30, J2-31,J2-32,J2-33, J2-34,J2-35,J2-36,
J1 and J2 Center
Table 2. Device I/O Connections (Continued)
Pin # Pin Name Expansion Connect Function/PCB Connect

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MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
Prototype Area
The MachXO Starter Evaluation Board contains a 0.8” x 1.0” plated through hole prototype area. The holes are
spaced on 0.1” centers and are not connected to any MachXO device pins.
Programming Headers
A 1x10 programming header is provided on the MachXO Starter Evaluation Board, providing access to the
MachXO JTAG port. The header is compatible with all Lattice ispDOWNLOAD cables. The pinout for the header is
provided in Table 4.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the MachXO device and render the board inop-
erable.
An ispDOWNLOAD cable is included with purchase of the ispLEVER design tools. Cables may also be purchased
separately from Lattice. Visit the Lattice web store to learn more at: www.latticesemi.com/store.
Table 4. JTAG Programming Header Connections
Power Setup
Power is supplied to the PCB via the supplied 5V AC/DC transformer. The DC input jack is a 2.5mm, positive tip
size connector. Input voltage should not exceed 9V DC. 800mA low dropout regulators provide V
CC
core and V
CCIO
voltages. The adjustable voltage regulator output can be modified by changing the value of resistor R153. The
equation for calculating V
ADJ
is as follows:
V
ADJ
= 1.25 * (1 + R2/120)
Table 5 shows some common voltages, and the appropriate resistor value for setting each voltage. Resistance
given is for the closest standard value. Resistor pads are 0805 component size.
JTAG Programming
Function JP1 Pin Number (1x10) Mach XO Device Pin Expansion Connector Pin
+3.3V 1 N/A N/A
TDO 2 31 J1-34
TDI 3 33 J1-35
N/C 4 N/A N/A
N/C 5 N/A N/A
TMS
1
626 J1-33
GND 7 N/A N/A
TCK
1
828 J1-32
N/C 9 N/A N/A
N/C 10 N/A N/A
1. Please note that some versions of the MachXO Starter Evaluation Board may have an incorrect silkscreen marking for these pins on the
printed circuit board. Please follow the connections guidelines in Table 4, and not the silkscreen markings on the board.

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MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
Table 5. Adjustable Voltage Resistor Values
Ordering Information
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
[phone] (Outside North America)
e-mail: techsuppor[email protected]
Internet: www.latticesemi.com
Revision History
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
ADJ Voltage R153 Resistor Value
3.3V 200
Ω
2.8V 150
Ω
2.5V 120
Ω
1.8V 51
Ω
1.5V 24
Ω
Description Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
MachXO 256C Evaluation Board - Starter LCMXO256C-S-EV
Date Version Change Summary
— —
Previous Lattice releases.
March 2007 01.3
Added Ordering Information section.
April 2007 01.4
Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
10

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MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
Appendix A. PCB Schematics
Figure 2. MachXO Starter Evaluation Board Expansion Port
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
LED0 LED2 LED6 LED4 LED3 LED7 LED8 SW6 SW7 SW5 SW4 SW3 SW2 SW1 SW0 IO32
IO35 IO36 IO43 IO44 IO45 IO46 IO47 IO48 IO49 IO50 IO51 IO52 IO42 IO41 IO40 IO39 IO38 IO37 IO30 IO31 IO33 IO34
IO61 IO60 IO59 IO58 IO57 IO55 IO54 IO53 IO29 IO28 IO27 TCK IO26 IO25 IO24 IO23 IO22 IO21 IO56 TDI TDO
IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO8 IO9
IO10 IO11 IO13 IO14 IO15 IO16 IO17 IO20 IO19
TMS
IO18 IO12
IO7 LED5
LED1
LED[8..0] SW[7..0] IO[61..0]
LED[8..0] SW[7..0] IO[61..0]
TDI TDO TCK
TMS
+3.3V+3.3VVCC_ADJ
+1.2V
Title Size Document Number Rev
Date: Sheet of
XO-STR-SCH B
MachXO Starter PCB - Expansion Port
A
13Wednesday, June 29, 2005
AB6 AB16
CB3
DB19
BB14
DB9
BB3
CB9
AB1
CB18
DB15
BB9
AB12
DB4
AB7
BB17
CB4
AB17
CB14
DB10
BB4
CB10
AB2
DB18
AB15
BB10 BB13
DB5
AB8
CB5
BB20
CB17
DB14 DB11
BB5
CB11
AB3 AB20
BB11 BB16
CB13
DB6
AB9
CB6
DB17
AB14
CB20
BB12 BB6
DB1
AB4
BB19
CB12
CB1
DB13
DB7
BB1
AB10
CB7
AB18
BB15
DB20
BB7
CB16
DB2
AB5
DB12
CB2
CB19
AB13
DB8
BB2
AB19
CB8
BB18
AB11
CB15
J1 QTH-030-01-F-D-TR
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30 31 31
32 32 33 33 34 34 35 35 36 36 37 37 3838 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 4848 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 5858 59 59 60 60
GND
61
GND
62
GND
63
GND
64
BB8
DB16
DB3
J2 QTH-030-01-F-D-TR
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30 31 31
32 32 33 33 34 34 35 35 36 36 37 37 3838 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 4848 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 5858 59 59 60 60
GND
61
GND
62
GND
63
GND
64

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MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
Figure 3. MachXO Starter Evaluation Board
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
LED1 LED5
IO26
SW2 SW6 SW7 SW3 SW4 SW1
TDO
TDI
TMS TCK
IO1 IO7 IO4
IO12 IO14
IO5 IO0
IO10
IO0 IO6 IO8
IO10 IO14 IO15 IO17
IO1 IO2 IO3 IO4 IO5 IO7 IO9
IO11 IO12 IO13 IO16 IO18 IO19 IO20
IO32 IO33
IO8 IO9
IO11
IO2 IO3
IO15 IO13
LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7
SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 IO41 IO40 IO39 IO38
TMS IO21 TCK IO22 IO23 TDO IO24
TDI
IO25 IO26 IO27 IO28 IO29
LED2
IO37 IO36 IO35 IO34 IO33 IO32 IO31 IO30
IO42 IO43 IO44 IO45 IO46 IO47 IO48 IO49 IO50 IO51 IO52
IO61 IO60 IO59 IO58 IO57 IO56 IO55 IO54 IO53
IO46 IO45 IO44 IO43 IO42 IO41 IO40 IO39 IO38 IO36 IO35 IO34 IO32 IO31 IO30 IO29 IO28 IO27 IO26 IO25 IO24 IO23 IO22 IO20 IO19 IO18 IO17 IO16 IO33 IO21 IO37
LED0
LED8
SW5 SW0
LED3 LED4
IO6
LED8 LED6 LED7
IO60 IO61 IO49 IO48 IO52 IO50 IO55 IO56 IO57 IO51 IO59 IO58 IO53
IO47
IO54
LED[8..0] SW[7..0] IO[61. .0]
TDO
TDI
TMS TCK
IO31
IO35
LED[8..0] SW[7..0] IO[61..0]
TDI
TDO TMS TCK
+3.3V
+3.3V
VCCIO0
+3.3V
+3.3V
VCCIO0
VCCIO1
VCCIO1 VCCIO1
VCCIO0 VCCIO1
VCCIO1
VCCIO0
VCC_CORE
VCC_CORE
Title Size Document Number Rev
Date: Sheet of
B
MachXO Starter PCB
B
23Wednesday, June 29, 2005
R41DNI
GND_44
R53DNI
R52DNI
IO9
IO22
GND_21
IO23
R131220
R31DNI
IO41
IO11
R123DNI
D6LED
R115DNI
R36DNIR14010K
R39DNI
R116DNI
GND_51
R47DNI
R23DNI
C1
0.1uF
GND_38
R108DNI
R4DNI
R44DNI
IO45 IO53
D2LED
R11DNI
GND_7
GND_37 GND_56
R19DNI
GND_59
R101DNI
IO6
R133220
SW3
1 4 2 3
IO38
IO29
R68DNI
IO49
R2DNI
R17DNI
D8LED
R71DNI
R124DNI
IO57
R95DNI
R117DNI
IO62
R107DNI
R97DNI
IO30
GND_28
R63DNI
GND_45
IO10
IO15
GND_22
IO25
R8DNI
R13810K
IO12
GND_27
R56DNI
SW1 SWDIP-8 CTS 208-8
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
R73DNI
R110DNI
D3LED
GND_52
SW2
EVQ-QWP01W
1 4 2 3
GND_24
R80DNI
IO46 IO54
R50DNI
R75DNI
R145 DNI
R114DNI
R6DNI
GND_8
R84DNI
R77DNI
GND_23
R88DNI
GND_60
R46DNI
IO7
R24DNI
IO18
GND_17
R126220
IO31
R14DNI
R3DNI
R92DNI
R85DNI
R78DNI
R66DNI
GND_13
IO3
R86DNI
IO55
R28DNI
R18DNI
R13610K
GND_30
R102DNI
R14110K
GND_46
R60DNI
IO16
GND_15
R1DNI
IO13
GND_3
R76DNI
R128220
GND_29
R106DNI
R96DNI
R13410K
IO32
GND_53
GND_26
R62DNI
R59DNI
IO39 IO47 IO58
GND_1
R120DNI
R111DNI
GND_25
GND_41
IO8
R130220
IO19
GND_18
IO33
R70DNI
GND_14
R118DNI
R32DNI
R49DNI
R122DNI
R113DNI
R5DNI
R7DNI
R83DNI
R29DNI
IO56
R40DNI
GND_32
GND_61
R55DNI
R45DNI
R25DNI
TQFP 100
U1
MACHXO 256
PR3D 69
TMS
26
PL9B
27
TCK
28
PB2A
29
PB2B
30
TDO
31
PB2C
32
TDI
33
PB2D
34
VCC
35
PB3A/PCLKT1_1
36
PB3B
37
PB3C/PCLKT1_0
38
PB3D
39
GND
40
VCCIO1
41
GNDIO1
42
PB4A
43
PB4B
44
PB4C
45
PB4D
46
PB5A
47
SLEEPN
48
PB5C
49
PB5D
50
PR9B 51 PR9A 52 PR8B53 PR8A54
PR7D 55 PR7C 56
PR7B 57 PR7A 58 PR6B 59
PL3D
6
PL4A
7
PL4B
8
PL5A
9PR4A 68
PR4B 67 PR5A 66 PR5B 65
PR5C 64 PR5D 63
GNDIO0 62
PR6A 61
VCCIO0 60
VCCIO1
24
PL3B
4
PL7C
19
PL9A
23
PL2A
1
PL8A
21
GNDIO1
25
PL3C
5
PL3A
3PL2B 2
PL8B
22
PL7D
20
PL5D/GSR_N
14
PL5B
11
PL6A
15
PL5C
13
VCCIO1
10
PL6B/TSALL
16
PL7A
17
GNDIO1
12
PL7B
18
PT5A 79
PT5B 78
PT5C 77
PR2A 76
GNDIO0 75
VCCIO0 74
PR2B 73 PR3A 72 PR3B 71
PR3C 70
PT2B 99
PT2A 100
PCLKT0_1/PT4B 85
GND84
PT4C 83
PT4D 82
PT4E 81
PT4F 80
PT2C 98
PT2D 97
PT2E 96
PT2F 95
PT3A 94
GNDIO0 93
VCCIO0 92
PT3B 91
VCC 90
PT3C 89
VCCAUX 88
PT3D 87
PCLKT0_0/PT4A 86
D1LED
GND_39
R13DNI
R91DNI
R37DNI
R30DNI
IO42
GND_16
IO50
GND_4
IO14
R132220
R34DNI
GND_31
R38DNI
R27DNI
R15DNI
D7LED
GND_54
R103DNI
R42DNI
R51DNI
IO40 IO48
R65DNI
IO59
GND_2
R21DNI
R13910K
R142 10K
R105DNI
R93DNI
IO34
GND_42
IO1
R22DNI
IO20
GND_19
R61DNI
IO35
R58DNI
Y1 33.33MHz
EN
1
GND
2OUT 3
VCC 4
R99DNI
IO26
R72DNI
GND_49
GND_34
GND_62
R100DNI
R143 10K
GND_40
R10DNI
IO43
R67DNI
IO51
D5LED
R81DNI
R48DNI
GND_5 GND_11
R74DNI
R112DNI
GND_33
GND_9
R82DNI
GND_57
IO4
R13710K
R89DNI
GND_47
R54DNI
R13510K
R125220
IO17
D4LED
R90DNI
R79DNI
IO24
R35DNI
IO60
R87DNI
R26DNI
R16DNI
R69DNI
GND_43
IO2
R119DNI
R43DNI
IO21
GND_20
IO37
R127220
R64DNI
IO27
R20DNI
GND_50
R104DNI
R94DNI
IO36GND_36
GND_55
R201 DNI
IO44 IO52
D9LED
GND_6 GND_12
GND_35
R98DNI
R129220
R144 10K
IO28
GND_58
IO5
GND_48
R9DNI
GND_10
R33DNI
R57DNI
JP1
HEADER1X10
1 2 3 4 5 6 7 8 9
10
R121DNI
R109DNI
IO61
R12DNI
XO-STR-SCH

11
MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
Figure 4. MachXO Starter Evaluation Board – Power Section
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
VIN
VINVIN
+3.3V
+3.3V
+1.2V
VCC_ADJ
VCC_CORE
VCCIO0VCCIO1
VCC_ADJ+3.3VVCCIO0
VCCIO1 VCC_CORE+1.2V
+3.3V
Title Size Document Number Rev
Date: Sheet of
XO-STR-SCH
B
MachXO Starter PCB – Power Section
A
33Wednesday, June 29, 2005
C13 0.1uF
+
C4
10uF
C17
0.1uF
R157* DNI R150 DNI
U4 RC1117X/SOT223
GND
1
VOUT 2
VIN
3
TAB 4
+
C7
10uF
J4 PWR JACK
3 2 1
R146220
C8
0.1uF
D12RED
C12
0.1uF
C16 0.1uF
+
C2
10uF
R149
120
+
C5 10uF
D10RED
R151 0
C11 0.1uF
R153
120
R154220
C15 0.1uF
+
C6 10uF
U3 RC1117X/SOT223
GND
1
VOUT 2
VIN
3
TAB 4
R1480
U2 RC1117X/SOT223
GND
1
VOUT 2
VIN
3
TAB 4
+
C3
10uF
R152 DNI
C10 0.1uF
R200 DNI
C14 0.1uF
TP0
R
*NOTE: Silkscreen markings are reversed for R156 and R157
on boards marked as Rev. B.
156* 0
R147 120
C9 0.1uF

12
MachXO Starter Evaluation Board
Lattice Semiconductor User’s Guide
Appendix B. PCB Layout Diagrams
Figure 5. MachXO Starter Evaluation Board Layout Diagrams
Figure 1. Top Silkscreen
Figure 3. Solder Side Layout
Figure 2. Component Side Layout
Figure 4. Bottom Silkscreen

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