Motorola MVME135 User manual

MVMEI35/ D2
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(f!yMOTOROLA
HVHE135/135-1fKV"E136
CUSTOMER lmER
HVHEl3l/l)
SEPTEMBER 1987
This letter ;s directed to customers using MVMEl35Bug, Revision 1.0, and to
software designers writing code for the MC6B681 OUART on the MVME135. The
purpose is to clarify an error in the data sheet on the H(68681 which defines
the reset condition of the Interrupt Status Register (lSR) as $00. Two
potential situations exist th at can cause this register to not be read as SOO
after a power-up or reset condition.
The first case involves bits two and six of the lSR. the Delta Break bits for
each serial port. Due to an anomaly in the chip circuitry, either of these
bits may be set after a power-up condition. This anomaly has been verified by
both vendors of the chip (Motorola and Signetlcs) and should not be considered
fatal faults in the
part. as their power-up conditions will not affect normal
operation of these bits. The proper initialization sequence for these bits is
to write all port control registers to desired values, then issue a " Reset
Channel x Break Change Interrupt" command for each channel. At this point,
the
state of these bits will be valid and further operations of these bits
will be accurate.
The second case involves bit three of the ISR, the Counter/ Timer Ready bit.
This bit may be set after a power-up or reset condition and prior to being
read by software In the lSR. The reason for this is that the HC68681 powers
up in the free running timer mode. and the timer may reach the end of a count-
down sequence, setting the Counter/Tim~r Ready bit at any time after release
of the reset line. This
status condition is normal to the device and will not
affect normal operation of the part. The proper Initialization sequence for
the
HC68681 timer Is to initialize the desired timer modes, then perform a
read of the Stop Counter command address to clear ISR bit three. At this
pOint. further setting of the bit will be due to normal counter/timer
operation
and may be considered valid.
Due to operation of the ISR In the MC68681 as described above. intermittent
failures of the
MVMEI358ug. Revision 1.0, confidence test at test SAO may be
observed. These failures are related to the ISR not containing SOO after
reset. As described, this is not a fatal error, and the MVHE135Bug will
operate normally
after exiting the confidence test. Future releases of the
MVMEI35Bug will correct for the operation of the HC68681 and will not
demonstrate this error.
We apologize for any inconvenience this may cause.
:m,. ... '''UO''._ .. __ lY

-- - -- ----- ----------------------------
BUSINESS REPLY MAIL
FIRST CLASS MAIL PERMIT NO . 2565 PHOENIX, ARIZONA
POSTAGE WILL BE PAID BY ADDRESSEE
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IN THE
UNITED STATES
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SAFETY SUMMARY
SAFETY DEPENDS ON YOU
The following general safety precautions must be observed during all phases of operation. service, and
repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere
In this
manual violates safety standards of design, manufacture, and Intended use of the equipment.
Motorola Inc. assumes no /lability for the customer's failure to comply with these requirements. The
safety
precautions listed below represent warnings of certain dangers of which we are aware. You, as
the user of the product. should follow these warnings and all other safety precautions necessary for
the safe operation of the eq~lpment In your operating environment.
GROUND THE INSTRUMENT.
To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical
ground. The equipment is supplied with a three-conductor ac power cable. The power cable must either
be plugged into an approved three-contact electrical outlet or used with a three-contact to two-contact
adapter. with the grounding wire (green) firmly connected to an electrical ground (safety ground) at the
power outlet. The power jack and mating plug of the power cable meet International Electrotechnical
Commission (IEC) safety standards.
DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE.
Do not operate the equipment in the presence of flammable gases or fumes. Operation of any electrical
equipment in such an environment constitutes a definite safety hazard.
KEEP AWAY FROM LIVE CIRCUITS.
Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or
other qualified maintenance personnel may remove equipment covers for internal subassembly or
component replacement or any internal adjustment. Do not replace components with power cable
connected. Under certain conditions, dangerous voltages may exist even with the power cable removed.
To avoid injuries. always disconnect power and di~charge circuits before touching them.
DO NOT SERVICE OR ADJUST ALONE.
Do not attempt internal service or adjustment unless another person, capable of rendering first aid and
resuscitation. is present.
USE CAUTION WHEN EXPOSING OR HANDLING THE CRT.
Breakage of the Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implo-
sion). To prevent CRT implosion, avoid rough handling or jarring of the equipment. Handling of the
CRT
should be done only by qualified maintenance personnel USing approved safety mask and gloves.
DO NOT SUBSTITUTE PARTS OR MODIFY EQUIPMENT.
Because of the danger of introducing additional hazards, do not install substitute parts or perform any
unauthorized modification of the equipment. Contact Motorola Field Service Division for service and
repair to ensure that
safety features are maintained.
DANGEROUS PROCEDURE WARNINGS.
Warnings, such as the example below, precede potentially dangerous procedures throughout this
manual. Instructions contained in the warnings must be followed. You should also employ all other
safety precautions which you deem necessary for the operation of the equipment in your operating
environment.
WARNING
Dangerous voltages, capable 01 causing death, are present In this equipment. Use extreme
caution when handling, testing, and adjusting.
SP015163 R.l (1/88)

PREFACE
This manual provides general information, hardware preparation,
installation instructions, functional description, and support
information for the MVME135/MVME136 Monoboard Series of 32-Bit
Microcomputers.
This manual is intended for anyone who wants to design OEM systems,
supply additional capabil ity to an existing compatible system or in
a 1 ab environment for experimental purposes.
A bas i c knowl edge of computers and di gita 1 1ogi cis assumed.
To use this manual, you should be faimilar with the publications
listed in the Re7ated Documentation paragraph in Chapter 1 of this
manual.

The computer programs stored in the read only memories of this device contain
material copyrighted
by r10torola Inc., first published 1988. and may be used
only under a license such as the License for Computer Programs (Article 14)
contained in Motorola's Terms and Conditions of Sale. Rev. 1/79.
WARNING
THIS EQUIPMENT GENERATES, USES, AND CAN RADIATE RADIO
FREQUENCY ENERGY AND IF NOT INSTALLED AND USED IN
ACCORDANCE WITH THE INSTRUCTIONS MANUAL, MAY CAUSE
INTERFERENCE TO RADIO COMMUNICATIONS. IT HAS BEEN TESTED
AND FOUND TO COMPLY WITH THE LIMITS FOR A CLASS A
COMPUTING DEVICE PURSUANT TO SUBPART J OF PART 15 OF FCC
RULES, WHICH ARE DESIGNED TO PROVIDE REASONABLE PROTECTION
AGAINST SUCH INTERFERENCE WHEN OPERATED IN A COMMERCIAL
ENVIRONMENT. OPERATION OF THIS EQUIPMENT IN A RESIDENTIAL
AREA IS LIKELY TO CAUSE INTERFERENCE IN WHICH CASE THE
USER, AT HIS OWN EXPENSE, WILL BE REQUIRED TO TAKE
WHATEVER MEASURES NECESSARY TO CORRECT THE INTERFERENCE.
VMEmodule, VSBbus. and 135bug are trademarks of Motorola Inc.
Second Ed it ion
Copyright 1989 by r10torola Inc.
First Edition April 1987

MYMEI35, MYMEI35-1, MVMEI35A,
MVME136, AND MVMEl36A
32-BIT MICROCOMPUTERS
USER'S MANUAL
(MVMEI35jD2)

The information in this document has been carefully checked and is
believed to be entirely reliable. However, no responsibility is
assumed for inaccuracies. Furthermore, Motorola reserves the right
to make changes to any products herei n to improve rel i abi 1i ty,
function, or design. Motorola does not assume any liability arising
out of the application or use of any product or circuit described
herein; neither does it convey any license under its patent rights
or the rights of others.

TABLE OF CONTENTS
CHAPTER 1 - GENERAL INFORMATION
1.1
1.2
1.3
1.3.1
1.3.2
1.4
1.5
1.6
1.7
I NTRODUCT ION ...•••.••.•..•.......•...........••.•
FEATURES .....•..••.•.•••..•.•....••..............
SPECIFICATIONS ................................. ..
Cooling Requirements •.....•.•••••••.•..•....•.
FCC Comp 1i ance •.•.•.......•••.••..••.•.•......
GENERAL DESCRIPTION ............................. .
MVME135/136 CONFIGURATIONS ..•.•.............••.•.
REFERENCE DOCUMENTATION ...............•.....••...
MANUAL TERMINOLOGY .............................. .
CHAPTER 2 - HARDWARE PREPARATION AND INSTALLATION
Page
1-1
1-1
1-2
1-4
1-4
1-5
1-5
1-6
1-7
2.1 INTRODUCTION.. .
.. • .. . .. .. . . .. .. . . .... .. . . .. . . .. .. 2-1
2.2
UNPACKING INSTRUCTIONS .... ...•.••••••... ......... 2-1
2.3
HARDWARE PREPARATION............................. 2-1
2.3.1 VMEbus Lock For VSBbus (Jl) .... ..... ......•... 2-4
2.3.2 Bus Grant/Request Level Select (J2) ........... 2-4
2.3.3 Factory Test Jumper (J5) .. ........ .•.•..••.... 2-6
2.3.4 RAM Acknowledge Mode (J6) .. ........... .....••• 2-6
2.3.5 ROM Size Select (J7) •.•................. ...••• 2-7
2.3.6 DRAM Address Multiplex Select (J8) •.........•• 2-8
2.3.7 Local/VMEbus Timeout Disable (Jll) ............ 2-8
2.3.8 DRAM Cycle Start Mode Select (J12) .......••.•. 2-9
2.3.9 External Timer Select (JI3,J14) ••.......•.•... 2-10
2.4 SERIAL PORT CABLING.............................. 2-11
2.4.1 DB-9 To DB-25 Cable Connection .•.............. 2-11
2.5 VME CHASSIS INSTALLATION •...•.................... 2-12
CHAPTER 3 - OPERATING INSTRUCTIONS
3.1 INTRODUCTION.............. ........ ...... ......... 3-1
3.2 FRONT PANEL...................................... 3-1
3.2.1 LED Indicators................................ 3-1
3.2.2 ABORT Switch (Sl) ............................. 3-1
3.2.3 RESET Switch (S2) ............................. 3-1
3.2.4 Mapping Switch (S3) ........................... 3-3
3.2.5 System Configuration Switch (S4) ...........•.. 3-10
3.3 MEMORY MAP AND MAP DECODER .•.•.•..•...••...••...• 3-11
3.3.1 MVME135/135-1/135A Main Memory Map •.•......... 3-12
3.3.2 MVME136/135A Main Memory Map .....•............ 3-13
vii

TABLE OF CONTENTS (cant.)
Page
CHAPTER 4 - FUNCTIONAL DESCRIPTION
4.1 INTRODUCTION ..................................... 4-1
4.2 GENERAL DESCR 1 PTION .............................. 4-1
4.2.1 Data Bus Structure ... .................... ..... 4-1
4.2.2 M~m?ry Map....... ............................. 4-1
4.2.3 Tlmlng........... ............................. 4-1
4.2.4 MVMEI35/135-1/136 DRAM Cycle Times .... ........ 4-1
4.2.5 MVMEI35A/136A DRAM Cycle Times ........ ..... ... 4-4
4.2.6 ROM/PROM/EPROM/EEPROM Cycle Times ... .......... 4-4
4.2.7 VMEbus Cycle Times ........... ........... ...... 4-5
4.2.8 VMEbus Arbitration Time ... ............ ........ 4-5
4.3 t4C68020 MPU ...................................... 4-6
4.4 t4C68881 FPCP ..................................... 4-6
4.5 MC68851 PMMU ..................................... 4-6
4.6 DEBUG MONITOR FIRMWARE .. ...... .......... ......... 4-7
4.7 VME SUBSYSTEM BUS (VSBbus) ...... ............ ..... 4-7
4.8 DYNAMIC RAM...................................... 4-7
4.9 FUNCTION CODE ASSIGNMENTS. ... .................... 4-8
4.10
t4VME135/136 USE OF CPU SPACE..................... 4-8
4.10.1 MC68851 Breakpoint Support .......... .......... 4-9
4.10.2 MC68851 Breakpoint Operation .................. 4-10
4.10.3 MC68851 Breakpoint Architecture ............... 4-11
4.10.4 MC68851 Acknowledge Cycle Operation ........... 4-12
4.10.5 Access Level Control .......................... 4-12
4.10.6 Coprocessor Communications .................... 4-13
4.11 INTERRUPT HANDLER ................................ 4-14
4.12 ON BOARD ROM/PROM/EPROM ........................... 4-17
4.13 DUAL SERIAL PORTS ................................ 4-17
4.14 MVME135/136 TIMER ................................ 4-17
4.15 LOCAL CONTROL/STATUS REGISTERS ................... 4-18
4.15.1 Status Register Format And Functions .......... 4-19
4.15.2 Control Register Format And Functions ......... 4-21
4 .16 ~1UL TIPROCESSOR CONTROL/STATUS REGISTERS (MPCSR) .. 4-27
4.16.1 Base Address Selection ........................ 4-32
4.17 VSBbus CONTROL/STATUS REGISTER................... 4-33
4.17.1 VSBbus Control/Status Format and Functions .... 4-33
4.18 CONFIGURING A VME SUBSYSTEM BUS .................. 4-37
CHAPTER 5 - SUPPORT INFORMATION
vii i
5.1
5.2
5.2.1
INTRODUCTION .................................... .
INTERCONNECTION SIGNALS ......................... .
Connector PI Interconnect Signals ............ .
5-1
5-1
5-1

5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.3
5.4
TABLE OF CONTENTS (cont.)
Connector P2 Interconnect Signals ............ .
Connector J3 Interconnect Signal s ............ .
Connector J4 Interconnect Signals ............ .
Connector J9 Interconnect Signals ............ .
Connector J10 Interconnect Signals ........... .
PARTS LIST ...................................... .
SCHEMATIC DIAGRAMS .............................. .
Page
5-6
5-13
5-15
5-19
5-20
5-21
5-43
APPENDIX A - MVME135/135-1/136 PAL2 SOURCE LISTING ............. A-I
APPENDIX B - MVME135A/136A PAL2 SOURCE LISTING................. B-1
APPENDIX C - MVME135/136 LOCAL MEMORY MAP ...................... C-1
FIGURE 2-1.
FIGURE 3-1.
FIGURE 3-2.
FIGURE 3-3.
FIGURE 4-1.
FIGURE 4-2.
FIGURE 4-3.
FIGURE 4-4.
FIGURE 4-5.
FIGURE 4-6.
FIGURE 4-7.
FIGURE 4-8.
FIGURE 4-9.
FIGURE 4-10.
FIGURE 4-11.
FIGURE 4-12.
FIGURE 5-1.
FIGURE 5-2.
FIGURE 5-3.
FIGURE 5-4.
FIGURE 5-5.
LIST OF ILLUSTRATIONS
Jumper, Connector, And Switch Location Diagram ... .
MVME135/136 Front Panel .......................... .
MVME135/135-1/136 Slave Access Addressing ........ .
MVMEI35A/136A Slave Access Addressing ............ .
MVME135/135-1/136 Block Diagram .................. .
MVME135A/136A Block Diagram ...................... .
CPU Space Type Field Encoding .................... .
Breakpoint
Acknowledge Cycle Address Encoding .... .
Breakpoi nt
Regi sters ............................. .
Breakpoint
Acknowledge Data Register Format ...... .
Breakpoint
Acknowledge Control Register Format ... .
ALC Interface Logical Address Bus Encoding ....... .
Coprocessor Interface Address Bus Encoding ....... .
Serial Port Interconnections
..................... .
016/032 Default Data Segmentation ................ .
MPCSR And DRAM Address Mapping ................... .
MVME135/136 Parts Location Diagram ............... .
1Mb DRAM Mezzanine Board Parts Location Diagram .. .
4Mb DRAM Mezzanine Board Parts Location Diagram .. .
MVME135/136 By-Pass Board Parts Location Diagram ..
MVME135/136 Schematic Oiagram .................... .
2-2
3-2
3-4
3-7
4-2
4-3
4-9
4-10
4-11
4-11
4-12
4-13
4-14
4-17
4-27
4-35
5-33
5-38
5-40
5-42
5-45
ix

FIGURE 5-6.
FIGURE 5-7.
FIGURE 5-8.
TABLE I-I.
TABLE 1-2.
TABLE 2-1.
TABLE 3-1.
TABLE 3-2.
TABLE 3-3.
TABLE 3-4.
TABLE 4-1.
TABLE 4-2.
TABLE 4-3.
TABLE 4-4.
TABLE 4-5.
TABLE 4-6.
TABLE 4-7.
TABLE 4-8.
TABLE 5-1.
TABLE 5-2.
TABLE 5-3.
TABLE 5-4.
TABLE 5-5.
TABLE 5-6.
TABLE 5-7.
TABLE 5-8.
TABLE 5-9.
TABLE 5-HL
x
TABLE OF CONTENTS (cant.)
1Mb DRAM Mezzanine Schematic Diagram
4Mb DRAM Mezzanine Schematic Diagram
PMMU By-Pass Board Schematic Diagram
LIST OF TABLES
MVME135/136 Specifications ........................ .
MVME135/136 Configurations ........................ .
Jumper Block Placements ........................... .
MVME135/136 Front Panel LED Status ................ .
Function
Code Assignments ......................... .
MVMEI35/135-1/136 Main Memory Map ................. .
MVt~E135A/136A Main Memory Map ..................... .
MVMEl35/136 Timing ................................ .
Function
Code Assignments ......................... .
ALC Interface Registers Map ....................... .
MC68851 Coprocessor Interface Register Map ........ .
MC68881 Coprocessor Interface Register Map ........ .
Interrupt Handler Priority Assignments ............ .
Multiprocessor Control/Status Registers
........... .
Mapping On The VMEbus ............................. .
Connector PI Interconnect Signals ................. .
Connector P2 Interconnect Signal s ................. .
Connector J3 Interconnect Signals ................. .
Connector J4 Interconnect Signals ................. .
Connector J9 Interconnect Signals ................. .
Connector J 10 Interconnect Si gna 1s ................ .
MVME135/136 Parts List ............................ .
1Mb DRAM Mezzanine Board Parts List ............... .
4Mb DRAM Mezzanine Board Parts List ............... .
PMMU By-Pass Board Parts List ..................... .
Page
5-97
5 -113
5-131
1-2
1-6
2-3
3-3
3-11
3-12
3-13
4-3
4-9
4-13
4-14
4-15
4-15
4-28
4-30
5-1
5-6
5-13
5-15
5-19
5-20
5-21
5-37
5-39
5-41

GENERAL INFORMATION
CHAPTER 1 - GENERAL INFORMATION
1. 1 I NTRODUCTI ON
This user's manual provides general information, preparation and
installation instructions, operating instructions, functional
description, and support information for the MVME135/MVME136 series
of 32-bit microcomputers (refer to section 1.5 for the different
module configurations). Unless otherwise specified, these
microcomputers are referred to as the MVME135/136 throughout the
contents of thi s user's manua 1.
1. 2 FEATURES
The features of the MVMEl35/136 i ncl ude:
.MC68~2~ Virtual Memory Microprocessor with 32-bit address and data
at 16.67 MHz or 2~.~~ MHz .
• 1Mb of shared local DRAM with no wait cycles, 32-bit wide;
accessible from the VMEbus with optional parity (MVME135,
MVME135-1, and MVME136 versions only) .
• 4Mb of shared local DRAM with one wait cycle, 32-bit wide;
accessible from the VMEbus with optional parity (MVME135A version
only) .
• 4Mb of shared local DRAM with two wait cycles, 32-bit wide;
accessible from the VMEbus with optional parity (MVME136A version
only). Parity does not add any additional wait cycles for this
version .
• On-board socket for MC68881 Floating Point Coprocessor (FPCP) at
16.67 MHz or 2~.0~ MHz .
• On-board socket for MC68851 Demand Paged Memory Management Unit
(PMMU) at 16.67 MHz (MVMEl36 and MVME136A versions only) .
• Multi-master VME Subsystem Bus (VSBbus) interface; 32-bit
secondary bus support.
• VMEbus interface; 32-bi t address and data .
• VMEbus Interrupt Handler.
• Z8036A Programmabl e Ti mer Modul e.
• Periodic tick interrupt (level 6).
• Watchdog reset (momentary local reset, local reset and hol d, or a
system level reset may be software selected) .
• VSBbus can eliminate "software holes" in VMEbus memory map caused
by except ion tabl es and stacks.
1-1
I

I
GENERAL INFORMATION
eSingle level system controller capability (level is jumper
selectable).
eHigh level multiprocessor control and status registers used for
inter-processor signaling and communication.
e Round Robin requesting provides fairness of VMEbus mastership for
systems with multi pl e MVME135/136s (software sel ectabl e).
~Two front panel RS-232C serial ports with level translators;
eliminating the need for a transition board between the
MVME135/136 and a terminal or modem.
eTwo on-board ROM sockets for a capacity of 128Kb (configured for
Industry Standard JEDEC 28-pin ROM/PROM/EPROM devices; user
provided).
1.3 SPECIFICATIONS
General specifications for the ~'VMEI35/136 are provided in the
following table. Sections 1.2.2 and 1.2.3 detail cooling
requ i rements and FCC compl i ance, respect i vely.
TABLE 1-1. MVME135/136 SPECIFICATIONS
Characteristic Specification
Microprocessor MC68£120 32-bit microprocessor
Clock signal:
MVME135/135A/136/136A 16.67 MHz CPU clock frequency
MVME135-1 20.0£1 MHz CPU clock frequency
Power requirements:
MVMEI35/135-1/135A
MVME136/136A
1-2
+5 Vdc, 6.75 A maximum (5.6 A typical)
+12 Vdc, 5£1 rnA maximum (1£1 rnA typical)
-12 Vdc, 9£1 mA maximum (30 mA typical)
+5 Vdc, 7.00 A maximum (5.8 A typical)
+12 Vdc, 5£1 mA maximum (HI rnA typical)
-12 Vdc, 9£1 mA maximum (3£1 rnA typical)
NOTE: Backplane Connectors -- The P2 backplane
is not only necessary for 32-bit operation but
is also used to connect +5 V to the ~1VME135/136
module for current distribution. The module
draws 5.6 A under typical operation and should
not
be operated without a P2 backpl ane.

GENERAL INFORMATION
TABLE 1-1. MVME135/136 SPECIFICATIONS (cont.)
Characteristic
Addressing:
System Size
(Total on-/off-board)
ROM/EPROM
Serial I/O ports
Timer
Interrupts
On-board memory
MVME135/135-1
MVME136
MV~lEl35A
MVME136A
Temperatures:
Operating
Storage
Rel ative humidity
Physical size (PCB):
Hei ght x wi dth
Thickness
Specification
32-bits = 4 gigabytes 1 inear address space
Two EPROM/ROM sockets for 16Kb or 32Kb devices
using
+5 Vdc only (JEDEC standard 28-pin
devices; user supplied).
Two multi-protocol serial communications
channels with
RS-232C interface (connection
made vi a two DB -9 connectors from the front
panel).
A Z8036A programmable timer module with three
independent 16-bit timers.
Any seven possible VMEbus interrupts can be
recei ved by the MVMEl35/136. VSBbus has
interrupt capability. as do most on-board
devices.
1Mb, 0 wa it state wi thout parity and 1 wa it state
wi th pari ty.
1Mb, 1 wait state without parity and 2 wait
states with parity. The MC68851 Paged Memory
Management Unit (PMMU) adds 1 wait state to
local
memory accesses.
4Mb, 1 wait state with or without parity.
4Mb, 2 wait states with or without parity. The
r~C68851 Paged Memory Management Unit (PMMU)
adds 1 wait state to local memory accesses.
o to 50 degrees C (inlet air temperature with
forced
air cool ing)
- 40 to 85 degrees C
5% to 95% (non-condensing)
(not incl uding the
front panel)
6.30 inches (16.00 cm) x9.19 inches (23.34 cm)
0.062 inch (0.157 em)
1-3
I

I
GENERAL INFORMATION
TABLE 1-1. HVHE135/136 SPECIFICATIONS (cont.)
Characteristic
Part projections:
Component side
Solder side
Connectors:
VMEbus/VSBbus
RS-232C
1.3.1 Cool ing Requirements
Specification
0.50 inch (1.27 cm) maximum
0.067 inch (0.17 cm) maximum
DIN triple row, 96-pin male (PI, P2)
DB-9, 9-pin female (J9, J10)
Motorola VMEmodules are specified, designed, and tested to operate
reliably with an incoming air temperature range from 0 degrees C to
50 degrees C (32 degrees F to 122 degrees F) with forced air coo1i ng.
Temperature qualification is performed in a standard Motorola
VMEsystem 1000 chassis. Twenty-five watt load boards are inserted
in the two card slots, one on each side, adjacent to the board under
test to simulate a high power density system configuration. An
assembly of three axial fans, rated at 100 CFM per fan, is placed
directly under the MVME card cage. The incoming air temperature is
measured between the fan assembly and the card cage where the
incoming airstream first encounters the board under test. Test
software is executed as the module is subjected to ambient
temperature variations. Case temperatures of critical, high power
density integrated circuits are monitored to ensure component
vendors speci fi cat ions are not exceeded.
While the exact amount of airflow required for cooling depends on
the ambient air temperature and the type, number, and location of
boards and other heat sources, adequate cooling can usually be
achieved with 10 CFM flowing over the module. Less air flow is
required to cool the module in environments having lower maximum
ambients. Under more favorable thermal conditions it may be
possible to operate the module reliably at higher than 50 degrees C
with increased air flow. It is important to note that there are
several factors, in addition to the rated CFM of the air mover, which
determine the actual volume of air flowing over a module.
1.3.2 FCC Compl iance
The MVME135/136 module is tested in an FCC-compliant chassis, and
meets
the requirements for Class A equipment. FCC compliance was
achi eved under the foll owi ng condi t ions:
1-4

GENERAL INFORMATION
1. Shielded cables on all external I/O ports.
2. Cable shields connected to earth ground via metal shell
connectors bonded to a conductive module front panel.
3. Conductive chassis rails connected to earth ground. This
provides the path for connecting shields to earth ground.
4. Front panel screws properly tightened.
For minimum RF emissions, it is essential that the conditions above
be implemented; failure to do so could compromise the FCC compliance
of the equipment containing the modules.
1.4
GENERAL DESCRIPTION
The MVME135/136 is a high performance MC68020 microprocessor-based
module implemented on a VME double-high, single-wide form-factor.
The MVME135/136 incorporates an MC68020, a 32-bit address and data
microprocessor, a high level multiprocessor CSR, and 1Mb or 4Mb of
fast DRAM. Other main features provided include a Demand Paged
Memory Management Unit (PMMU), a Floating Point Coprocessor (FPCP),
and interfaces to the VMEbus and the VSBbus.
The MVME135/136 is designed for those applications which require
fast on-board RAM and a secondary bus (VSBbus). The features of the
MVME135/136 include high performance and an elegant architecture.
The MVME135/136 is especially suited to applications requiring
multiple processors where the efficiency of inter-processor
communication is important.
The 135bug resident debug package (refer to Motorola publication
MVME135BUG) is the firmware package designed for use with the
MVME135/136 modul e. 135bug provides a powerful system debuggi ng
tool for VMEmodule systems. This firmware features a one line
assembler/disassembler, provisions for upload/download, and disk
bootstrap commands. 135bug is available as an EPROM-based resident
package whi ch is plugged into IC sockets U54 and U56 on the
MVME135/136.
1.5 MVME135j136 CONFIGURATIONS
There are five module configurations available in the MVME135/136
series of 32-bit microcomputers. These configurations are listed in
the following table.
1-5
I

I
GENERAL INFORMATION
TABLE 1-2. MVME135/136 CONFIGURATIONS
Module CPU Clock On-Board MC68881 MC68851
Designation Cycle (MHz) Memory
(FPCP)
(PMMU)
MVME135
16.67 1Mb Yes No
MVMEl35-1
20.00 1Mb
Yes
No
MVME135A 16.67 4Mb Yes
No
MVME136
16.67 1Mb Yes Yes
MVME136A
16.67 4Mb
Yes
Yes
1. 6 REFERENCE DOCUMENTATION
The following publications may provide additional helpful
information. If not shipped with this product, they may be
purchased from Motorola's Literature Distribution Center, 616 West
24th Street, Tempe, Arizona 85282; telephone [phone].
DOCUM ENT TI TL E
MC68020 32-Bit Microprocessor U.M.
MC68851 Paged Memory Management Unit U.M.
MC68881 Floating-Point Coprocessor U.M.
MVME204-1/-2 Dual Ported Dynamic Memory U.M.
MVME204-2F Dual Ported Dynamic Memory U.M.
MVME224-1/ - 2 4/8Mb Dynami c Memory U.M.
MVSB2400 VSBchip U.M.
VME System Architecture Guide
VME Subsystem Bus (VSBbus) Specification
(RevA.1)
135bug Diagnostic/Debug Package U.M.
MOTOROLA
PUBLICATION NUMBER
MC68020UM/AD
MC68851UrVAD
MC68881UM/AD
MVME204
MVME204F
MVME224
MVSB2400
MVMESYSAM/D
MVMESB
MVME135BUG
NOTE: Although not shown in the above list, each Motorola MCD manual
publication number is suffixed with characters which
represent the revision level of the document, such as "D2"
(the second revision of a manual); a supplement bears the same
number as the manual but has a suffix such as "AI" (the first
suppl ement to the manual).
U.M. denotes User's Manual.
1- 6

GENERAL INFORMATION
Additional publications that may provide helpful information are
listed below.
ANSI/IEEE Standard 1014-1987
Versatile Backplane Bus: VMEbus
Zilog Z-CIO (Z8036) Counter/Timer
and Parallel I/O Unit Technical
Manual
1. 7 MANUAL TERMINOLOGY
Institute of Electrical and
Electronics Engineers, Inc.
345 East 47th Street
New York, New York 10017
Zilog Incorporation
1315 Del Avenue
Campbell, California 95008
[phone]
Throughout this manual, a convention has been maintained whereby
data and address parameters are preceded by a character which
specifies the numeric format as follows:
S
%
&
doll ar
percent
ampersand
specifies a hexadecimal number
specifies a binary number
specifies a decimal number
Unless otherwise specified, all address references are in
hexadecimal
throughout this manual.
An asterisk (*) following the signal name for signals which are
level significant denotes that the signal is true or valid when the
signal is low.
An asterisk (*) following the signal name for signals which are edge
significant denotes that the actions initiated by that signal occur
on high to low transition.
In this manual, assertion and negation are used to specify forcing a
signal to a particular state. In particular, assertion and assert
refer to a signal that is active or true; negation and negate
indicate a signal that is inactive or false. These terms are used
independently of the voltage level (high or low) that they
represent.
1-7
I