Phytec phyCORE-167CS User manual

A product of a PHYTEC Technology Holding company
phyCORE-167CR/
phyCORE-167CS
Hardware Manual
Edition November 2002

phyCORE-167CR/167CS
PHYTEC Meßtechnik GmbH 2002 L-527e_8
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark () and copyright () symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Meßtechnik GmbH assumes no responsibi-
lity for any inaccuracies. PHYTEC Meßtechnik GmbH neither gives any guarantee
nor accepts any liability whatsoever for consequential damages resulting from the
use of this manual or its associated product. PHYTEC Meßtechnik GmbH
reserves the right to alter the information contained herein without prior
notification and accepts no responsibility for any damages which might result.
Additionally, PHYTEC Meßtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Meßtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
Copyright 2002 PHYTEC Meßtechnik GmbH, D-55129 Mainz. Rights -
including those of translation, reprint, broadcast, photomechanical or similar
reproduction and storage or processing in computer systems, in whole or in part -
are reserved. No reproduction may occur without the express written consent from
PHYTEC Meßtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone] [e-mail] 1 [phone] [e-mail]
Technical
Support: [phone] [email protected] 1 [phone] [e-mail]
Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
8th Edition: November 2002

Contents
PHYTEC Meßtechnik GmbH 2002 L-527e_8
Preface ......................................................................................................1
1 Introduction .........................................................................................3
1.2 Block Diagram..............................................................................6
1.2 View of the phyCORE-167CR/167CS.........................................6
2 Pin Description.....................................................................................7
3 Jumpers..............................................................................................15
3.1 J1 Use of Pin 30 on the SRAM..................................................19
3.2 J2 Internal or External Program Memory..................................20
3.3 J3 Flash Addressing...................................................................20
3.4 J4, J5 A/D Reference Voltage ...................................................21
3.5 J6 Oscillator Watchdog / On-Chip Flash...................................22
3.6 J7, J8 Use of the External UART ..............................................22
3.7 J9, J10 Configuration of P3.3, P3.4 for I²C Bus........................23
3.8 J11 RTC Interrupt Output..........................................................24
3.9 J12 Write Protection of EEPROM/FRAM................................24
3.10 Second Serial Interface Configuration J13, J14 ........................25
3.11 J15 Address of the Serial EEPROM/ FRAM ............................25
3.12 CAN Interfaces J16, J17, J18, J19.............................................26
3.13 J20 Remote Download Source...................................................27
3.14 J21, J22 Serial Interface.............................................................28
3.15 J23, J24 Microcontroller Supply Voltage..................................29
4 System Configuration........................................................................31
4.1 System Startup Configuration.....................................................31
5 Memory Models.................................................................................35
5.1 Bus Timing .................................................................................39
6 Serial Interfaces.................................................................................41
6.1 RS-232 Interface.........................................................................41
6.2 CAN Interface.............................................................................42
7 The Real-Time Clock RTC-8563 (U10)...........................................43
8 Serial EEPROM/FRAM (U9)...........................................................44
9 Remote Supervisory Chip (U8) ........................................................45
10 Flash Memory (U1)............................................................................46
11 Battery Buffer and Voltage Supervisor Chip (U13).......................47
12 Technical Specifications....................................................................49
13 Hints for Handling the phyCORE-167CR/167CS..........................51

phyCORE-167CR/167CS
PHYTEC Meßtechnik GmbH 2002 L-527e_8
14 The phyCORE-167CR/167CS on the phyCORE Development
Board HD200.....................................................................................53
14.1 Concept of the phyCORE Development Board HD200.............53
14.2 Development Board HD200 Connectors and Jumpers...............55
14.2.1 Connectors.....................................................................55
14.2.2 Jumpers on the phyCORE Development
Board HD200 ................................................................57
14.2.3 Unsupported Features and Improper Jumper Settings ..59
14.3 Functional Components on the phyCORE Development
Board HD200 .............................................................................60
14.3.1 Power Supply at X1.......................................................61
14.3.2 Activating the Bootstrap Loader ...................................63
14.3.3 First Serial Interface at Socket P1A..............................65
14.3.4 Second Serial Interface at Socket P1B..........................67
14.3.5 First CAN Interface at Plug P2A...................................72
14.3.6 Second CAN Interface at Plug P2B ..............................77
14.3.7 Programmable LED D3.................................................82
14.3.8 Pin Assignment Summary of the phyCORE, the
Expansion Bus and the Patch Field...............................82
14.3.9 Battery Connector BAT1...............................................90
14.3.10 Releasing the /NMI Interrupt ........................................90
14.3.11 DS2401 Silicon Serial Number.....................................90
14.3.12 Pin Header Connector X4 .............................................91
15 debugCORE-167CR/167CS .............................................................93
15.1 Components of the debugCORE................................................93
15.2 debugADAPTER-167 ................................................................95
15.2.1 The Quad-Connector.....................................................96
15.3 Physical Dimensions...................................................................98
Index ....................................................................................................99

Contents
PHYTEC Meßtechnik GmbH 2002 L-527e_8
Index of Figures
Figure 1: Block Diagram phyCORE-167CR/167CS....................................6
Figure 2: View of the phyCORE-167CR/167CS.........................................6
Figure 3 Pinout of the phyCORE-connector (Top View, with Cross
Section Insert)...............................................................................9
Figure 4: Numbering of the Jumper Pads...................................................15
Figure 5: Location of the Jumpers (Component Side / Soldering Side) ....15
Figure 6: Memory Model Examples ..........................................................38
Figure 7: Physical Dimensions...................................................................49
Figure 8: Modular Development and Expansion Board Concept
with the phyCORE-167CR/167CS.............................................54
Figure 9: Location of Connectors on the phyCORE
Development Board HD200.......................................................55
Figure 10: Numbering of Jumper Pads ........................................................57
Figure 11: Location of the Jumpers (View of the Component Side)...........57
Figure 12: Default Jumper Settings of the phyCORE Development
Board HD200 with phyCORE-167CR/167CS ...........................58
Figure 13: Connecting the Supply Voltage at X1 ........................................61
Figure 14: Pin Assignment of the DB-9 Socket P1A as First RS-232
(Front View) ...............................................................................65
Figure 15: Pin Assignment of the DB-9 Socket P1B as Second
RS-232 (UART populated, Front View) ....................................69
Figure 16: Pin Assignment of the DB-9 Socket P1B as Emulated
RS-232 (Front View)..................................................................70
Figure 17: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver
on phyCORE-167CR/167CS, Front View) ................................72
Figure 18: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver
on Development Board)..............................................................73
Figure 19: Pin Assignment of the DB-9 Plug P2A (CAN Transceiver
on Development Board with Galvanic Separation)....................76

phyCORE-167CR/167CS
PHYTEC Meßtechnik GmbH 2002 L-527e_8
Figure 20: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on phyCORE-167CS, only with C167CS).................................77
Figure 21: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on Development Board, only with C167CS)..............................78
Figure 22: Pin Assignment of the DB-9 Plug P2B (CAN Transceiver
on Development Board with Galvanic Separation, only
with C167CS).............................................................................81
Figure 23: Pin Assignment Scheme of the Expansion Bus..........................83
Figure 24: Pin Assignment Scheme of the Patch Field................................83
Figure 25: Connecting the DS2401 Silicon Serial Number.........................91
Figure 26: Pin Assignment of the DS2401 Silicon Serial Number..............91
Figure 27: Positions of the Additional Components on the
debugCORE-167CR/167CS.......................................................94
Figure 28: Physical Dimensions debugCORE-167CR/167CS ....................98

Contents
PHYTEC Meßtechnik GmbH 2002 L-527e_8
Index of Tables
Table 1: Pinout of the phyCORE-Connector X1......................................13
Table 2: Jumper Settings...........................................................................18
Table 3: J1 SRAM Capacity Configuration.............................................19
Table 4: J2 Code Fetch Selection.............................................................20
Table 5: J3 Addressing the Flash.............................................................21
Table 6: J4, J5 A/D Converter Reference Voltage ..................................21
Table 7: J6 Activating the Oscillator Watchdog......................................22
Table 8: J7, J8 Control Signals for Optional External UART.................23
Table 9: J9, J10 I²C Bus Configuration ...................................................23
Table 10: J11 RTC Interrupt Configuration ..............................................24
Table 11: J12 Write Protection of EEPROM/FRAM................................24
Table 12: J13, J14 Second Serial Interface Configuration ........................25
Table 13: J15 EEPROM/FRAM Address Configuration ..........................25
Table 14: J16, J17, J18, J19 CAN Interface Configuration.......................27
Table 15: J20 Remote Download Source Configuration...........................27
Table 16: J21, J22 First Serial Interface Configuration.............................28
Table 17: J23, J24 Configuration VCC Pins Microcontroller ...................29
Table 18: Functional Settings on Port P0 for System Startup
Configuration..............................................................................32
Table 19: System Startup Configuration Registers.....................................34
Table 20: Memory Device Options for U9.................................................44
Table 21: Improper Jumper Setting for JP16 on the
Development Board....................................................................59
Table 22: Improper Jumper Setting for JP30/33 on the
Development Board....................................................................59
Table 23: JP9 Configuration of the Main Supply Voltage VCC...............61
Table 24: JP9 Improper Jumper Settings for the Main Supply Voltage.....62
Table 25: JP28 Configuration of the Boot Button......................................63

phyCORE-167CR/167CS
PHYTEC Meßtechnik GmbH 2002 L-527e_8
Table 26: JP28 Configuration of a Permanent Bootstrap Loader Start.....64
Table 27: JP22, JP23, JP10 Configuration of Boot via RS-232................64
Table 28: Improper Jumper Settings for Boot via RS-232.........................64
Table 29: Jumper Configuration for the First RS-232 Interface ................65
Table 30: Improper Jumper Settings for DB-9 Socket P1A as
First RS-232 ...............................................................................66
Table 31: Jumper Configuration of the DB-9 Socket P1B
(no second RS-232)....................................................................67
Table 32: Improper Jumper Settings for DB-9 Socket P1B
(no second RS-232)....................................................................68
Table 33: Jumper Configuration of the DB-9 Socket P1B
(UART, 2nd RS-232)...................................................................69
Table 34: Jumper Configuration of the DB-9 Socket P1B
(2nd RS-232 via Software Emulation).........................................70
Table 35: Improper Jumper Settings for DB-9 Socket P1B
(2nd RS-232 via Software Emulation).........................................71
Table 36: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the phyCORE-167CR/167CS............................72
Table 37: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the Development Board.....................................73
Table 38: Improper Jumper Settings for the CAN Plug P2A
(CAN Transceiver on the Development Board).........................74
Table 39: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the Development Board with
Galvanic Separation ...................................................................75
Table 40: Improper Jumper Settings for the CAN Plug P2A
(CAN Transceiver on Development Board with
Galvanic Separation)..................................................................76
Table 41: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the phyCORE-167CS ........................................77
Table 42: Jumper Configuration for CAN Plug P2B using the CAN
Transceiver on the phyCORE-167CS ........................................78

Contents
PHYTEC Meßtechnik GmbH 2002 L-527e_8
Table 43: Improper Jumper Settings for the CAN Plug P2B (CAN
Transceiver on the Development Board, only with C167CS) ....79
Table 44: Jumper Configuration for CAN Plug P2A using the CAN
Transceiver on the Development Board with Galvanic
Separation (only with C167CS)..................................................80
Table 45: Improper Jumper Settings for the CAN Plug P2B
(CAN Transceiver on Development Board with
Galvanic Separation) ..................................................................81
Table 46: JP17 Configuration of the Programmable LED D3...................82
Table 47: Pin Assignment Data/Address Bus for the
phyCORE-167CR/167CS / Development Board /
Expansion Board.........................................................................84
Table 48: Pin Assignment Port P2, P3, P4 for the
phyCORE-167CR/167CS / Development Board /
Expansion Board.........................................................................85
Table 49: Pin Assignment Port P5, P6, P7, P8 for the
phyCORE-167CR/167CS / Development Board /
Expansion Board.........................................................................86
Table 50: Pin Assignment Interface Signals for the
phyCORE-167CR/167CS / Development Board /
Expansion Board.........................................................................87
Table 51: Pin Assignment Control Signals for the
phyCORE-167CR/167CS / Development Board /
Expansion Board.........................................................................87
Table 52: Pin Assignment Power Supply for the
phyCORE-167CR/167CS / Development Board /
Expansion Board.........................................................................88
Table 53: Unused Pins on the phyCORE-167CR/167CS /
Development Board / Expansion Board.....................................89
Table 54: JP28 Releasing the /NMI Interrupt............................................90
Table 55: JP19 Jumper Configuration for Silicon Serial Number Chip.....90
Table 56: Pinout Pin Header Row X3 on the
debugCORE-167CR/167CS.......................................................94
Table 57: Connector Layout of the of the Quad-Connector (X6)...............97

phyCORE-167CR/167CS
PHYTEC Meßtechnik GmbH 2002 L-527e_8

Preface
PHYTEC Meßtechnik GmbH 2002 L-527e_8 1
Preface
This phyCORE-167CR/167CS Hardware Manual describes the
board’s design and functions. Precise specifications for Infineon’s
C167CR/C167CS microcontroller series controller can be found in
the enclosed microcontroller Data Sheet/User's Manual. If software is
included please also refer to additional documentation for this
software.
In this hardware manual and in the attached schematics, low active
signals are denoted by a "/" in front of the signal name (i.e.: /RD). A
"0" indicates a logic-zero or low-level signal, while a "1" represents a
logic-one or high-level signal.
Declaration of Electro Magnetic Conformity of the
PHYTEC phyCORE-167CR/167CS
PHYTEC Single Board Computers (henceforth products) are designed
for installation in electrical appliances or as dedicated Evaluation
Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD-dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product's pin header rows are longer than 3 m.

phyCORE-167CR/167CS
2PHYTEC Meßtechnik GmbH 2002 L-527e_8
PHYTEC products fulfill the norms of the European Union’s
Directive for Electro Magnatic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
The phyCORE-167CR/167CS is one of a series of PHYTEC Single
Board Computers that can be populated with different controllers and,
hence, offers various functions and configurations. PHYTEC supports
all common 8- and 16-bit controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional micro-, mini- and phyCORE
OEM modules, which can be embedded directly into the user’s
peripheral hardware, design.
PHYTEC's microcontroller modules allow engineers to shorten
development horizons, reduce design costs and speed project concepts
from design to market.

Introduction
PHYTEC Meßtechnik GmbH 2002 L-527e_8 3
1Introduction
The phyCORE-167CR/167CS belongs to PHYTEC’s phyCORE
Single Board Computer module family. The phyCORE SBCs
represent the continuous development of PHYTEC Single Board
Computer technology. Like its mini-, micro- and nanoMODUL
predecessors, the phyCORE boards integrate all core elements of a
microcontroller system on a subminiature board and are designed in a
manner that ensures their easy expansion and embedding in peripheral
hardware developments.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin
package. The increased pin package allows dedication of
approximately 20 % of all pin header connectors on the phyCORE
boards to Ground. This improves EMI and EMC characteristics and
makes it easier to design complex applications meeting EMI and
EMC guidelines using phyCORE boards even in high noise
environments.
phyCORE boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD components and laser-drilled
Microvias are used on the boards, providing phyCORE users with
access to this cutting edge miniaturization technology for integration
into their own design.

phyCORE-167CR/167CS
4PHYTEC Meßtechnik GmbH 2002 L-527e_8
The phyCORE-167CR/167CS is a subminiature (60 x 53 mm)
insert-ready Single Board Computer populated with Infineon’s
C167CR or C167CS microcontroller. Its universal design enables its
insertion in a wide range of embedded applications. All controller
signals and ports extend from the controller to high-density pitch
(0.635 mm) connectors aligning two sides of the board, allowing it to
be plugged like a “big chip” into a target application.
Precise specifications for the controller populating the board can be
found in the applicable controller User’s Manual or Data Sheet. The
descriptions in this manual are based on the Infineon
C167CR/C167CS. No description of compatible microcontroller
derivative functions is included, as such functions are not relevant for
the basic functioning of the phyCORE-167CR/167CS.

Introduction
PHYTEC Meßtechnik GmbH 2002 L-527e_8 5
The phyCORE-167CR/167CS offers the following features:
•subminiature Single Board Computer (60 x 53 mm) achieved
through modern SMD technology
•populated with the Infineon C167Cx microcontroller (QFP-144
packaging) featuring up to two1on-chip 2.0B CAN modules
•improved interference safety achieved through multi-layer PCB
technology and dedicated Ground pins
•controller signals and ports extend to two 100-pin high-density
(0.635 mm) Molex connectors aligning two sides of the board,
enabling it to be plugged like a “big chip” into target application
•16-bit, demultiplexed bus mode
•20 MHz clock frequency (100 ns instruction cycle)
•16 MB address space
•256 kByte to 2 MB external Flash on-board2
•on-board Flash programming, no dedicated Flash programming
voltage required through use of 5 V Flash devices
•256 kByte to 1 MB RAM on-board2
•up to 21CAN interfaces with Philips 82C251 CAN transceiver, or
Siliconix’ Si9200EY
•I²C Real-Time Clock with internal quartz
•4 to 8 kByte I2C EEPROM1, or 512 Byte to 8 kByte FRAM1
•Voltage Supervisory Chip for Reset logic and power supervision
•Remote Supervisory Circuit3
•free Chip Select signals for easy connection of peripheral devices
•requires single 5 V / <220 mA supply voltage
•RS-232 transceiver for two serial interfaces
•optional UART for second asynchronous serial interface
•support for modem signals CTS, RTS, DTR, and DSR over the
second serial interface (only when populated with external UART)
1: Dual on-chip CAN is only available with Infineon‘s C167CS microcontroller.
2: Please contact PHYTEC for more information about additional modul configurations.
3: This feature is under development and not available yet.

phyCORE-167CR/167CS
6PHYTEC Meßtechnik GmbH 2002 L-527e_8
1.1 Block Diagram
Figure 1: Block Diagram phyCORE-167CR/167CS
1.2 View of the phyCORE-167CR/167CS
Figure 2: View of the phyCORE-167CR/167CS
R e s e t
Di
g
ital I / O Ports
I N F I N E O N
C 1 6 7 C R P1
p
h
y
C
O
R
E
-
C
o
n
n
e
c
t
o
r
R S - 2 3 2
A d d r
F L A S H
256KB - 2MB R A M
256KB-1MB
P0 D a t a
R S - 2 3 2
C A N
RxD1 / TxD1
RxD0 / TxD0
CAN0H /CAN0L
I2C Bus
U A R T
R T C
RxD0
TxD0
RxD1
TxD1
Reset
R e m o t e1
S u p e r v i s o r
E E P R O M /
F R A M
C 1 6 7 C S
Jumper
opt.
CAN0
CAN1 CAN1H /CAN1L
C A N
Transceiver
Transceiver
Transceiver
Transceiver
1: This feature is under development and is not available yet.
o
p
t.

Pin Description
PHYTEC Meßtechnik GmbH 2002 L-527e_8 7
2Pin Description
Please note that all module connections are not to exceed their
expressed maximum voltage or current. Maximum signal input values
are indicated in the corresponding controller manuals/data sheets. As
damage from improper connections varies according to use and
application, it is the user’s responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
As Figure 3 indicates, all controller signals extend to surface mount
technology (SMT) connectors (0.635 mm) lining two sides of the
module (referred to as phyCORE-connector). This allows the
phyCORE-167CR/167CS to be plugged into any target application
like a “big chip”.
A new numbering scheme for the pins on the phyCORE-connector
has been introduced with the phyCORE specifications. This enables
quick and easy identification of desired pins and minimizes errors
when matching pins on the phyCORE module with the
phyCORE-connector on the appropriate PHYTEC Development
Board or in user target circuitry.
The numbering scheme for the phyCORE-connector is based on a two
dimensional matrix in which column positions are identified by a
letter and row position by a number. Pin 1A, for example, is always
located in the upper left hand corner of the matrix. The pin numbering
values increase moving down on the board. Lettering of the pin
connector rows progresses alphabetically from left to right
(refer to Figure 3).

phyCORE-167CR/167CS
8PHYTEC Meßtechnik GmbH 2002 L-527e_8
The numbered matrix can be aligned with the
phyCORE-167CR/167CS (viewed from above; phyCORE-connector
pointing down) or with the socket of the corresponding phyCORE
Development Board/user target circuitry. The upper left-hand corner
of the numbered matrix (pin 1A) is thus covered with the corner of the
phyCORE-167CR/167CS marked with a white triangle. The
numbering scheme is always in relation to the PCB as viewed from
above, even if all connector contacts extend to the bottom of the
module.
The numbering scheme is thus consistent for both the module’s
phyCORE-connector as well as mating connectors on the phyCORE
Development Board or target hardware, thereby considerably
reducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix
previously described, the phyCORE-connector is usually assigned a
single designator for its position (X1 for example). In this manner the
phyCORE-connector comprises a single, logical unit regardless of the
fact that it could consist of more than one physical socketed
connector. The location of row 1 on the board is marked by a white
triangle on the PCB to allow easy identification.

Pin Description
PHYTEC Meßtechnik GmbH 2002 L-527e_8 9
The following figure (Figure 3) illustrates the numbered matrix
system. It shows a phyCORE-167CR/167CS with SMT
phyCORE-connectors on its underside (defined as dotted lines)
mounted on a Development Board. In order to facilitate understanding
of the pin assignment scheme, the diagram presents a crossview of the
phyCORE module showing these phyCORE-connectors mounted on
the underside of the module’s PCB.
Figure 3 Pinout of the phyCORE-connector (Top View, with Cross Section
Insert)
Many of the controller port pins accessible at the connectors along the
edges of the board have been assigned alternate functions that can be
activated via software.
A B C D
11

phyCORE-167CR/167CS
10 PHYTEC Meßtechnik GmbH 2002 L-527e_8
Table 1 provides an overview of the pinout of the
phyCORE-connector , as well as descriptions of possible alternative
functions. Please refer to the Infineon C167Cx User’s Manual/Data
Sheet for details on the functions and features of controller signals
and port pins.
Pin Number Signal I/O Description
Pin Row X1A
1A CLKIN I Optional external clock generator
2A, 7A, 12A, 17A,
22A, 27A, 32A,
37A, 42A, 47A
GND - Ground 0 V
3A P2.9 I/O CAPCOM1: CC9 Capture Input/Compare Output
Fast external Interrupt 1 Input (I)
4A /NMI I Non-masked interrupt input
5A P6.4/ /CS4 O Chip Select #4
6A ALE O Address latch enable
8A WRL O /WRL signal of the microcontroller
9A, 10A, 11A,
13A, 14A, 15A,
16A, 18A,
24A, 25A,
26A, 28A
A1, A2, A4,
A7, A9, A10,
A12, A15,
A17, A18,
A20, A23
O Address line of the microcontroller
19A, 20A, 21A,
23A, 29A, 30A,
31A, 33A
D1, D2, D4,
D7, D9, D10,
D12, D15
I/O Data line of the microcontroller
34A /RDY I Microcontroller READY signal input
35A NC - Not connected.
These contacts should remain unconnected on the
target hardware side.
36A P6.6/ /HLDA I/O Acknowledge output (master mode)/ input
(slave mode)
38A, 39A P7.1, P7.3 O POUT1 PWM Channel 1
POUT3 PWM Channel 3
40A, 41A P7.4, P7.6 I/O CAPCOM2:CC28 Capture Input/Compare Output
CAPCOM2:CC30 Capture Input/Compare Output
43A P3.9 I/O SSC Master transmit/Slave receive
44A P3.0 I CAPCOM1 Timer T0 Counter input
45A P3.1 O GPT2 Timer T6 Latch output
46A P3.3 O GPT1 Timer T3 Latch output
48A P3.6 I GPT1 Timer T3 Counter input
49A P6.0/ /CS0 O Chip Select #0
50A P6.1/ /CS1 O Chip Select #1