Phytec phyCORE-SC520 User manual

A product of a PHYTEC Technology Holding company
phyCORE-SC520
Hardware Manual
Edition June 2002

phyCORE-SC520
PHYTEC Meßtechnik GmbH 2002 L-554e_2
In this manual are descriptions for copyrighted products that are not explicitly
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does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Meßtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Meßtechnik GmbH neither gives any
guarantee nor accepts any liability whatsoever for consequential damages resulting
from the use of this manual or its associated product. PHYTEC Meßtechnik
GmbH reserves the right to alter the information contained herein without prior
notification and accepts no responsibility for any damages which might result.
Additionally, PHYTEC Meßtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Meßtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
Copyright 2002 PHYTEC Meßtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or in
part - are reserved. No reproduction may occur without the express written consent
from PHYTEC Meßtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone] [e-mail] 1 [phone] [e-mail]
Technical
Support: [phone] [email protected] 1 [phone] [e-mail]
Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
2nd Edition June 2002

Contents
PHYTEC Meßtechnik GmbH 2002 L-554e_2
Preface...........................................................................................................1
1 Introduction .........................................................................................3
1.1 Block Diagram..............................................................................7
1.2 View of the phyCORE-SC520......................................................8
2 Pin Description.....................................................................................9
2.1 Supply Voltage ...........................................................................20
2.2 AMDebug Interface....................................................................22
2.3 Serial Interfaces..........................................................................23
2.4 Infrared Interface........................................................................25
2.5 Parallel Interface.........................................................................26
2.6 Floppy Interface..........................................................................27
2.7 IDE Interface ..............................................................................28
2.8 Keyboard and Mouse Interfaces.................................................28
2.9 Ethernet Connector.....................................................................29
2.10 SSI Interface ...............................................................................29
2.11 ISA Bus.......................................................................................30
2.12 PCI Bus.......................................................................................32
3 System Configuration........................................................................33
3.1 Memory Mapping .......................................................................33
3.2 Interrupts.....................................................................................34
3.3 DMA Channels...........................................................................36
3.4 Chip Select Signals.....................................................................37
3.5 Programmable Address Region Register....................................38
3.6 SIO Initialization ........................................................................39
4 System-BIOS......................................................................................41
4.1 Various Boot Modes...................................................................41
4.2 CMOS Setup...............................................................................42
4.3 Flash Disk...................................................................................43
4.4 Manufacturing Mode..................................................................44
4.4.1 Access to Drives Configured in the BIOS
(i.e. Flash Disk) .............................................................44
4.4.2 Direct Access to the Flash Device.................................47
5 Technical Specifications....................................................................53

phyCORE-SC520
PHYTEC Meßtechnik GmbH 2002 L-554e_2
6 Hints for Handling the phyCORE-SC520.......................................55
7 Connection Examples for External Periphery ...............................57
7.1 Connecting a Serial Device to the SSI Bus................................57
7.1.1 3-Wire Connection........................................................57
7.1.2 4-Wire Connection........................................................57
7.2 Connecting a Hard-Drive ...........................................................58
7.3 Connecting a Floppy-Drive........................................................58
7.4 Connecting a Keyboard..............................................................59
7.5 Connecting a Mouse...................................................................59
7.6 Connecting the Serial Interfaces.................................................59
7.7 Connecting the Parallel Interface ...............................................60
7.8 Connecting an Infrared Transmit/Receive Unit .........................61
7.8.1 Connection at COM4 Pins.............................................61
7.8.2 Connecting at SIO GP Pins...........................................61
7.9 Ethernet Connection...................................................................62
7.10 Connecting the Boot Jumper......................................................62
Index............................................................................................................63

Contents
PHYTEC Meßtechnik GmbH 2002 L-554e_2
Index of Figures
Figure 1: Block Diagram phyCORE-SC520................................................7
Figure 2: View of the phyCORE-SC520......................................................8
Figure 3: Pinout of the phyCORE-Connector
(Top View, with Cross Section Insert).......................................11
Figure 4: Pinout of the AMDebug-Connector X2......................................22
Figure 5: System BIOS Setup-Utility Window..........................................42
Figure 6: Physical Dimensions...................................................................53
Figure 7: SSI Bus, 3-Wire Connection (Example).....................................57
Figure 8: SSI Bus, 4-Wire Connection (Example).....................................57
Figure 9: Connecting a Hard-Drive (Example)..........................................58
Figure 10: Connecting a Floppy-Drive (Example).......................................58
Figure 11: Connecting a Keyboard (Example).............................................59
Figure 12: Connecting a Mouse (Example) .................................................59
Figure 13: Connecting the Serial Interfaces COMx (Example)...................59
Figure 14: Connecting the Parallel Interface (Example)..............................60
Figure 15: Connecting an Infrared Module (Example with COM4 Pins)....61
Figure 16: Connecting an Infrared Module (Example with SIO GP Pins) ..61
Figure 17: Ethernet Connection (Example) .................................................62
Figure 18: Connecting the Boot Jumper (Example).....................................62

phyCORE-SC520
PHYTEC Meßtechnik GmbH 2002 L-554e_2
Index of Tables
Table 1: Pinout of the phyCORE-Connector X1......................................19
Table 2: Supply Voltage Connections......................................................20
Table 3: Current Draw..............................................................................21
Table 4: Pinout of the AMDebug-Connector X2 .....................................22
Table 5: Pinout of the Serial Interface COM1 (V24)...............................23
Table 6: Pinout of the Serial Interface COM2 (V24)...............................24
Table 7: Pinout of the Serial Interface COM3 (5 V TTL)........................24
Table 8: Pinout of the Serial Interface COM4 (5 V TTL)........................24
Table 9: Pinout IR Interface on COM4 Pins ............................................25
Table 10: Pinout IR Interface on I/O Pins..................................................25
Table 11: Pinout of the Parallel Interface...................................................26
Table 12: Pinout of the Floppy Interface....................................................27
Table 13: IDE-Specific Signals..................................................................28
Table 14: Keyboard Interface.....................................................................28
Table 15: Mouse Interface..........................................................................28
Table 16: Ethernet Connector.....................................................................29
Table 17: Pinout of the SSI Interface .........................................................29
Table 18: PCI Bus.......................................................................................32
Table 19: Memory Mapping.......................................................................33
Table 20: Interrupt Configuration...............................................................34
Table 21: Interrupts on the Molex Connector X1.......................................35
Table 22: DMA Connections......................................................................36
Table 23: Chip Select Configuration..........................................................37
Table 24: PAR Register Configuration ......................................................38
Table 25: Super I/O Interrupt and DMA Configuration.............................39

Preface
PHYTEC Meßtechnik GmbH 2002 L-554e_2 1
Preface
This phyCORE-SC520 Hardware Manual describes the board’s design
and functions. Precise specifications for the “Elan SC520” controller
series can be found in the enclosed microcontroller Data Sheet/User's
Manual from AMD as well as the documentation for peripheral
components: “FDC37B787, Enhanced Super I/O Controller with
ACPI Support, Real-Time Clock and Consumer IR” from SMSC and
“RTL8139C, Single Chip Fast Ethernet Controller with Power
Management” from Realtek. If software is included also refer to
additional documentation for this software.
In this hardware manual and in the attached schematics, low active
signals are denoted by a "/" in front of the signal name (i.e.: /RD). A
"0" indicates a logic-zero or low-level signal, while a "1" represents a
logic-one or high-level signal.
Declaration of Electro Magnetic Conformance of the
PHYTEC phyCORE-SC520
PHYTEC Single Board Computers (henceforth “products”) are
designed for installation in electrical appliances or as dedicated
Evaluation Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Caution:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD-dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product's pin header rows are longer than 3 m.

phyCORE-SC520
2PHYTEC Meßtechnik GmbH 2002 L-554e_2
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, are subject
to renewed establishment of conformity to, and certification of,
Electro Magnetic Directives. Users should ensure conformance
following any modifications to the products as well as implementation
of the products into target systems.
The phyCORE-SC520 is one of a series of PHYTEC Single Board
Computers that can be populated with different controllers and,
hence, offers various functions and configurations.
PHYTEC supports all common 8- and 16-bit as well as specific 32-bit
controllers in two ways:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional micro-, mini- and phyCORE
OEM modules, which can be embedded directly into the user’s
peripheral hardware, design.
PHYTEC's microcontroller modules allow engineers to shorten
development horizons, reduce design costs and speed project concepts
from design to market.

Introduction
PHYTEC Meßtechnik GmbH 2002 L-554e_2 3
1Introduction
The phyCORE-SC520 belongs to PHYTEC’s phyCORE Single Board
Computer module family. The phyCORE SBCs represent the
continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the
phyCORE boards integrate all core elements of a microcontroller
system on a subminiature board and are designed in a manner that
ensures their easy expansion and embedding in peripheral hardware
developments.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments, the phyCORE board design features an increased pin
package. The increased pin package allows dedication of
approximately 20 % of all pin header connectors on the phyCORE
boards to Ground. This improves EMI and EMC characteristics and
makes it easier to design complex applications meeting EMI and
EMC guidelines using phyCORE boards even in high noise
environments.
phyCORE boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD components and laser-drilled
Microvias are used on the boards, providing phyCORE users with
access to this cutting edge miniaturization technology for integration
into their own design.
We at PHYTEC consider it our responsibility, as a reliable partner
and ISO 9001 certified supplier, to enable the integration of our insert
ready microcontroller modules into your OEM production. This is an
important condition for the success of our product.

phyCORE-SC520
4PHYTEC Meßtechnik GmbH 2002 L-554e_2
The phyCORE-SC520 is a subminiature (60 x 53 mm) insert-ready
Single Board Computer populated with the Elan SC520 micro-
controller from AMD.
Its universal design enables its insertion in a wide range of embedded
applications. All controller signals and ports extend from the
controller to high-density pitch (0.635 mm) connectors aligning two
sides of the board, allowing it to be plugged like a “big chip” into a
target application.
Precise specifications for the controller populating the board can be
found in the applicable controller User’s Manual or Data Sheet. No
description of compatible microcontroller derivative functions is
included, as such functions are not relevant for the basic functioning
of the phyCORE-SC520.

Introduction
PHYTEC Meßtechnik GmbH 2002 L-554e_2 5
The phyCORE-SC520 offers the following features:
•subminiature Single Board Computer (60 x 53 mm) achieved
through modern SMD technology
•586-compatible CPU with a Floating Point Unit and 16 kByte
write back cache
•133 MHz clock frequency (core)
•Low Voltage Operation (VCCcore = 2.5 V)
•Integrated PCI controller for 33 MHz 32-bit PCI Bus
(Version 2.2), supports up to 5 external PCI masters
•SDRAM controller for up to 256 MB, 66 MHz clock
•Expanded JTAG port (AMDebug) with the possibility of
debugging and executing individual steps during operation.
•General Purpose (GP) Bus with programmable timings
•ROM / FLASH controller for 8-, 16-, 32-bit data bus width
•PC/AT compatible periphery units: 22 prioritizable interrupt
channels (15 external inputs), expandable DMA controller,
2 modem capable UARTs.
•Real-Time Clock with 114 Byte CMOS-RAM with battery
buffering
•Additional integrated periphery: 3 cascaded and freely
programmable 16-bit timers, watchdog and software timers,
Synchronous Serial Interface
•32 programmable I/O-Pins
•Support of Windows CE, pSOS, QNX, RTXC, and VxWorks
operating systems
•Industry standard BIOS support
•Improved interference protection via multilayer technology as well
as reduced radiation interference due to improved ground
connections.
•All ports as well as data and address lines extend to two 160-pole
high density (0.635 mm) Molex connectors located on the
underside of the Development Board
•Can be inserted into target circuitry like a "big chip"

phyCORE-SC520
6PHYTEC Meßtechnik GmbH 2002 L-554e_2
•On-board Flash programming
•No separate programming voltage for use with 3.3 V Flash devices
•16 MB – 64 MB DRAM on-board
•1 MB (up to 4 MB) Flash on-board
•128 Byte to 2 kByte serial EEPROM
•Voltage Supervisor Chip for Reset Logic
•Battery monitoring
•8 Chip Select signals extending to Molex connectors
•2 DMA channels extending to Molex connectors
•19 I/Os extending to Molex connectors
•9 IRQ inputs extending to Molex connectors
•PC/AT compatible Programmable Interval Timer (PIT) for system
loud speaker
•Supply voltages: 5 V, 3.3 V, 2.5 V
•Populated with Super Input Output (SIO) device FDC37B787
•ISA Plug and Play compatible register chain
•Multi faceted power management
•8042 keyboard controller
•Real-Time Clock
•2.88 MB Floppy Disc Controller
•2 modem capable UARTs
•Infrared interface supporting the following formats: IrDA 1.0,
Consumer IR< HP-SIR, ASK-IR
•Parallel port
•Populated with Ethernet controller RTL8139
•10 MB/s and 100 MB/s operation
•PCI version 2.2 compatible
•Supports ACPI and PCI power management
•PC99 standard compatible
•Supports Wake-on-LAN and remote wake-up (Magic Packet,
LinkChg and Microsoft wake-up frame)
•External serial EEPROM for storing the configuration and
identification data

Introduction
PHYTEC Meßtechnik GmbH 2002 L-554e_2 7
1.1 Block Diagram
Figure 1: Block Diagram phyCORE-SC520
Super
Input
Output
Controller
Flo
ppy
Parallel Port
COM3
COM4
Ke
y
board
Mouse
IrDa
GP Adressbus
GP Data Bus
GP Control BusElan SC520
PCI-Bus
PCI
Ethernet
Controller
Ethernet Coil
Connector
COM1
COM2
SS
I
RS-232 Transceiver
RS-232 Transceiver
Serial EEPROM
AMDebu
g
3,3V
area
5 V
area

phyCORE-SC520
8PHYTEC Meßtechnik GmbH 2002 L-554e_2
1.2 View of the phyCORE-SC520
Figure 2: View of the phyCORE-SC520
U2
SIO
U1
Elan SC520
U4
SDRAM
U5
SDRAM
U16
U15
U9
U17
Ethernet

Pin Description
PHYTEC Meßtechnik GmbH 2002 L-554e_2 9
2Pin Description
Please note that all module connections are not to exceed their
expressed maximum voltage or current. Maximum signal input values
are indicated in the corresponding controller manuals/data sheets. As
damage from improper connections varies according to use and
application, it is the user’s responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
As Figure 3 indicates, all controller signals extend to surface mount
technology (SMT) connectors (0.635 mm) lining two sides of the
module (referred to as phyCORE-connector). This allows the
phyCORE-SC520 to be plugged into any target application like a
“big chip”.
A new numbering scheme for the pins on the phyCORE-connector
has been introduced with the phyCORE specifications. This enables
quick and easy identification of desired pins and minimizes errors
when matching pins on the phyCORE-module with the phyCORE-
connector on the appropriate PHYTEC Development Board or in user
target circuitry.
The numbering scheme for the phyCORE-connector is based on a two
dimensional matrix in which column positions are identified by a
letter and row position by a number. Pin 1A, for example, is always
located in the upper left hand corner of the matrix. The pin
numbering values increase moving down on the board. Lettering of
the pin connector rows progresses alphabetically from left to right
(refer to Figure 3).

phyCORE-SC520
10 PHYTEC Meßtechnik GmbH 2002 L-554e_2
The numbered matrix can be aligned with the phyCORE-SC520
(viewed from above; phyCORE-connector pointing down) or with the
socket of the corresponding phyCORE Development Board/user
target circuitry. The upper left-hand corner of the numbered matrix
(pin 1A) is thus covered with the corner of the phyCORE-SC520
marked with a white triangle. The numbering scheme is always in
relation to the PCB as viewed from above, even if all connector
contacts extend to the bottom of the module.
The numbering scheme is thus consistent for both the module’s
phyCORE-connector as well as mating connectors on the phyCORE
Development Board or target hardware, thereby considerably
reducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix
previously described, the phyCORE-connector is usually assigned a
single designator for its position (X1 for example). In this manner the
phyCORE-connector comprises a single, logical unit regardless of the
fact that it could consist of more than one physical socked connector.
The location of row 1 on the board is marked by a white triangle on
the PCB to allow easy identification.
The following figure (Figure 3) illustrates the numbered matrix
system. It shows a phyCORE-SC520 with SMT phyCORE-
connectors on its underside (defined as dotted lines) mounted on a
Development Board.

Pin Description
PHYTEC Meßtechnik GmbH 2002 L-554e_2 11
In order to facilitate understanding of the pin assignment scheme, the
diagram presents a crossview of the phyCORE module showing these
phyCORE-connectors mounted on the underside of the module’s
PCB.
Figure 3: Pinout of the phyCORE-Connector (Top View, with Cross Section
Insert)
Many of the controller port pins accessible at the connectors along the
edges of the board have been assigned alternate functions that can be
activated via software.
A B C D
11

phyCORE-SC520
12 PHYTEC Meßtechnik GmbH 2002 L-554e_2
Pin # Signal I/O Description
Row X1A
1A CLKIN I Optional external clock generator
2A, 7A, 12A,
17A, 22A, 27A,
32A, 37A, 42A,
47A, 52A, 57A,
62A, 67A, 72A,
77A
GND - Ground
3A GPIRQ1 I GP Bus Interrupt Request 1 or PIO 22, Interrupt input 1 or
programmable in-/output 22
4A GPIRQ5 I GP Bus Interrupt Request 5 or PIO 18, Interrupt input 5 or
programmable in-/output 18
5A /GPCS1 O Chip Select 1, can be used for external Flash
6A GPALE O GP Bus Address Latch Enable, displays valid addresses
on the address bus
8A /GPIOWR O GP Bus I/O Write, shows write access to I/O device
9A GPA1 O General-Purpose Address Bus, Address bus for memory,
I/O and external Flash devices, GP address line 1
10A GPA2 O GP address line 2
11A GPA4 O GP address line 4
13A GPA7 O GP address line 7
14A GPA9 O GP address line 9
15A GPA10 O GP address line 10
16A GPA12 O GP address line 12
18A GPA15 O GP address line 15
19A GPD1 I/O General Purpose Data Bus, Data transfer during memory
or I/O read or write accesses, GP data line 1
20A GPD2 I/O GP data line 2
21A GPD4 I/O GP data line 4
23A GPD7 I/O GP data line 7
24A GPA17 O GP address line 17
25A GPA18 O GP address line 18
26A GPA20 O GP address line 20
28A GPA23 O GP address line 23
29A GPD9 I/O GP data line 9
30A GPD10 I/O GP data line 10
31A GPD12 I/O GP data line 12
33A GPD15 I/O GP data line 15
34A GPA25 O GP address line 25
35A GPRDY I GP Bus Ready, with a „Low“ GP enters Bus Wait States
36A /GPMEMRD O GP Bus Memory Read, write access to selected memory
components
38A GPTC O GP Bus Terminal Count, DMA Transfer counter is zero,
last transfer cycle
39A /GPIOCS16 I GP Bus I/O Chip Select 16, I/O component awaits 16-bit
access
40A /GPDBUFOE O GP Bus Data Buffer Output Enable, shows access to GP
Bus

Pin Description
PHYTEC Meßtechnik GmbH 2002 L-554e_2 13
Pin # Signal I/O Description
Row X1A
41A - NC, should remain disconnected
43A PCI-AD1 I/O PCI Address Data Bus, time multiplexed address and data
bus, PCI address-/dataline 1
44A PCI-AD3 I/O PCI address/data line 3
45A PCI-AD4 I/O PCI address/data line 4
46A PCI-AD6 I/O PCI address/data line 6
48A PCI-AD9 I/O PCI address/data line 9
49A PCI-AD11 I/O PCI address/data line 11
50A PCI-AD12 I/O PCI address/data line 12
51A PCI-AD14 I/O PCI address/data line 14
53A PCI-AD17 I/O PCI address/data line 17
54A PCI-AD19 I/O PCI address/data line 19
55A PCI-AD20 I/O PCI address/data line 20
56A PCI-AD22 I/O PCI address/data line 22
58A PCI-AD25 I/O PCI address/data line 25
59A PCI-AD27 I/O PCI address/data line 27
60A PCI-AD28 I/O PCI address/data line 28
61A PCI-AD30 I/O PCI address/data line 30
63A /PCI-FRAME I/O Frame, Initiator shows start and duration of the transaction
on the bus
64A /PCI-CBE1 I/O Command or Byte-Enable Bus 1
65A /PCI-CBE2 I/O Command or Byte-Enable Bus 2
66A PCI-PAR I/O Parity, is set by the initiator
68A /PCI-DEVSEL I/O Device Select, set by target, if it has recognized the
address
69A /PCI-REQ1 I Bus Request, Master 1 wants bus access
70A /PCI-GNT1 O Bus Grant 1, bus access for Master 1 granted
71A /PCI-REQ3 I Bus Request, Master 3 wants bus access
73A /PCI-GNT4 O Bus Grant 4, bus access for Master 4 granted
74A /PCI-INTA I Interrupt Request, PCI Interrupt A
75A /PCI-INTC I Interrupt Request, PCI Interrupt C
76A PCI-CLK0 O PCI Clock line 0
78A PCI-CLK2 O PCI Clock line 2
79A PCI-CLK3 O PCI Clock line3
80A /PCI-PERR B Parity Error, a parity error has occurred on the bus

phyCORE-SC520
14 PHYTEC Meßtechnik GmbH 2002 L-554e_2
Pin # Signal I/O Description
Row X1B
1B OSC14M O 14.318 MHz clock
2B GPIRQ0 I GP Bus Interrupt Request 0 or PIO 23, Interrupt input 0 or
programmable in-/output 23
3B GPIRQ2 I GP Bus Interrupt Request 2 or PIO 21, Interrupt input 2 or
programmable in-/output 21
4B, 9B,
14B, 19B,
24B, 29B,
34B, 39B,
44B, 49B,
54B, 59B,
64B, 69B,
74B, 79B
GND - Ground
5B /GPCS2 O Chip Select, can be used for external Flash
6B /GPCS4 O GP Chip Select, can address memory or I/O devices or be
configured as timer input 1
7B /GPIORD O GP Bus I/O Read, shows read access on I/O device
8B GPA0 O GP address line 0
10B GPA3 O GP address line 3
11B GPA5 O GP address line 5
12B GPA6 O GP address line 6
13B GPA8 O GP address line 8
15B GPA11 O GP address line 11
16B GPA13 O GP address line 13
17B GPA14 O GP address line 14
18B GPD0 I/O GP data line 0
20B GPD3 I/O GP data line 3
21B GPD5 I/O GP data line 5
22B GPD6 I/O GP data line 6
23B GPA16 A GP address line 16
25B GPA19 O GP address line 19
26B GPA21 O GP address line 21
27B GPA22 O GP address line 22
28B GPD8 I/O GP data line 8
30B GPD11 I/O GP data line 11
31B GPD13 I/O GP data line 13
32B GPD14 I/O GP data line 14
33B GPA24 O GP address line 24
35B /GPBHE O GP Bus Byte High Enable, is active if data is located in
the upper 8-bits of the bus
36B /GPMEMWR O GP Bus Memory Write, shows a write access to memory
37B GPAEN O GP Bus Address Enable, shows that the current bus access
is a memory access within a DMA cycle
38B /GPMEMCS16 I GP Bus Memory Chip Select 16, memory device awaits
16-bit access
40B - NC, should remain disconnected
41B PCI-AD0 I/O PCI address/data line 0