Quectel EG9 Series Guide

EG9x
Reference Design
LTE Module Series
Rev. EG9x_Reference_Design_Rev.A
Date: 2018-02-09
Status: Released
www.quectel.com

LTE Module Series
EG9x Reference Design
EC20_R2.1_Reference_Design 1 / 4
Our aim is to provide customers with timely and comprehensive service. For any
assistance, please contact our company headquarters:
Quectel Wireless Solutions Co., Ltd.
7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, China
Tel: [phone]
Email: [email protected]om
Or our local office. For more information, please visit:
http://quectel.com/support/sales.htm
For technical support, or to report documentation errors, please visit:
http://quectel.com/support/technical.htm
Or Email to: [e-mail]
GENERAL NOTES
QUECTEL OFFERS THE INFORMATION AS A SERVICE TO ITS CUSTOMERS. THE INFORMATION
PROVIDED IS BASED UPON CUSTOMERS’ REQUIREMENTS. QUECTEL MAKES EVERY EFFORT
TO ENSURE THE QUALITY OF THE INFORMATION IT MAKES AVAILABLE. QUECTEL DOES NOT
MAKE ANY WARRANTY AS TO THE INFORMATION CONTAINED HEREIN, AND DOES NOT ACCEPT
ANY LIABILITY FOR ANY INJURY, LOSS OR DAMAGE OF ANY KIND INCURRED BY USE OF OR
RELIANCE UPON THE INFORMATION. ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO
CHANGE WITHOUT PRIOR NOTICE.
COPYRIGHT
THE INFORMATION CONTAINED HERE IS PROPRIETARY TECHNICAL INFORMATION OF
QUECTEL WIRELESS SOLUTIONS CO., LTD. TRANSMITTING, REPRODUCTION, DISSEMINATION
AND EDITING OF THIS DOCUMENT AS WELL AS UTILIZATION OF THE CONTENT ARE
FORBIDDEN WITHOUT PERMISSION. OFFENDERS WILL BE HELD LIABLE FOR PAYMENT OF
DAMAGES. ALL RIGHTS ARE RESERVED IN THE EVENT OF A PATENT GRANT OR
REGISTRATION OF A UTILITY MODEL OR DESIGN.
Copyright © Quectel Wireless Solutions Co., Ltd. 2018. All rights reserved.

LTE Module Series
EG9x Reference Design
EC20_R2.1_Reference_Design 2 / 4
About the Document
History
Revision
Date
Author
Description
A
2018-02-09
Felix YIN
Initial

LTE Module Series
EG9x Reference Design
EC20_R2.1_Reference_Design 3 / 4
Contents
About the Document...................................................................................................................................2
Contents.......................................................................................................................................................3
1Reference Design.................................................................................................................................4
1.1. Introduction................................................................................................................................4
1.2. Schematics................................................................................................................................4

LTE Module Series
EG9x Reference Design
EG9x_Reference_Design 4 / 4
1Reference Design
1.1. Introduction
This document provides the reference design for Quectel EG9x modules, which contain EG91 and EG95
modules.
1.2. Schematics
The schematics illustrated in the following pages are provided for your reference only.

Quectel Wireless Solutions
Yeoman CHEN
CHECKED BY
Felix YIN
DRAWN BY
EG9x
2018-02-09
TITLEPROJECT
A
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
SIZE VER
101 DATE
A2
1. Keep all RESERVED and unused pins unconnected.
Notes:
Reference Design
2. It is recommended to reserve the test points for upgrading the firmware over USB interface and minimizing stub length of USB test signals.
Module Interface
Close to module
3. EG9x module provides a digital clock output (CLK_OUT) for an external audio codec, please refer to EG91 and EG95 Hardware Designs for further details.
Notes2
Model
EG9x-E
Installed Not installed
4. SMD difference between EG9x-E and EG9x-NA is shown as below:
R0105, R0107
R0106
EG9x-NA
R0105, R0107
R0106
EG9x module
EG9x module
C0101
100nF
1RESERVED
2RESERVED
3GND
4PCM_CLK
5PCM_SYNC
6PCM_DIN
7PCM_DOUT
8USB_VBUS
9USB_DP
10 USB_DM
11 RESERVED
12 RESERVED
13 RESERVED
14 RESERVED
15 PWRKEY
16 RESERVED
17 RESET_N
18 RESERVED
19 AP_READY 20 STATUS 21 NETLIGHT 22 DBG_RXD 23 DBG_TXD 24 RESERVED 25 CLK_OUT 26 SPI_CLK 27 SPI_MOSI 28 SPI_MISO 29 VDD_EXT 30 DTR 31 GND
32
VBAT_BB
33
VBAT_BB
34
RXD
35
TXD
36
CTS
37
RTS
38
DCD
39
RI
40
I2C_SCL
41
I2C_SDA
42
USIM1_PRESENCE
43
USIM1_VDD
44
USIM1_RST
45
USIM1_DATA
46
USIM1_CLK
47
USIM_GND
48
GND
49
ANT_DIV
50
GND
51
RESERVED
52
VBAT_RF
53
VBAT_RF
54
GND
55
GND
56
RESERVED
57
RESERVED
58
GND
59
GND
60
ANT_MAIN
61
GND
62
GND
U0101-A
63 RESERVED
64 RESERVED
65 RESERVED
66 RESERVED
67 GND
68 GND
69 GND
70 GND
71 GND
72 GND
73 GND
74 GND
75 USB_BOOT
76 RESERVED
77 RESERVED
78 RESERVED
79 GND
80 GND
81 GND
82 GND 83
USIM2_PRESENCE
84
USIM2_CLK
85
USIM2_RST
86
USIM2_DATA
87
USIM2_VDD
88
RESERVED
89
GND
90
GND
91
GND
92
RESERVED
93
RESERVED
94
RESERVED
95
RESERVED
96
RESERVED
97
RESERVED
98
RESERVED
99
RESERVED
100
GND
101
GND
102
GND
103
GND
104
GND
106 GND
105 GND
U0101-B
R0101 0R
R0103 NM_0R
R0102 0R
R0104 NM_0R
R0105 NM_0R
R0106 0R
R0107 NM_0R
[2,10]USB_VBUS
[2,10] PWRKEY
[2] RESET_N
[1,3,10]
VBAT
[9]ANT_MAIN
[8]
USIM1_CLK
[8]
USIM1_DATA
[8]
USIM1_RST
[8]
USIM1_PRESENCE
[8]
USIM_GND
USIM1_VDD
VDD_EXT
[4]RI_MODULE
[4]DCD_MODULE
[4]
RTS_MODULE
[4]CTS_MODULE
[4]TXD_MODULE
[4]
RXD_MODULE
[4] DTR_MODULE
[10] STATUS
[10] NETLIGHT
[5,6] PCM_CLK
[5,6] PCM_SYNC
[5,6] PCM_IN
[5,6] PCM_OUT
[5,6]
I2C_SDA
[5,6]
I2C_SCL
[2] AP_READY
CLK_OUT
[1,3,10]
VBAT
[10] DBG_RXD [10] DBG_TXD
[10] SPI_CLK
[10] SPI_MOSI
[10] SPI_MISO
[2] USB_DP
[2] USB_DM
[10] USB_DP_TEST
[10] USB_DM_TEST
[8]
USIM2_RST
[8]
USIM2_CLK
[8]
USIM2_PRESENCE
[8]
USIM2_DATA
USIM2_VDD
[10] USB_BOOT
[1,9]
ANT_DIV
[9]
ANT_GPS
[1,9]ANT_DIV

Yeoman CHEN
CHECKED BY
DRAWN BY
Felix YIN
Quectel Wireless Solutions
A
EG9x
TITLE
PROJECT
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
SIZE VER
102 DATE 2018-02-09
A2
Notes:
1. U0201 represents customer's MCU.
2. EG9x can only work as a USB device and supports FS/HS modes. To communicate with USB interface, MCU needs to support USB host or OTG function.
VBUS_CONTROL is active high.
It is used to reset the module.It is used to turn on or off the module.
MCU Interface
The VBUS pins of MCU and EG9x should be provided by 5V power system for USB detection, and VBUS_CONTROL is used to turn on and off VBUS power supply.
3. AP_READY is used to detect the MCU's sleep state. For more details about AP_READY, please refer to EG91 and EG95 Hardware Designs
AP_READY High Level Detection AP_READY Low Level Detection
4. Transistor circuits (Q0203～Q0206) are used for level translation.
The Necessary Control Circuit
Reference Design
5V power source from main board.
and AT Command manuals.
1
VDD 2
GND 3
TXD 4
RXD 5
DTR 6
RI 7
CTS 8
RTS 9
DCD
12
USB_DM 13
USB_ID 14
GPIO_01 15
GPIO_02 16
GPIO_03 17
GPIO_04
10
USB_VBUS 11
USB_DP
18
GPIO_05 19
GPIO_06 20
GPIO_07
U0201
Q0206
DTC043ZEBTL
R0203
47K
R0201
0R
Q0205
DTC043ZEBTL
Q0204
DTC043ZEBTL
R0205
4.7K
R0204
4.7K
Q0203
2SC4617TLQ
G
SD
Q0201 SI2333CDS-T1
Q0202
DTC043ZEBTL
R0202
10K
C0201
470nF
R0206
100K
C0202
1nF
VDD_MCU
[4]
RXD_MCU
[4]
TXD_MCU
[4]
DTR_MCU
[4]
RI_MCU
[1]
USB_DP
[1]
USB_DM
[1,2,10]
USB_VBUS
[2]
ON/OFF_MCU
[2]
RESET_MCU
[2]
VBUS_CONTROL
[2]
SLEEP_STATUS
VDD_EXT
[1,2]
AP_READY
[2] SLEEP_STATUS
[1]
RESET_N
[2] RESET_MCU
[1,10]
PWRKEY
[2] ON/OFF_MCU
VDD_EXT
[2] SLEEP_STATUS [1,2]
AP_READY
VDD_EXT
[4]
CTS_MCU
[4]
RTS_MCU
[4]
DCD_MCU
[3]
VBAT_EN
DC_5V [1,2,10]
USB_VBUS
[2] VBUS_CONTROL
[3]
CODEC_POWER_EN

Quectel Wireless Solutions
Felix YIN
DRAWN BY
Yeoman CHEN
CHECKED BY
PROJECT TITLE
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
SIZE VER
103
A
DATE 2018-02-09
EG9x
A2
e.g. 5V
LDO Application
It is used when the input voltage is below 7V.
VBAT = (R0302/R0303+1)*1.24 = 3.88V
Close to the module VBAT pins
Notes:
2. VBAT should be routed in star mode to VBAT_BB and VBAT_RF pins.
Power Supply Design
VBAT Design
Connect to VBAT_BB pins
Connect to VBAT_RF pins
Reference Design
1. The power supply must be able to provide sufficient current up to 2A or more.
3. The recommended operating voltage of VBAT is 3.3V～4.3V.
Notes:
DC-DC Application
It is used when the input voltage is above 7V. Use a DC-DC convertor to convert a high
e.g. DC12V IN DC-DC DC 5V OUT LDO DC 3.8V for module
input voltage to a 5V output, and then the LDOs will generate a 3.8V typical voltage for the
LDO DC 1.8V for codec
module and 1.8V & 3.3V typical voltages for codec.
LDO DC 3.3V for codec
1. The load current is recommended to be greater than 10mA.
2. The power supply must be able to provide sufficient current up to 2A or more.
VDD_1V8 = [(R0311+R0312)/R0312]*1.207 = 1.8V
VDD_3.3V = (R0305/R0306+1)*1.207 = 3.3V
Supply Power for PCM Codec
e.g. 5V
e.g. 5V
Notes:
Power-on Sequence: power on VDD_1V8 first, then VDD_3.3V.
Power-off Sequence: power off VDD_3.3V first, then VDD_1V8.
1. CODEC_POWER_EN must be at low level in order to ensure the normal output voltage of VDD_3.3V.
If VDD_3.3V power supply needs to be switched off, please keep CODEC_POWER_EN at high level.
2. The following power-on/off sequences should be complied with to ensure the audio codec works normally.
+
C0303
470uF
1EN
2IN
3GND
4
OUT
5ADJ
U0301
MIC29302WU
C0304
100nF
C0302
100nF
+
C0301
470uF
R0302
100K
1%
R0303
47K
1%
+
C0305
100uF
D0301
PZ3D4V2H
R0301
51K
C0306
100nF
C0307
33pF
C0308
10pF
C0310
100nF
C0311
33pF
C0312
10pF
+
C0309
100uF
R0304
330R
D0302
TVS
Q0301
DTC043ZEBTL
1IN
3EN
5
OUT 4
BP
2GND
U0302
SGM2019-ADJYN5G/TR
C0320
4.7uF
R0310
39K_1%
R0311
75K_1%
C0318
100nF
C0321
100nF
C0322
33pF
C0319
1uF
C0315
4.7uF
R0305
73.2K
1%
R0306
42.2K
1%
C0316
100nF
C0313
1uF
C0314
100nF
1IN
3EN
5
OUT 4
BP
2GND
U0303
SGM2019-ADJYN5G/TR
C0317
33pF
R0308
100K
R0309
100K
R0307
0R
Q0302
DTC043ZE
[3] DC_IN
VBAT
[1,3,10]
VBAT
[1,3,10]
VBAT
VBAT
[2] VBAT_EN
VDD_1V8
VDD_3.3V
[3] DC_IN
[3] DC_IN
[1,2,4,8,10] VDD_EXT
[2] CODEC_POWER_EN
VDD_1V8

Quectel Wireless Solutions
Yeoman CHEN
CHECKED BY
Felix YIN
DRAWN BY
A
PROJECT TITLE
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
SIZE VER
104 DATE 2018-02-09
EG9x
A2
Notes:
UART Design
UART Translation - IC Solution
UART Translation - Transistor Solution (Recommended)
1. The power supply voltage of VCCA should not exceed that of VCCB. For more information about TXS0108E, please refer to the datasheet from TI.
2. If a high baud rate is needed, it is highly recommended to install a 1nF capacitor (C0403/C0404) on transistor circiut.
Reference Design
3. The transistor circuit of DTR is similar to that of RTS interface, and the transistor circuit of RI and DCD is similar to that of CTS interface.
C0401
100nF
R0402
120K
R0401
10K
C0402 100nF
Q0401
2SC4617TLQ Q0402 2SC4617TLQ
R0404
4.7K
R0403
4.7K
C0403
1nF
R0405
4.7K
R0406
4.7K
C0404
1nF
Q0403
2SC4617TLQ
R0408
4.7K
R0407
4.7K
Q0404 2SC4617TLQ
R0409
4.7K
R0410
4.7K
6A5
7A6
8A7
9A8
10 OE
5A4
4A3
19
VCCB
20
B1
18
B2
14
B6
13
B7
12
B8
11
GND
3A2
2VCCA
1A1
17
B3
16
B4
15
B5
U0401
TXS0108E
C0405
1nF
C0406
1nF
VDD_EXT
VDD_EXT VDD_MCU
[1,4] TXD_MODULE
[1,4] RXD_MODULE
[1] RI_MODULE
[1] DTR_MODULE
[2,4]
TXD_MCU
[2,4]
RXD_MCU
[2]
DTR_MCU
[2]
RI_MCU
[2,4] RXD_MCU [1,4]
RXD_MODULE
VDD_EXT
VDD_EXT
[2,4] TXD_MCU [1,4] TXD_MODULE
VDD_EXTVDD_MCU
VDD_EXT
[1,4]
RTS_MODULE
[2,4] RTS_MCU
VDD_EXT VDD_MCU
[2,4] CTS_MCU [1,4]
CTS_MODULE
VDD_EXT
[2,4]
CTS_MCU
[2,4]
RTS_MCU
[1,4] CTS_MODULE
[1,4] RTS_MODULE
[1] DCD_MODULE [2]
DCD_MCU

CHECKED BY
Felix YIN
DRAWN BY
Quectel Wireless Solutions
EG9x
A
TITLE
PROJECT
OF
A
65432
1
SHEET
A
B
C
D
123456
D
C
B
SIZE VER
105 DATE 2018-02-09
A2
Reference Design
Winter CHEN
Notes:
3. EG9x module will automatically initialize the codec via I2C interface after it is turned on successfully, so all power supplies for the codec need to be powered on before that.
Audio Codec Design (ALC5616)
1. ALC5616 power-on sequence: DBVDD/I2C pull-up power/AVDD/DACREF/CPVDD -> MICVDD -> software initialization.
2. ALC5616 power-off sequence: close codec function by software -> MICVDD -> DBVDD/I2C pull-up power/AVDD/DACREF/CPVDD.
2IN1P/DMC_DAT
3IN2P
4IN2N/JD2
5
DACREF 6
AVDD
7AGND
10
LOUTR/N
11
CPN2
12
CPP2
13
CPN1
14
CPP1
15
CPVDD
16
CPVPP
18
CPVREF
19
CPVEE
20
HPO_L
21 ADCDAT1
22 DACDAT1
23 LRCK1
26
SCL
27
SDA
28 GPIO1/IRQ1
29
DBVDD
30
DCVDD
31
MICVDD
32 MICBIAS1
8
VREF2
24 BCLK1
1JD1
9
LOUTL/P
17
HPO_R
25 MCLK
33 DGND
U0501
ALC5616
C0505
4.7uF
C0504
4.7uF
C0503
100nF
R0501 0R
C0501
4.7uF
C0502
100nF
C0509
2.2uF
C0510
100nF
C0506
4.7uF
C0507
100nF
C0508
2.2uF
C0515 2.2uF
C0516 2.2uF
C0511 4.7uF R0503
0R
R0508 NM_10K
R0510
4.7K
R0509
4.7K
C0523 4.7uF
C0521 2.2uF
C0522 2.2uF
R0504 0R
R0505 0R
R0506 0R
R0507 0R
C0512
NM
C0513
NM
C0514
NM
C0524 2.2uF
C0525 2.2uF
R0516
1K
R0514
1.5K
R0513
1K
R0515
1.5K
C0526
10uF
R0502 0R
C0517 1uF
C0518 1uF
C0519 1uF
C0520 1uF
R0511 0R
R0512 0R
R0522
0R
R0523
0R
C0549
NM_33pF
C0548
NM_33pF
R0524 0R
R0525 0R
VDD_3.3V
VDD_1V8
VDD_3.3V
[1,6]
I2C_SDA
[1,6]
I2C_SCL
VDD_1V8
VDD_1V8
[1,6] PCM_OUT
[1,6] PCM_IN
[1,6] PCM_CLK
[1,6] PCM_SYNC
[5] MIC+
[5] MIC-
[6,7]
SPK_P
[6,7]
SPK_N
MICBIAS
[6,7] MIC_P
[6,7] MIC_N
MICBIAS
[5]
MIC+
[5]
MIC-
VDD_1V8
[6,7]
SPK_R
[6,7]
SPK_L