Sharp ER-A440 User manual

SERVICE MANUAL
ELECTRONIC
CASH REGISTER
MODEL ER-A440
SRV Key : LKGIM7113RCZZ
PRINTER : DP-730
("U" & "A" version)
CAUTION
EXTREME CAUTION MUST BE TAKEN WHEN SERVICING THIS MACHINE. EVEN
THOUGH THE MODE SWITCH IS IN THE OFF POSITION, VOLTAGE IS STILL SUPPLIED
TO THE ENTIRE MACHINE.
WHEN WORKING ON THIS MACHINE MAKE SURE THAT THE POWER CORD IS
REMOVED FROM THE WALL OUTLET.
CHAPTER 1. SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
CHAPTER 2. OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
CHAPTER 3. SERVICE (SRV) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
CHAPTER 4. HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
CHAPTER 5. TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
CHAPTER 6. DOWN LOAD FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
CHAPTER 7. SERVICE PRECAUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
CHAPTER 8. CIRCUIT DIAGRAM & PWB LAYOUT . . . . . . . . . . . . . . . . . . . 8-1
PARTS GUIDE
SHARP CORPORATION
CONTENTS
This document has been published to be used
for after sales service only.
The contents are subject to change without notice.
Parts marked with " " is important for maintaining the safety of the set. Be sure to replace these parts with specified ones
for maintaining the safety and performance of the set.

CHAPTER 1. SPECIFICATIONS
1. Appearance/Rating
1) Rating
Power source AC 120 V ±10% 50/60Hz
Power consumption Standby: 11.5 W
Maximum: 40 W (max.)
Operating temperature 0°C~40°C (32°F~104°F)
Operating humidity 10%~90% (RH)
Physical dimensions,
including the drawer 420(W) ✕427(D) ✕292(H)mm 16.5(W) ✕16.8(D) ✕11.5(H)in.
Weight 28.7 lbs (13 kg)
2. Keyboard
1) Standard keyboard layout
Fig. 2-1
2) Key top name
WYPL2
WYPL2
WYPL2
WYPL2
RECEIOT
#
PCPT
CL
NS
000
123
456
789
1 6 11 16
2 7 12 17
3 8 13 18
4 9 14 19
5101520
CA/AT
CHK CH
CONV
FS
SHIFT
AUTO
1AUTO 2
PLU/SUB TAX1
SHIFT TAX2 SHIFT
TAX
FS
TEND
SBTL
MDSE
SBTL
JOURNAL
CASH
PRINT
%1 %2 PO
VOID
#
RA
RFND
@/
FOR
Standard Key Top
KEY TOP DESCRIPTION
0 to 9,00 Numeric keys
•Decimal point key
CL Clear key
@/FOR Multiplication/split-pricing key
1 to 20 Department 1 to 20 keys
↑R Receipt Paper Feed key
↑J Journal Paper Feed key
RCPT Receipt print & on/off key
# Non-Add Code key
AUTO 1, 2 Automatically Entry key 1, 2
CASH # Cashier code entry key
NS No Sales key
Discount key
% 1, 2 % key 1, 2
PO 1, 2 Paid Out key
RA Received on Account key
VOID Void key
PLU/SUB PLU/Subdept code entry key
SBTL Subtotal key
CH Charge key
CA/AT Cash/amount tendered
TAX1 SHIFT TAX1 shift key
TAX2 SHIFT TAX2 shift key
TAX Tax key
KEY TOP DESCRIPTION
PRINT Validation print key
RFND Refund key
CONV Currency conversion key
CHK Check key
MDSE SBTL Merchandise subtotal key
FS SHIFT Food stamp shift key
FS TEND Food stamp tendered key
Optional Key Top
KEY TOP DESCRIPTION
% 3, 4 % key 3, 4
2, 3, 4 Discount key 2, 3, 4
AUTO 3 ∼10 Automatically entry key 3 ∼10
CA 2 Cash total 2 key
CH 2 ∼5 Charge key 2 ∼5
CR 3, 4 Credit key 3, 4
21 to 50 Department 21 to 50 key
TAX3 SHIFT TAX3 shift key
TAX4 SHIFT TAX4 shift key
RA2 Received on account key 2
PO2 Paid out key 2
CONV2 ∼4 Currency conversion key 2 ∼4
CHK2 Check key 2
RFND SALE Refund sales key
BIRTH Birthday key
1 to 68 Direct price lookup/Subdepartment keys
1 – 1

3. Mode switch
Fig. 3-1
*The key can be removed in the REG or OFF position.
*In the SRV’ mode, key inputs are prohibited and no display is
made.
*With the key in the off position power is not supplied to the
main PWB.
[Functions]
•Function for each key position
•SRV’: System reset
•SRV: Service mode (Service programming)
•PGM2: Allows programming of an item that is not changed
frequently, in addition to the PGM1 mode program-
ming.
•PGM1: Allows programming of items frequently changed (e.g.
department, PLU pricing, and discount rate setting).
•OP, X/Z:Allows X or Z operation by servers or cashiers.
•REG: Allows registrations.
•MGR: Allows the operations, by authorized person such as a
manager (e.g. correction after transaction finished or
cancellation of entry limits), which are not permitted to
ordinary cashiers.
•X1/Z1: Allows reading and resetting of a day’s sales total.
•X2/Z2: Allows reading or resetting sales totals in a specified
period.
•OFF: Switching off the display to prevent key board entries.
(The setting turn off the AC power.)
4. Display
1) Layout
Operator display
Fig. 4-1
7 segment display (LED)
No. of positions 10
Color of display Yellow Green
Character size 14.2 (H) ✕8.0 (W) mm
Customer display (Pop-up display)
Fig. 4-2
7 segment display (LED)
No. of positions 7
Color of display Yellow Green
Character size 14.2 (H) ✕8.0 (W) mm
Display contents
Display
Position Description
Amount 1-8
Minus sign 4-10 –: Floating
Error 10 E
PGM Mode 10 P
VOID Mode 10 u
CA/AT
CHK, CR 10 F: Lights up when a registration is finalized by depressing CA/AT, CHK,
CR key
SUB TOTAL/
short tender 10 o
Change 10 C: Light up whenever the change due
amount appears in the display.
Department 9-10 No zero-suppressed
PLU 5-10 No zero-suppressed
Repeat 8 Endless count, starting from 2.
Decimal point 3-1 TAB
Receipt OFF 9 (–)
Cashier No. 2-3 –xx–: free code
VP
compulsory 10 U: Light up when the validation printing is compulsory
Sentinel 10 Light up the decimal point
5. Printer (DP-730)
1) Specifications
•Part number: DP-730
•No. of stations: 2
•Printing system: Mechanical serial dot
•Direction of printing: Bidirectional
•Printing capacity: Receipt – 24 characters
Journal – 24 characters
Validation – 55 characters
(one line only)
•Character size: 1.36 (W) ✕2.75 (H) mm at 7 ✕7 dots
Print pitch:
Column distance
Row distance 1.59 mm 5.08 mm
•Total number of dots: Receipt – 108 dots/216 positions
Journal – 108 dots/216 positions
Validation – 248 dots/495 positions
•Font: 7 ✕7 dots (including half dot)
Space between characters – 1 dot (2
positions)
X2/Z2
X1/Z1
MGR
REG
OP,X/Z
PGM1
PGM2
(SRV)
(SRV')
OP
SM
MA
SRV
OFF
1 – 2

•Distance between dots: 0.353 mm (H) ✕0.353 mm (W)
•Journal near end sensor: Service route option
•Print speed: Approx. 3.0 lines/sec.
•Paper feed speed: Receipt – Approx. 30 lines/sec.
Journal – Approx. 30 lines/sec.
•Reliability: MCBF – 4 million lines (excluding the
print head)
Head life – 50 million characters
(at 4 dots/1 character/
1 pin)
•Validation form sensor: Not setup
2) Printing area
Receipt/journal
Fig. 5-1
Validation form
Fig. 5-2
3) Paper
•Paper roll dimensions:44.5±0.5mm in width, 83mm in diameter
•Paper quality: Journal
Bond paper (paper thickness: 0.06 to
0.09mm, paper weight: 52.3 to 64g/m2)
Validation form
Thickness: 0.07 to 0.14mm
Size:
130mm or more (W)✕
70mm or more (H)
4) Inking
•Ink supply system: Ink ribbon
•Form: Cartridge/Endless ribbon
•Specification: Material – Nylon
•Ribbon life: Approx. 6 million characters
•Print color: Purple (single color)
5) Logo stamp: None
6) Cutter
•Method: Manual
6. Drawer
1) Specification
(1) Drawer box and drawer
Model name SK-423
Size 420 (W) ✕427 (L: included lock key)
✕112 (H: included rubber leg)
Color GRAY 368
Material Metal
Bell —
Release lever Standard equipment; Situated at the bottom
Drawer open sensor Standard equipment
2) Money case
For "U" version For "A" version
Separation from the drawer Allowed Allowed
Separation of the coin com-
partments from the money
case
Disallowed Disallowed
Bill separator — YES
Number of compartments 5B/5C 4B/8C
3) Lock
Location of the lock Front
Method of locking
and unlocking Locking: Insert the drawer lock key into the lock and turn it 90 degrees
counterclockwise.
Unlocking: Insert the drawer lock key into
the lock and turn it 90 degrees
clockwise.
Key No. SK1-1
87.08
44.5± 0.5
RECEIPT JOURNAL
Unit : mm
37.87
44.5± 0.5
3.56 3.56 3.56 37.87
4.2
3.56
70
130 ~ 210
87.08 (PRINT AREA)
20
22
Unit : mm
5B/8C
Bill compartments
Coin compartments
Bill separator
5B/5C
For "U" Version For "A" Version
1 – 3

CHAPTER 2. OPTIONS
1. System configuration
Fig. 1-1
(NOTE1)
This symbol shows
NEW MODEL
COMPUTER
LOCAL PURCHASE
OPTION RAM
ER-03RA
ER-A440
MASTER MACHINE
CABLE3.5 inch FDD
ER-01/02FD COMMERCIAL
PRODUCT ER-04DW
REMOTE DRAWER
2 – 1

2. Options
No. NAME MODEL DESCRIPTION
1 EXPANSION RAM CHIP ER-03RA 512K bytes RAM CHIP
2 REMOTE DRAWER ER-04DW
3 PRESETS LOADER ER-01FD/02FD FD unit
4 KEY TOP KIT ER-11KT7 1 ×1 KYE TOP UNIT
ER-12KT7 1 ×2 KYE TOP UNIT
ER-22KT7 2 ×2 KYE TOP UNIT
ER-11DK7G 1 ×1 DUMMY KYE KIT
ER-51DK7G 5 ×1 DUMMY KYE KIT
5 COIN CASE ER-55CC2 for "U" version
6 COIN CASE ER-48CC2 for "A" version
3. Service options
No. NAME PARTS CODE PRICE
RANK DESCRIPTION
1 SERVICE KEY AF
2 MODE KEY GRIP COVER AL OP key only
3 DRIP-PROOF KEYBOARD COVER BE Include the switch cover
4 JOURNAL NEAR END SENSOR BB
5 TEXT PRESET KEYBOARD COVER BH
4. Service tools
No. NAME PARTS CODE PRICE
RANK DESCRIPTION
1 RS-232 LOOP BACK CONNECTOR BU
2 KEY TOP REMOVER BB
5. Supplies
No. NAME PARTS CODE PRICE
RANK DESCRIPTION
1 ROLL PAPER AR 5 roll/pack
2 INK LIBBON AZ
6. Options
For installation of the options, refer to the Installation Manual which is issued separately.
2 – 2

CHAPTER 3. SRV. RESET AND
MASTER RESET
1. SRV. reset (Program Loop Reset)
Used to return the machine back to its operational state after a lock-
up has occurred.
Procedure
•Method 1
1) Unplug the AC cord from the wall outlet.
2) Set the mode switch to (SRV′) position.
3) Plug in the AC cord to the wall outlet.
4) Turn to (SRV) position from (SRV′) position.
•Method 2
1) Set the mode switch to PGM2 position.
2) Turn off the AC switch.
3) While holding down JOURNAL FEED key and RECEIPT FEED
key, Turn on the AC switch.
Note: When disassembling and reassembling always power up us-
ing method 1 only. Method 2 will not reset the CKDC8.
Note: SRV programming job#926-B must be set to "4" to allow PGM
program loop reset.
2. Master reset (All memory clear)
There are two possible methods to perform a master reset.
•MRS-1
Used to clear all memory contents and return machine back to its
initial settings and return keyboard back to default keyboard layout.
Procedure
1) Unplug the AC cord from the wall outlet.
2) Set the MODE switch to the (SRV′) position.
3) Plug in the AC cord to the wall outlet.
4) While holding down JOURNAL FEED key, turn to (SRV) position
from (SRV′) position.
•MRS-2
Used to clear all memory and keyboard contents.
This reset returns all programming back to defaults. The keyboard
must be entered by hand.
This reset is used if an application needs different keyboard layout
other than that supplied by a normal MRS-1.
Procedure
1) Unplug the AC cord from the wall outlet.
2) Set the MODE switch to the (SRV′) position.
3) Plug in the AC cord to the wall outlet.
4) While holding down JOURNAL FEED key and RECEIPT FEED
key, turn to (SRV) position from (SRV′) position.
5) Key position assignment:
After the execution of MRS-2, only the RECEIPT FEED and
JOURNAL FEED keys can remain effective on key assignment.
Any key can be assigned on any key position on the main key-
board.
[key setup procedure]
NOTES:
1: When the 0 key is pressed, the key of the key number on display
is disabled.
2: Push the key on the position to be assigned. With this, the key of
the key number on display is assigned to that key position.
Key number Key name Key number Key name
1 Numeric key "0" 10 Numeric key "9"
2 Numeric key "1" 11 Numeric key "00"
3 Numeric key "2" 12 Numeric key "000"
4 Numeric key "3" 13 Decimal point key
5 Numeric key "4" 14 CL key
6 Numeric key "5" 15 @/FOR key
7 Numeric key "6" 16 SBTL key
8 Numeric key "7" 17 CA/AT key
9 Numeric key "8"
MRS-2
executed
Key position set Free key
Disable
Free key setup
complete.
*2
*1
0
0
3 – 1

CHAPTER 4. HARDWARE DESCRIPTION
1. Hard ware block diagram
Fig. 1-1
CPU
GATE ARRAY
MPCA7
DRAWER
STANDARD
RAM1
32KBx2
OPTIONAL
RAM
512KB
ER-03RA:512KB
STANDARD
ROM
256KB
SWITCH
KEY BOARD
RS232
I/F
1 ports
CKDC8
1 LINE
7SEG 7DIG
1 LINE
7SEG 10DIG
CUSTOMER DISPLAY
OPERATER DISPLAY
PRINTER
DP-730
RAM2
4 – 1

2. Description of main LSI’s
2-1. CPU (HD6415108-10)
1) Pin configuration
HD6415108-10 pin configuration
Fig. 2-1
RES
NMI
VSS
P10
P11
P12
P13
P14
P15
P16
P17
D0
D1
D2
D3
D4
D5
D6
D7
VSS
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
STBY
MD2 MD1 MD0 VCC
RFSH
LWR
HWR
RD
AS
E
VSS XTAL
EXTAL
VSS
TXD2
RXD2
TXD1
RXD1
SCK2
UASKC
IRQ1 IRQ0
VCC
AVCC
AN3 AN2
112 111 110 109 108 107 106 105 104 103 102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
P41
P42
P43
P44
P45
P46
P47
VSS
P50
P51
P52
P53
P54
P55
P56
P57/STOP
P60
P61
P62
P63
P64
P65
P66
P67
VSS
AVSS
AN0
AN1
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
78
80
81
82
83
84
A8 A9
A10 A11 A12 A13 A14 A15
VSS
A16 A17 A18 A19 A20 A21 A22 A23
VSS
WAIT
BACK
BREQ
P33 P34 P35 P36 P37
VCC
P40
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
X
4 – 2

2) Block diagram
Fig. 2-2
P47
FTI2
P45
FTI1
P43
P42
P41/TMCI
P40
P37
P36
P35
P34
P33
BREQ
BACK
WAIT
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AVCC
AVSS
MD2
MD1
MD0
RES
STBY
NMI
AS
RD
HWR
LWR
RFSH
EXTAL
XTAL
E
P17 P16 P15 P14 P13 P12 P11 P10
D7 D6 D5 D4 D3 D2
D1 D0
STOP/P57
P56
FMRS
P54 P53 P52 P51 P50 P67 P66
RS/P65
RR/P64 CD/P63
CS/P62
DR/P61
ER/P60
P73
AN2 AN1 AN0
TXD2
RXD2
TXD1
RXD1
SCK2
IRQ2 IRQ1 IRQ0
H8/500 CPU DTC
Serial
communication
interface x 2ch
8bit timer
16bit free running
timer x 2ch
Refresh controller
Wait state
controller
A/D convertor
Interruption controller
Clock
oscillator Watch dog timer
Data bus Port 1
Data bus (Lower) Data bus (Upper) Address bus
Port 2
Port 3Port 4
Port 5Port 6Port 7Port 8
Address bus
X
4 – 3

3) Pin description
PIN
No. SYMBOL SIGNAL NAME IN/ OUT FUNCTION
1 IN RESET INPUT from CKDC WUTH
BUFFER
2IN NON-MASKABLE INTERRUPT INPUT
FOR SSP INTERRUPT INPUT
3 VSS VSS GND
4 P10 ERC OUT EVENT READ CANCEL (to CKDC)
5 P11 LDRQ OUT LOAD REQUEST (to CKDC)
6 P12 /SHEN IN SHIFT ENABLE (from CKDC)
7 P13 /FRES OUT FISCAL MEMORY RESET (NU)
8 P14 BUSY IN FISCAL MEMORY BUSY (NU) Pull-up
9IN FISCAL MEMORY READY (NU)
Pull-up
10 IN POP-UP DISPLAY SENSOR (NU)
Pull-up
11 P17 IN GND Nu
12 D0 D0 I/O DATA BUS 0
13 D1 D1 I/O DATA BUS 1
14 D2 D2 I/O DATA BUS 2
15 D3 D3 I/O DATA BUS 3
16 D4 D4 I/O DATA BUS 4
17 D5 D5 I/O DATA BUS 5
18 D6 D6 I/O DATA BUS 6
19 D7 D7 I/O DATA BUS 7
20 VSS VSS GND
21 A0 A0 OUT ADDRESS BUS 0
22 A1 A1 OUT ADDRESS BUS 1
23 A2 A2 OUT ADDRESS BUS 2
24 A3 A3 OUT ADDRESS BUS 3
25 A4 A4 OUT ADDRESS BUS 4
26 A5 A5 OUT ADDRESS BUS 5
27 A6 A6 OUT ADDRESS BUS 6
28 A7 A7 OUT ADDRESS BUS 7
29 A8 A8 OUT ADDRESS BUS 8
30 A9 A9 OUT ADDRESS BUS 9
31 A10 A10 OUT ADDRESS BUS 10
32 A11 A11 OUT ADDRESS BUS 11
33 A12 A12 OUT ADDRESS BUS 12
34 A13 A13 OUT ADDRESS BUS 13
35 A14 A14 OUT ADDRESS BUS 14
36 A15 A15 OUT ADDRESS BUS 15
37 VSS VSS GND
38 A16 A16 OUT ADDRESS BUS 16
39 A17 A17 OUT ADDRESS BUS 17
40 A18 A18 OUT ADDRESS BUS 18
41 A19 A19 OUT ADDRESS BUS 19
42 A20 A20 OUT ADDRESS BUS 20
43 A21 A21 OUT ADDRESS BUS 21
44 A22 A22 OUT ADDRESS BUS 22
45 A23 A23 OUT ADDRESS BUS 23
46 VSS VSS GND
47 /WAIT /WAIT IN Wait signal from MPCA
48 OUT Bus control request acknowl edge (Nu)
49 /BREQ /BREQ IN Bus control request (Nu) pull-up
50 P33 DOPS IN Drawer open sencer signal
51 P34 /DR0 OUT Drawer open drive signal
52 P35 /DR1 OUT Option drawer 1 drive signal
53 P36 NU IN (Nu) GND
54 P37 NU IN (Nu) GND
55 VCC VCC +5V
56 P40 /IFV IN Slip printer enable (Nu) pull-up
57 IN Printer (Dp-730) timing signal from
MPCA
PIN
No. SYMBOL SIGNAL NAME IN/ OUT FUNCTION
58 P42 /TOF IN Slip TOF signal (Nu) pull-up
59 P43 /BOF IN Slip BOF signal (Nu) pull-up
60 IN Printer (Dp-730) Reset signal from
MPCA
61 P45 /NEJ IN Near END signal jounal
62 IN CKDC interface shift enable signal
(NU) GND
63 P47 /NER IN Near END signal receipt
64 VSS VSS GND
65 P50 TRG1 OUT Dot pulse adjust signal
66 P51 /PSTOP OUT Nu
67 P52 /CKDCR2 OUT Nu
68 P53 OPDS IN Nu (GND)
69 P54 FVPON OUT Nu
70 P55 FMRS IN Nu (GND)
71 P56 /SLIPLMP OUT Nu
72 P57 /STOP OUT Nu
73 OUT ER signal for RS232 (Equipment
Ready)
74 IN DR signal for RS232 (Data set Ready)
75 IN CS signal for RS232 (Clear to Send)
76 IN CD signal for RS232 (Carrier Detect)
77 OUT RR signal for RS232 (Ready to
Receive) (Nu)
78 OUT RS signal for RS232 (Request to Send)
79 IN CI signal for RS232 (Calling Indicator)
80 IN Printer (Dp-730) Home position pulse
81 VSS VSS GND
82 AVSS AVSS IN GND
83 P70 VPJ IN Validation sensor journal (NU) GND
84 P71 VPR IN Validation sensor receipt (NU) GND
85 P72 VPTEST IN +24V test input
86 P73 IN Validation sense signal (Nu) GND
87 AVCC AVCC IN +5V
88 VCC VCC +5V
89 P80 /iRQ0 IN Interrupt signal 0 from MPCA
90 IN Interrupt signal from OPTION PWB
91 P82 /iRQ2 IN Interrupt signal (Nu) pull-up
92 P83 SCK2 OUT CKDC & FMC i/F sync shift clock
93 P84 RXD IN RS232C RECEIVE DATA
94 P85 TXD OUT RS232C SEND DATA
95 IN CKDC, Fiscal memory unit I/F shift
input data
96 OUT CKDC, Fiscal memory unit I/F shift
output data
97 VSS VSS GND
98 EXTAL EXTAL IN X-TAL (14.7456MHz)
99 XTAL XTAL IN X-TAL (14.7456MHz)
100 VSS VSS GND
101 φφ OUT System clock (7.3728MHz)
102 E OUT E clock (NU)
103 /AS /AS OUT Address strobe
104 /RD /RD OUT Read
105 /HWR /WR OUT Write
106 /LWR OUT Nu
107 /RFSH /RFSH OUT Refresh cycle (NU)
108 VCC VCC +5V
109 MD0 MD0 IN +5V (MODE 3)
110 MD1 MD1 IN +5V (MODE 3)
111 MD2 MD2 IN GND (MODE 3)
112 /STBY /STBY IN +5V (Nu)
4 – 4

2-2. G.A (MPCA7)
1) Pin configuration
GATE ARRAY (LZ9AH39)
MPCA7
Fig. 2-3
1RF 2JF 3PCUT 4FCUT 5VF 6STAMP
7 SLF
8SLRS 9SLMTD 10RES 11TRG
12TRG
13POFF 14INT1 15HTS1 16SCK1 17STH1 18NU 19NU 20VCC 21GND 22NU 23VRESC 24SLTMG 25SLRST 26AS 27RD 28WR 29
PHAI
30SDT7
31SDT6
32SDT5 33GND 34SDT4 35SDT3
36SDT2
37SDT1 38D0 39D1 40D2
160 NU 159 DOTEN 158 TWAIT
157 NU
156 NU 155 NU 154 NU 153 NU 152 STH2 151 SCK2 150 HTS2 149 SLMTR 148 SLMTS 147 SLMTD 146 RJMTR 145 RAS3 144 NU 143 GND 142 VCC 141 ASKRX
140 NU
139 NU 138 NU 137 RJMTD
136 RJMTS
135 DT5 134 DT6 133 DT7 132 GND 131 DT1 130 DT2 129 DT3
128 DT4
127 RJTMG 126 RJRST 125 RAS1 124 RAS2 123 ROS2 122 ROS1 121 OPTCS
41
D3 42GND 43 D4 44
D5 45
D6 46 D7 47SSPRQ 48
RESET
49
INT2
50
INT3 51RXDI 52TXDI 53SCKI 54IRQ0
55A0 56A1 57A2 58A3 59A4 60A5
61GND 62VCC 63A6 64A7 65A8 66A9 67A10 68A11 69A12 70A13 71A14 72A15 73A16
74A17 75A18 76A19 77A20 78A21 79A22 80NU
120 EXINT0
119 EXINT1
118 EXINT2
117 EXINT3
116 WRO
115 RDO
114 RA15
113 RA16
112 GND
111 RA17
110 RA18
109 EXWAIT
108 WAIT
107 NU
106 MCR1
105 NU
104 DAX1
103 RCKX
102 IRRX
101 GND
100 VCC
99
UATX
98 UARX
97
UASCK
96 IRTX
95 RCO
94 NU
93 NU
92 NU
91 NU
90 MA15
89 TEST
88 MD0
87 MD1
86 IPLON
85 INT4
84 PRST
83 PTMG
82 TRGI
81 A23
4 – 5

2) Block diagram
Fig. 2-4
MTD
MTD
RJMTR
SLMTD
SLMTS
SLMTR
SLMTD
TXDI
SCKI
RXDI
HTS1
SCK1
STH1
HTS2
SCK2
STH2
ROS1
ROS2
RAS1
RAS2
RAS3
OPTCS
AS
RD
WR
RDO
WRO
Φ
RESET
RES
VRESC
POFF
MD0
MD1
WAIT
RJRST
SLRST
*PRST
RJTMG
SLTMG
PTMG
INT4
INT1
INT2
INT3
EXINT0
EXINT1
EXINT2
EXINT3
SDT1~7 DT1~9
TEST
IRQ0
A23~A0
SSPRQ
SLF SLRS
VF
RF JF FCUT PCUT STAMP
TRGI
TRG TRG DOTEN
IRLON
D0~D7
Φ
Address decode
External CS
Internal CS
RASEL
Image
control
SSP comparison register
BAR.
Buffer
Read/write
control
Divider
CHS
serial select Multiplexer
WAIT
control
CAPS
select
Print gate
Print pulse control
Print mode PMD
INTO
control
Printer control port
Motor
drive
* Output selection with CAPS.
PRST/PTMG.
EXWAIT
I/R Control
IRTX
IRRX
RCI
ASKRX
4 – 6

3) Pin description
Pin
No. Signal name In/ Out Function
1 RF Out Receipt side paper feed solenoid
2 JF Out Journal side paper feed solenoid
3PCUT Out Printer partial cut signal (NU)
4FCUT Out Printer auto cut signal (NU)
5VF Out Multi line validation paper feed (NU)
6STAMP Out Printer stamp signal (NU)
7SLFS Out Slip printer paper feed singnal (NU)
8SLRS Out Slip printer release signal (NU)
9SLMTD Out Slip printer motor drive signal (NU)
10 RES Out Peripheral output reset
11 TRG Out Dot head trigger signal (NU)
12 TRG Out Dot head trigger signal
13 POFF In Power off signal input
14 INT1 In (NU)
15 HTS1 Out 8 bit serial port output (for CKDC8)
16 SCK1 Out Serial port shift clock output (for CKDC8)
17 STH1 In 8 bit serial port input (for CKDC8)
18 RAS VZ — Chip select (NU)
19 — — Nu
20 VCC — +5V
21 GND — GND
22 INTMCR — Interrupt (NU)
23 VRESC Out Turns active when reset and power
down is met
24 SLTMG In Slip printer timing signal (NU)
25 SLRST In Slip printer reset signal (NU)
26 AS In Address strobe
27 RD In Read strobe
28 WR In Write strobe
29 φIn (φ) System clock (7.3728 MHz)
30 SDT7 Out Slip printer printhead drive signal (dot7)
(NU)
31 SDT6 Out Slip printer printhead drive signal (dot6)
(NU)
32 SDT5 Out Slip printer printhead drive signal (dot5)
(NU)
33 GND — GND
34 SDT4 Out Slip printer printhead drive signal (dot4)
(NU)
35 SDT3 Out Slip printer printhead drive signal (dot3)
(NU)
36 SDT2 Out Slip printer printhead drive signal (dot2)
(NU)
37 SDT1 Out Slip printer printhead drive signal (dot1)
(NU)
38 D0 I/O Data bus 0
39 D1 I/O Data bus 1
40 D2 I/O Data bus 2
41 D3 I/O Data bus 3
42 GND — GND
43 D4 I/O Data bus 4
44 D5 I/O Data bus 5
45 D6 I/O Data bus 6
46 D7 I/O Data bus 7
47 SPRQ Out SSP interrupt request to CPU
48 RESET In MPCA reset
49 SHEN In Shift enable from CKDC8
Pin
No. Signal name In/ Out Function
50 INT3 In Interrupt signal (Nu)
51 RXD2 Out 8 bit serial port output to CPU
52 TXD2 In 8 bit serial port input from CPU
53 SCK2 In Serial port shift clock input from CPU.
54 IRQ0 Out Interrupt request to CPU
55 A0 In Address bus 0
56 A1 In Address bus 1
57 A2 In Address bus 2
58 A3 In Address bus 3
59 A4 In Address bus 4
60 A5 In Address bus 5
61 GND — GND
62 VCC — +5V
63 A6 In Address bus 6
64 A7 In Address bus 7
65 A8 In Address bus 8
66 A9 In Address bus 9
67 A10 In Address bus 10
68 A11 In Address bus 11
69 A12 In Address bus 12
70 A13 In Address bus 13
71 A14 In Address bus 14
72 A15 In Address bus 15
73 A16 In Address bus 16
74 A17 In Address bus 17
75 A18 In Address bus 18
76 A19 In Address bus 19
77 A20 In Address bus 20
78 A21 In Address bus 21
79 A22 In Address bus 22
80 LCDC — LCD CS (NU)
81 A23 In Address bus 23
82 TRGI In Dot pulse control/drive signal
83 PTMG Out Printer timing signal
84 PRST Out Printer reset signal
85 RDY In Ready from FMC unit
86 IPLON In To option connector (NU)
87 MD1 In Mode select input (+5V)
88 MD0 In Mode select input (GND)
89 TEST In +5V
90 MA15 — Image address 15 (NU)
91 MA18 — Nu
92 MA19 — Nu
93 RCVRDY1 — Nu
94 RCVRDY2 — Nu
95 RC0 — Remote control encord signal for CPU
96 IRTX — I/R output for LED (NU)
97 UASCK — I/R serial data shift clock (NU)
98 UARX — I/R serial data for CPU (NU)
99 UATX — I/R serial data from CPU (NU)
100 VCC — +5V
101 GND — GND
102 IRRX — I/R input from I/R unit (NU)
103 RCI — I/R input from I/R unit (NU)
104 DAX1 — System clock (7.3728MHz)
4 – 7

Pin
No. Signal name In/ Out Function
105 DAX2 — Nu
106 MCR1 — Nu
107 MCR2 — Nu
108 WAIT Out Wait request signal
109 EXWAIT In External wait control input signal
110 RA18 Out Nu
111 RA17 Out Nu
112 GND — GND
113 RA16 Out Nu
114 RA15 Out Nu
115 RDO Out Expansion RD signal Option
116 WRO Out Expansion WR signal
117 EXINT3 In Expansion interruption signal 3
Option
118 EXINT2 In Expansion interruption signal 2
119 EXINT1 In Expansion interruption signal 1
120 EXINT0 In Expansion interruption signal 0
121 OPTCS Out Chip select base signal for expansion
option
122 ROS1 Out ROM 1 chip select signal
123 ROS2 Out ROM 2 chip select signal (NU)
124 RAS2 Out RAM 2 chip select signal
125 RAS1 Out RAM 1 ship select signal
126 RJRST In Printer reset signal
127 RJTMG In Printer timing signal
128 DT4 Out Printer dot signal 4
129 DT3 Out Printer dot signal 3
130 DT2 Out Printer dot signal 2
131 DT1 Out Printer dot signal 1
132 GND — GND
133 DT7 Out Printer dot signal 7
134 DT6 Out Printer dot signal 6
135 DT5 Out Printer dot signal 5
136 MTD Out Printer motor drive signal
137 MTD Out Printer motor drive signal
138 DOT9 Out Printer dot signal 9 (NU)
139 DOT8 Out Printer dot signal 8 (NU)
140 SYNC — Nu (+5V)
141 ASKRX — I/R input from I/R unit (NU)
142 VCC — +5V
143 GND — GND
144 — — Nu
145 RAS3 Out
146 RJMTR In Printer motor lock detection signal (NU)
147 SLMTD In Nu
148 SLMTS In Nu
149 SLMTR In GND
150 HTS2 Out Serial output to FMC unit (NU)
151 SCK2 Out Serial clock to FMC unit (NU)
152 STH2 In Serial input to FMC unit (NU) pull-up
153 — — Nu
154 — — Nu
155 — — Nu
156 — — Nu
157 — — Nu
158 LCDWT — Nu
159 DOTEN Out Dot drive enable signal
160 RASP — Nu
2-3. CKDC8
1) Pin configulation
2) Pin assignment (CKDC8)
Pin
No. SYMBOL SIGNAL
NAME IN/ OUT FUNCTION
1 DP DP OUT DISPLAY SEGMENT Dp
2 A SA OUT DISPLAY SEGMENT a
3 B SB OUT DISPLAY SEGMENT b
4 C SC OUT DISPLAY SEGMENT c
5 D SD OUT DISPLAY SEGMENT d
6 E SE OUT DISPLAY SEGMENT e
7 F SF OUT DISPLAY SEGMENT f
8 G SG OUT DISPLAY SEGMENT g
9 VSS0 GND GND
10 VDD0 VDD VDD
11 KR4 KR4 IN KEY RETURN 4
12 KR10 KR10 IN KEY RETURN (feed clerk
MRS sw)
13 KR11 KR11 IN KEY RETURN (MODE sw)
14 KR8 NU IN GND
15 HTS HTS IN
16 STH STH OUT
17 /SCK /SCK IN SHIFT CLOCK
18 ST0 ST0 OUT KEY STROBE 0
19 ST1 ST1 OUT KEY STROBE 1
20 ST2 ST2 OUT KEY STROBE 2
21 ST3 ST3 OUT KEY STROBE 3
22 ST4 ST4 OUT KEY STROBE 4
23 ST5 ST5 OUT KEY STROBE 5
24 VDD1 VDD VDD
25 AXSS GND GND
26 KR9 NU GND
27 KR0 KR0 IN KEY RETURN 0
28 KR1 KR1 IN KEY RETURN 1
29 KR2 KR2 IN KEY RETURN 2
30 KR3 KR3 IN KEY RETURN 3
31 KR5 KR5 IN KEY RETURN 5
32 KR6 KR6 IN KEY RETURN 6
NU NU G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 BUZ /POFF NU ST8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DP
SA
SB
SC
SD
SE
SF
SG
GND
VDD
KR4
KR10
KR11
NU
HTS
STH
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ST7
ST6
/RESETS
/SHEN
ERC
LDRQ
GND
GND
/RES0
VDD
GND
KR7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
/SCK
ST0 ST1 ST2 ST3 ST4 ST5
VDD
GND
NU
KR0 KR1 KR2 KR3 KR5 KR6
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
CKDC8
4 – 8

Pin
No. SYMBOL SIGNAL NAME IN/ OUT FUNCTION
33 KR7 KR7 IN KEY RETURN 7
34 AVRF GND
35 AVDD VDD
36 /RESET /RES0 IN
37 XT2 32.768 KHz
38 XT1
39 IC GND
40 X2 4.19 MHz
41 X1
42 VSS1 GND
43 LDRQ LDRQ IN LORD REQUEST
44 ERC ERC IN EVENT READ CANCEL
45 SHEN /SHEN OUT SHIFT ENABLE
46 /RES1 /RESETS OUT SYSTEM TO RESET
47 ST6 ST6 OUT KEY STROBE 6
48 ST7 ST7 OUT KEY STROBE 7
49 ST8 ST8 OUT KEY STROBE 8
50 ST9 NU OUT KEY STROBE 9
51 /POFF /POFF IN POWER OFF
52 BUZ BUZ OUT BUZZER
53 T0 G1 OUT DISPLAY DIGIT 1
54 T1 G2 OUT DISPLAY DIGIT 2
55 T2 G3 OUT DISPLAY DIGIT 3
56 T3 G4 OUT DISPLAY DIGIT 4
57 T4 G5 OUT DISPLAY DIGIT 5
58 T5 G6 OUT DISPLAY DIGIT 6
59 T6 G7 OUT DISPLAY DIGIT 7
60 T7 G8 OUT DISPLAY DIGIT 8
61 T8 G9 OUT DISPLAY DIGIT 9
62 T9 G10 OUT DISPLAY DIGIT 10
63 T10 NU OUT DISPLAY DIGIT 11
64 ID NU OUT DISPLAY SEGMENT
3. Clock generator
1) CPU (HD64151010FX)
Fig. 3-1
Basic clock is supplied from a 14.7456MHz ceramic oscillator.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
2) CKDC8 oscillation circuit
Fig. 3-2
Two oscillators are connected to the CKDC8.
The main clock X3 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC8 goes into the standby mode
and the main clock stops.
The sub-clock X2 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
4. Reset (POFF) circuit
Fig. 4-1
In order to prevent memory loss at a time of power off and power
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal STOP forced low to prepare for the power-off situation.
The signal STOP is supplied to the CKDC8 as signal RESET to reset
the devices.
CPU
(HD64151010FX)
99
98
XTAL
EXTAL
14.7456MHz
X1
101
PHAI
37
38
33P
HD404728A91FS
C105
CKDC 8
X2
X3
4.19MHz
X2
32.768KHz
2
1
3
41
18P
C106
40
X1
XT2
XT1
R164
330K
+
-/POFF
3
21
4
8B
IC3A
KIA393F C3
1000P
D7
1SS133
C208
1µ 50V
+
ZD2
MTZ5.1A
R14
9.1KG
R13
15KG
R10
56K
R11
2.7K R9 2.7K
R12
8.2KG
+24V +5V
POFF
CPU
72
IRQ0
89
RESET (FROM CKDC 8)
STOP (TO CKDC 8)
MPCA7
13 48
1
IRQ0
54
INT0
4 – 9

This circuit monitors +24V supply voltage.
The voltage at the (–) pin of the comparator IC3A is always main-
tained to 5.1V by means of the zener diode ZD2, while +24V supply
voltage is divided through the resistors R12, R13, and R14, and is
applied to the (+) pin. When normal +24V is in supply, 6.8V is sup-
plied to the (+) pin, therefore, signal POFF is at a high level. When
+24V supply voltage decreases due to a power off or any other
reason, the voltage at the (+) pin also decreases. When +24V supply
voltage drops, the voltage at the (+) pin drops below +5.1V, which
causes POFF to go low, thus predicting the power-off situation.
The STOP signal from the CPU is converted into the RESETS signal
by the CKDC6.
The RESETS signal from the CKDC8 is converted into the RESET
signal at the gate backed-up by the VRAM power, performing the
system reset.
5. Memory control
1) Memory map
All range memory map
Fig. 5-1
(1) “Internal I/O” means the registers in the H8/510.
(2) “External I/O” means the base system I/O area to be ad-
dressed in page 0.
(3) "Memory image area" means the lower 32KB of ROM area
which is projected to 000000H ~ 007FFFH for allowing reset
start and other vector addressing, or the lower 32KB of RAM
area which is projected to 008000H ~ 00FE7FH for allowing 0
page addressing of work RAM area.
(4) “Expansion I/O” means expansion I/O device area which isad-
dressed to area other than page 0.
0 page memory map
Fig. 5-2
•ROM image area: Image is formed in ROM area address
C00000H to C07FFFH. This area is identical to IPL ROM area
which will beseparately developed.
•RAM image area: Image is formed in RAM area address 1F0000H
to 1F7E7FH. ( Note)
Note: Image can be formed in lower 32KB of RAS2.
ROM area memory map
Fig. 5-3
RESETS
STOP
CKDC8
RAS3 4
5 6
IC10B
74HC00S
/(RAS3./RESET)
/RESET
1
2 3
IC10A
74HC00S
VDD
C86
1000P C87
1000P
R123
10K C88
1000P
9
10 8
14
IC10C
74HC00S
14
14
VDD
VDD
Internal I/O
External I/O
Memory image area
(*1)
(*2)
(*3)
RAM area
(10M byte)
ROM area
(3M byte)
Expansion I/O area (1M byte)
000000H
1C0000H
C00000H
FFFFFFH
000000H
004000H
008000H
00FFFFH
1FFFFFH
ROM image area
32KB
RAM image area
slightly smaller than32KB
NOT USE
00F800H
00FE80H
00FF80H
00FFFFH
RAM image area
Internal I/O area
External I/O area
(0 page)
1BFFFFH RAM area
C00000H
D00000H
EFFFFFH
ROS3
NOT USE
ROS1
(256K Byte)
C40000H
CA0000H
ROS2
(Not used)
4 – 10

RAM area memory map
Fig. 5-4
Note: RAS2 signal is formed as OR in the image area of 0 page.
(lower32KB).
I/O area memory map
Fig. 5-5
Note 1: MPCCS signal is the base signal for MPCA7 internal reg-
isterdecoding, and does not exist as an internal signal.
Note 2: OPCCS1 and OPCCS2 signals are decoded in the OPC
(optionperipheral controller) using the base signal OPTCS
for optiondecoding. They does not exist as external sig-
nals.
2) Block diagram
Fig. 5-6
ROM control
Fig. 5-7
IPLON: IPL board detection signal incorporated in the option slot.
Note used in the ER-A445P. (Not used)
Access is performed with two ROM chip select signals ROS1 and
ROS2, which decode 512KB address area respectively to access-
max. 4MB ROM.
RAM control
Fig. 5-8
Access is performed with two RAM chip select signals, RAS2 and
RAS3. The control register in MPCA7 allows selection of pageimage
memory area. (RAS1 is selected for initializing.)
: For 0 page image area, selection between RAS2 and RAS3 can
bemade with the control register. The 0 page control registerper-
forms initializing at the timing of no stack processimmediately
after resetting.
100000H
400000H
BFFFFFH
NOT USE
NOT USE
RAS1 (Not use)
RAS2 64K Byte
RAS3
512K Byte
1C0000H
1F0000H
200000H
(MAX 2MB)
280000H
(OPTION)
00FF80H
00FFA0H
00FFFFH
MPCCS
NOT USE
NOT USE
NOT USE
OPCCS1
OPCCS2
00FFC0H
00FFD0H
00FFE0H
00FFF0H
(*1)
(*2)
(*2)
00FFE8H
MCR1 (NOT USE)
MCR2 (NOT USE)
NOT USE
CPU MPCA7
ROM1
(STANDARD)
RAM1
RAM2
(OPTION)
RAM
Data bus
Address bus
ROS1
RAS2 RAS3
Address
A23~A14
(IPLON)
Address
decorder
C80000H~CFFFFFH
C00000H~C7FFFFH
000000H~007FFFH
MPCA7
ROS2
ROS1
Address
A23~A14
Address
decorder
1C0000H~1DFFFFH
008000H~
00F7FFH
*1
1E0000H~1FFFFFH
RAS1
RAS2
RESET
D
CK
Q
R
DOI
S8F Control register
MPCA7
RAS3
200000H~3FFFFFH
4 – 11

6. SSP circuit
1) Block diagram
This is the circuit employed to do the Special Service Preset(SSP).
(Block diagram)
Fig. 6-1
(MPCA7 block diagram)
Fig. 6-2
As the address detection system, the brake address register compari-
son system is employed though the mapping system was employed
in the conventional monitor RAM. The address registerlocated in
MPCA is always compared with the system address bus to monitor
and generate NMI signal at a synchronized timing and togo to NMI
exception process.
In the exception process routine service routine, the entry address is
checked to go to SSP sub routine.
Entry to the break address register (BAR) is performed through ad-
dress FFFF00H or later decoded in MPCA7.
2) SSP register
The break address register (BAR) is accessed through direct address
of FFFF00H~FFFFFFH. Entry number is 32 entry.
Fig. 6-3
Each BAR is composed of 4 byte address. Bit composition is as
follows:
Fig. 6-4
is the enable register. The entry registers of the break address are
assigned to , , and . Each bit of address corresponds to each
bit position, writing to , , and is performed without shifting. The
corresponding area is 1MB space of ROS1 and ROS2.
CPU MPCA7
A0~23
D0~D7
NMI SSPRQ
D0~
D7
A23~
A0
BAR 0
BAR N
REGCS
Decode
Comparator
Coincide
Coincide
SPE
(Enable register)
SSPRQ
(NMI)
Control signal
ROMCS
O
N
1
2
3
4
FFFF00
H
1
2
3
4
5
6
7
BAR0
BAR1
BAR2
70
1234
A19 A18 A17 A16 A15 A8 A7 A2
EN
Upper bits Intermediate bits Lower bits Enable register
EN (bit7) = 1 Enable
= 0 Inhibit
Don't care for "-----."
< BAR composition >
4 – 12

3) SSP register access method
Access to SSP break address register is performed through the tem-
porary register as shown below:
Fig. 6-5
Enable flags can be accessed individually.
Though enable register can be accessed individually, writing to
brake address registers and is performed at the same time as
writing to brake address register through the temporary register.
Therefore, set and to temporary, then write into at last.
Since the temporary register is commonly used by BAR sets, thefol-
lowing register setting is performed after completion ofsetting of each
break address register.
SSP control method
Access to the enable register and the brake address register is only
possible when writing to them from the CPU.
Information on which brake register the SSP brake is detected in is
read as binary data by reading address FFFFFFH (*1).
Used in an expanded register.
Normally is a reserve bit. Whenreading, fixed to 0.
If there are 32 break registers, binary expression is made with the
above 5 bits, and 0th is “00000B” and 31st is “11111B.”
When detected simultaneously by two or more break registers,
onewith the smaller BAR number is read as binary data.
The brake signals (NMI) and the above detection data (CMP0~4)
areheld until the above detection data are read. So read should be-
made in the NMI sub routine. (Clear by FFFFFFH read.)
1: FFFFFFH is not fulldecoded. (FFFF00H~FFFFFFH). There-
fore,unnecessary read access in parentheses should not be
performed.
1 2 3
4
A19 A18 A17 A16 A15 A8 A7 A2 EN
WR
WR
Temporary Temporary
bit 7 654321
000
CMP4
0
CMP3 CMP2 CMP1 CMP0 (FFFFFFH)
7. PRINTER control circuit
1) Block diagram
Fig. 7-1
2) General description of the printer controller
The DP-730 is used as the R/J printer. The printer mechanical timing
control is made by the CPU through MPCA7.
3) Printer motor drive circuit
When the MTD is high, the motor rotates.
When the MTD is low, the motor stops.
CPU Data
bus
MPCA7
DRIVER
PRINTER
(DP-730)
RECEIVER
Address bus
MTD
MPCA7 M
Speed limiter
circuit
2.2K
R128
+24V
C92
DP
Normal 555µs (516~590µs)
Main PWB side Printer side
R127
COM
Q7
C227
MTD
DP
4 – 13