Sharp Pc-1500 User manual

----SHARP----

SERVICE

MANUAL

PC-1500

WWW.

PC-1500

.INFO

SHARP

CORPORATION

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MODEL-PC-1500

TABLE OF CONTENTS

I.

General Description

.......

........

............

.

.......

.

2.

Block Diagram . . . . . . . • . . . • . . . • . . . • . . . • • • . . . • . . . . . . . . . . 3

3. U l

58

1J

1/0

Po

rt

. . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . 9

4. Circuit Description .

..

. .

........

.

..........

..

. .

..

. . .

.•..

14

5. Se

rvi

ci

ng . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . • . . . . . . 19

6.

PC.J500

Key

& PowerSupply Circuit

...

, . . . , . . . . . . . . . . . . . . . . .

21

?. P

C-

15

00

Key

P.W.B

......

.

....

..

. . ,

...

,

...

.

..

.

..

.

..

.

..

. .

22

8.

PC-

1500 Main P.W.B. . .

..

. .

...

•.......•

.....•

.....

......

23

9.

PC

-1500 Main

Ci

rcuit

Di

agram

...........•.....•

. . . . . . . . . . . 24

IO

.

LCD

Segment & Back-Plate Signal

......•...•••...•....•.....

25

11. Parts

Lis

t & Guide

..........

...........

•....

•

..

.

...

.

....

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1.

GENERAL

DESCRIPTION

(1J Key

lay

out

Adap

tor

jack

Used

to

supply pcwer from AC line via

the

EA·l

50

AC

Adaptor

tha

t

comes

with the

op

ti

on unit.

CE-150

.

SOF

T KEY DISPLAY

SHIFT

KEY

.

150:

C=.f

<

fi:t:A+

B:tB-2:t:1i:t:

B:t

:

COS

~

• Iii

..

...

.

~

• .

amama

:a :

mraaa

·• ·

••&1·

au

a a a

Cl

a .a 11

••

• ·

r:il

a a a a

am

ma

II

m • •

tiil

.m

. .

s

11

L

rn

~

• m

~

:

~

c~:r

• Kinds

of

k~

ys

MOOE KEY

CLEAR/CLEAR

ALL

KEY

---'

POWER

ON/BREAK

KEY

--

-'

POWER

OFF

KEY

----'

Th

ere are

65

keys

in

al

l, and their functions differ depending on how

wh

etheroperation is per-

formed

ope

rated,

in

dependently

or

in

conjunction with thelSHIFTlkcy.

(2) Power

on/off

Dep

res

sion

of

theI

ON

Ikey that is located on the upper right corner.

of

the keyboard causes the

power

to tum

on

<111d

the

following

p

rom

pt

a

pp<:

auon

the

ll

is

p

lay

.

BATTERY

INDICATOR

[

~

--

·"

~

·-··

_

_____,

·

]_J

HEl·H)?

:

CHECK

.

L

If

an

op

tion is connected, a

numbe

r

or

letter representing

the

opti

on

may

be

indicat

ed

on

the

display.

ANGLE MOOE SYMBOL l

IOEG, OAO, GRAD)

I>

.,.

I_

PROMPT SIGN

r

MOOE SYMBOL

(RUN.PRO, RESERVE)

. I RESERVE NO.

~

II,

11,

1111

..

. · 1

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The

prompt shown

in

(

I)

appears afteran operation such

as

battery replacement.

The

pocket computer needs to

be

reset

in

the following manner, when the prompt shown in (E)

aippears

on

the display.

I

CL

I

NEW

O IENTERI "NEW

O"

is the command to reset

all

pock

et

computer conditions

to

their initi

al

states.

Upon

completi

on

of

above operation, the

pr

ompt

sign

shown

in

(2)

is brought on the display.

Abo,

depressing the lONI key after turning

off

the power with the

lO

FFI key brings the same

prompt on the display.

However, involvement

of

a failure in a peripheral

will

put a check

message

such as "CHECK

6-

"

on

the display,

if

any peripheral is connected

to

the pocket computer.

• Auto power off

With

this pocket computer the power is automatically shut

off

to

save

power, unless a key

entry is made within

seve

n minutes after the last key entry.

Depression

of

the

ION

I key after automatic turn-off

turns

the power on to the pocket

computer, then the machine and display conditionsretu

rn

to

what they were imediately before

the power was shut

ofC.

(3) Specifications

Capacity:

Operating sequence:

Programming language:

Central processing unit:

Memory configuraton:

Powerconsumption:

Physical dimensions:

Weight:

Accessories:

(4) Options

10digits (mantessa) +2 digits (exponent)

Direct formula entry (furnished with priority determining function)

BASIC

CMO

S 8-bit microprocessor

ROM:

16KB

RAM

: 3.5KB

System area:

Jnput buffer area:

Stack area:

0.13W

0.9KB

80

bytes

196 bytes

I95(W) x

86(0)

x 25

.5

(H)mm

375g, including batteries

Soft

case

, two templates, four batteries (type AA), instmction manual,

applica

ti

ons man

ual

and name label.

• CE-150 color graphic printer (built-in cassette interface)

The

CE-ISO

is the 4-color graphic printer that incorporates the cassette interface unit.

As

ball

point pen type

of

stylus

is

used for printing, four varieties

of

colored pens (black, blue, green,

red) can be installed and controlled

by

the proaram to draw either a straight

or

broken

li

ne

from

any

desired

locati

on

by

the

co

lor

designated.

Co

mbinat

i

ons

of

co

l

ors

a

nd

lines

will

ena

b

le

th

e formation

or

colorful graphics and any desired figure.

The

CE-150

can

al

so be used to print

program lists and data outputs.

Two tape recorders may

be

connected

at

the same time with the CE-I

SO

, one can

be

used

for

recording and the other for data transfer. For instance, today's data can

be

summarized and

recorded

in

one tape recorder, while transferring the data

file

of

yesterday from

th

e other tape

r

eco

r

der.

• CE-151 memory module

The CE-

ISi

is

the RAM chip of 4KB used to expand the program and

da

ta storage

of

the

PC

-1500.

o

When

th

e CE

-1

51

is

mounted

in

the

PC

-1500, the capacity

of

program and data storage is

expanded

to

5946 bytes.

• CE-152 cassette

tape

recorder

The CE

-1

52 is the ca'sette tape recorder exclusively designed

for

use

with the pocket compute:r.

Storing previous prog

ra

m and. data

on

tape

usiJ

1g the

CE-

15

2 as theexternal memory device

of

thePC-I

SOO

wi

ll

enable you

to

use the data again.

2 Note tltat

it

needs the CE-I

SO

color graphic printer to use the CE-I S2 cassette tape recor

der

.

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2-1.

RAM

MAP

0000

USER

MEMORY

YO

2KB

USER

MEMORY

STANDARD

so

USER

MEMORY

OPTION

IOKB

PV

EXPAND

ROMO

16KB

SYSTEM

POGRAM

16KB

PV

EXPAND

ROMI

16KB

* : Inhibit

to

use

by

redundancy

SI

S2

YI

SS

S4

SS

S7

Y2

BFFF

c 0

Y8

FFF~'

2-2.

LSI

signal description

1.

LH

5801 (8-bit CMOS MPU)

4

1)

Outline

The

LH5801 is

the

8-bit microprocessor

of

the

CMOS

stat

ic

type, featuring very low power

dissipation and large data processing capability. The

MPU

incorporates functions such

as

the

LCD

·backplate signal generator,

input

port,

"external latch clock,

and

timer, which allows a

va

riety

of

:systems with a

few

chips.

2)

Feature•

of

MPU

o 8°bit parallel operations

o I28KB direct acces.,ing

o Implementation

of

6.byte general purpose register besides

the

accumulator allows

the

use

of

three data pointers.

o 9·bit timer function

o Three kinds

of

interrupts

Non-maskable interrupt

Maskable interrupt

Timer interrupt

o

In

struction.set

of

80

kinds

o

DMA

and multiprocessor capabilities

o

MPU

wait function (memory access control)

o Implementation

of

8·bit

input

port

and clock

Pl/>

for external latch

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o Memory backup function

o

LCD

back

plate controll

o Clock 2.6MHz (crystal control)

Internal machine cycle ...... J.3MHz

Mininum instruction excute time ...... I.3µS

2-3. MPU block d i

agram

Control signal

Backpla

,.

48

b;t)

•

"8

¥0

.,,

:.

c

g 0

·-

u

li

::>

,

...

~~

.=

Back

plate

driver

Address

contr

ol

Internal register

l

nterool

bus

A

I..

u

t t i

%

Vee

GNO

t:

lnput

port

0

0.

48

b;11

~

,

Q

.=

0 Data bus

-

~

48

bit)

c

0

u

-

,

CD

Table below shows t

he

internal registers

of

the

MPU

that consist

of8·bit

x

14

RAM storages.

P11

P1.

S11

SL

Wu

WL

A E

Uu

Ur.

...... Program counter

......

Stack

pointer

...... Wregister

...... A register, E register

...... U register

} iExclus

ive

registers

Yn

YL

...... Y register General purpose register

Xu

x,

. ...... X register

MPU

registers consists

of

two groups

of

registers; exclusive register group and general purpose

registergrou

p.

Exclusive registers consist

of

program counter (PH, PL) [16 bits) , stack pointer (SH, SL) [16

bits),

and Wregister

(WH,

WL)

(16 bits] .

General purpose registers consist

of

eight 8·bit registers; U register (UH, UL), X register (XH,

XL), and Y register(YH, YL) can be used

in

pair to comprise 16-bit registers. 6

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2-4.

description

IH

XLO,

XL1

Crystal

oscillator

ex

t

erna

l

con

n

ection

p

in

s

(XLO

:

Jn,

XL!

:

Ou

t:)

(2)

ADO

-

AD15

16 bits address bus

(ADO

: least si

gn

ificant address bil, ADI 5: most significant address bit).

Turnshigh impedance by the BRQ

si

gnal

.

131

D0-07

Bidirectional data bus used

to

write and read data to/from the external memory

(DO:

least

significant bit,

07:

most significant bit).

(4

) M

EO,

MEl

Memory enable signals

that

the

MPU

uses for direct acces

si

ng:

to

an external memory

of

which

the maximum capacity

is

128

KB

(64KB x

2)

.

(5)1

R/W

Read/write

signal

lhat tlie

MPU

use

to

perform reading operation when

R/W=

I and

writ~

operation when

R/W=O

.

,,.

0 s

ADI

x x x

L_/

MEO

I

~

MEI

'

DI

IN

OUT

Data

read

Data

w(ite

cycle

eye;

le

(6)

RES

ET

Ahigh input

of

this

sign

al causes the

MPU

to

return

to

its initial state.

(7) BRO

Bus

request. A high state

of

this signal causes the

MPU

to

respond with the hi

gh

state

of

the

BAK

signal

upon

comp

le

tion

of

present

command

execution.

(8)

BAK

6

Bus acknowledge appears

in

response with a high

BRQ

indicating that address bus, data bus,

R/W,

ME

O,

and MEI are

in

higl1

impedance.

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(9)

OPF

Operation code fetch appears when the

MPU

fetches

an

operation (instruction) code. OPF is

an

output only during the fetch

of

an instruction code and

is

not an

output

when address data,

immediate data,

or

the second byte

of

a two step instruction

is

fetched.

ADO-ADIS

MEO

OPF

Last Operation

Cycle fetch cyel.e

(10)

INO-

IN7

Input port. The

MP

U takes the signal

on

INO

-IN7 input port into the internal accumulator as

S·bit data.

(11) PU, PV, DIS

On

chip Oipfiops

of

which outputs arc

on

1.SI

pins.

PU: Set

to

high with the SPU instruction and set to low with the RPU ins'lruction.

PV: Set

to

high with the SPV instruction and set to low with the RPV instruction.

DIS: Set

to

high with the SOP instruction and set

to

low with the RDP instruction.

(12)

Pip

Strobe

output

is an

outpu

t during the execution

of

theATP instruction normally, used

for

the

external latch

of

the A register contents.

l13l

.pos

Clock which is

in

the same

pha<e

as

the basic clock inside the chip and it

is

the basic clock for

an

entire system.

It

becomes the basic clock

of

I.3MHz frequency when a 2

.6MH

z crystal is connected between

Xl.Oand

XLI

.

(14)

WAIT

(15)

(16)

(17)

WAIT

output

that informs the

MP

U

that

addressed memory

or

1/0 device

is

not

ready. The

MP

U is

in

the

wait state while this signal

is

on

.

HO-H7

LCD

backplate signal

VA,

VB,

VM, VDIS

LCD

drive source.

HIN

LCD backplate signal. Counter input that g.enerates

HO

-H7. Normally connected

to

HA.

(18)

HA

MP

Udivider output.

119)

BFO, BFI

MP

U

int

ernal register

BF

flipOop output (BFO) and input(BFI) can be reset

by

the instruction

from the MPU and set by the

BFI

input. Normally used for the memory backupsystem. 7

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(20)

NM

I

Non·maskable interrupt. A high NMI signal denotes an inte

rrupt

request,

to

which

the

MPU

responds unconditionally and

the

control

mows

to

start

the

interrupt

pro~ssing

rout.inc

after

the

cont

ents

of

th

e memory address

FFFC

is moved into

the

high

order

byte

of

the

program

counte

r and the

contents

of

the

memory address

FFFD

into

the

low order

byte

of

th

e program

co

unter

.

(21) Ml

Maskable int

errupt.

A

hi

gh

on

this signal makes interrupt request when

interrupt

enable is

set.

The

MP

U responds uncond.

it

ionally

to th

is request. Cont

ro

l moves

to

start

th

e Interrupt

pr~ssing

routine after

the

con

tents

of

the

memory address

FFF8

is mo,·ed

into

the high order

byte

of

the program

counter,

the

contents

of

the

memory address FF

F9

are moved i

nto

the

lo

w

order

byte

of

the program

counter

.

(221

OD

011tp11t

diS<lble.

Wh

en

the OD

~ign

al

i$

act

ive

th

e

data

bus

is

in

the

outpu

t mode.

"'

...

"'

N 0

---

"'

00

0

t-.

(I)

lO

~

CO

CN

- 0

Q Q Q

~

Q Q Q Q z Q Q Q

C<

Q Q Q Q

< < <

<(

< < < 0 < < < < < < < <

57 56 55 54 58

52

51

50

49

48

47 46 45

44

43

42

41

40

39

R/W

58 38

D7

P/6 59 87

D6

PV

60

86

D5

PU

61

85 04

f!

os

62

84

08

Xi,0

63

83

02

XI,

I

64

82

I)

I

WAIT

65

SI

DO

IN7

66

30

ME

I

INS

67

LH5

801

29

M

EO

INS

68

28

OD

IN4

69

27

HO

I

N3

10

26

111

I

N2

71

25

11

2

IN I

72

24

118

INO

73

28

H4

74

22

HS

75

0

21

H6

76

20

H7

2 3 4 5 6 7 8 9 10

11

12 IS

14

15

16

17

18 19

I-

Q -

w a

~

0

...

:.:

v

::e

Q <

'°

::;

-

17-

<:

VJ

U> <

"'

...

< v --- -

w

O'.l O'.l

'°

0

O'.l

> > > > > z

~:I:'""'O

"'

8

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3.

LH5811

1/0

PORT

(1

I

Out

li

ne

The LH58 I

:t

l/0

port

is

the single chip I.SI of

CMOS

static circuit that can

be

connected with a

general purpose 8°

bit

CPU

.

It

has the

foUowiJlg

functions:

(I)

Two paors

of

8

-bi

t bidirectional ports

(2) One pair

of

&.

bit

output ports

(3) Two lines

of

interrupt request inputs,

one

of

them

is

the input from

por"t.

(4) One line

of

interrupt request output.

(

5)

CPU

wait control

(

6)

Serial control

(2) Fun

ct

ions

(I

) Ports,

PAO

-PA7 and

PBO

-PB7, can

be

programmed for l

/0

directions by each bit.

The CPU can access

PAO

-

PA

7 and

PBO

-

PB7

as though one location

of

memory.

(2)

!'CO

-

PC7

is

the port

of

011

t

p11t

type.

The

CPU

can

acces

s

it

as

though

one

loca

t

ion

of

memory.

Also, the latch clock

P.p

to

the

PC

port can

be

supplied directly from

an

external sou

rc

e.

(3) LH58

ll

incorporates two interrupt request inputs, 1RQ and PB7, when apply interrupt

request to the CPU at the rising edge

of

the input when the corresponding bit

of

the internal

mask register is

"l

". Signal PB7 represents the

8th

bit

of

the portPBand it needs to be

in

the

in

put

mode when the interrupt input

is

applied.

(4) The LH5811 has a CPU wait control circuit which uses two output lines

of

memory enable

signals for a memory that

ha

s slower access time. Jn addition, two input lines for the wait

conditions are used. Six different

of

access times can be chosen by programming.

(5)

TI1e

following functions are provided

for

serial control.

A. Serial data transmission

Serial data transmission

is

used

in

th.e format

of

start bit/8-bit data/2 stopbits.

Transmission clock

is

programmable by changing internal and external clocks, as well as

cha11ging

the clock rate; 1/1, 1/2, 1

/128,

1

/256,

1/512, 1/1024, 1/2048, l/4096

of

the

basic clock.

B.

Seri.

al

data

re

ception

When a start bit

is

received

in

t

he

i.dle

state, 8 bits

of

data

is

received, and stored

in

the

internal register and the interrupt request

Oag

is

set

on.

Reception clock

is

sent from the external clock and must be synchronized with the

se

rial

data

input.

C.

LC

D drivercontrol

T

he

LCD

driver is connected with three signal lines

of

the transmission clock,a serial data

bus, and asynchronous signal line to carry

out

data trans

fer

fo

r

chip

select,

addressing,

and data read/write.

For

the transmission clock in this

case

, the clock

ra

te can

be

programmed in the same

mann

er as in the serial

data

transmission clock. (Transmission clock to the

LCD

driver

is

I

MHz

.)

D. Pul.e waveform

Th

e pul

se

waveform can be sentout

in

continuation.

Eigh

t sorts

of

frequencies arc

programmable; 1/1, 1

/2

, 1/ 128, 1

/2

56, 1/512, 1/1024, and 1/4096 Qf the basic clock.

E.

Tr3J1smiss

ion to audio casse

tt

e tape recorder

The

modulated signal can be

se

nt from the

SDO

output

in

the

fo

:miat

of

start bit/8-bit

data/2 stop b

ih.

Modulation clocks, FX and FY, can

be

set separately to any

of

clock rate;

l/64,

l/128

,

1

/256

, 1

/512

,and

l/1024oftheba

s

ic

cl

ock.

9

Do

notsale this PDF

!!!

0

::J

0

-

(J)

Ql

CD

-::r

iii'

-0

0

"T1

-

0

I

NT

IRQ

...s CLO

LC

5

00

CL

l

50

1 W

AI

T DME I

r-----,----

--1---1---

'fr-

-

-r

-

-z-i--------

--

-

--r--

-

Vee

l+

I

VsSJ

...

vsst

j-+

0

Interrup

t

control

M

SK

r9;ister

}

][

OPA

r

ev

lner

OUTPUT

control

!,,_

I""

h

{f"

~

t I +

D

erider

&.

cl

ock

con

trol

G

r

eg

ister

{~

1--'

h

DATA

BUS

co

nt

ro

1

F

regist

er

~

h

I

Stri

.i

tr1nsm

l

sslon

con

t

rol

w

~

Sorlll

receMr

control

~

W

AIT

control

~WW-U~I

I ,II ft l 1

1H

f-i

Chip

regist

er

i.ete

ct

control

~

H

OAA

rt19lator

l'

Br

l

j.l

OPB

rtQis.ter

II

O

UT

PUT

control

r1

l

l+-i

008

j+l

re

g

iste

r

o~

DATA

BUS

register control

I

L

__

_v

_________

-~

L

JJ.

____

____'!l

__

~

__ I

_

<l..,

_ - - - -

_J

V

SS

I

=VSS2=GNJ>

VCC

• 4,5

:!:

0.S

I'

PA0-7

PB0-7

PC0-

7

1/0 PORT

controll

er system

block

d

lt

gr

11m

I'•

D0-7

)>

Q)

WI

:>

a.

WO

3

DM

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~

Q)

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0

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-

KEO

UJ

::r

Q)

IVll' ,

"O

RSO

-u

()

RS

I '

~

R

S2

<.n

RS3

0

cso 0

Q)

CS I -

m ::r

-

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:::::

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-u

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and more abo

ut

Sharp PC-1500

at

http://www.PC-1500.info

1

/0

po

rt

(LH5810)

Pin Signal In/out Connection Functional description

No. Name

I PAI Inf

out

Key Port A input/output. Key strobe.

? l ( ( ?

7 PA7 I

n/out

K

ey

Port A input/

output.

Key

strobe.

8

GN

O In Power

OV

9

PBO

In/out Option

Port

B input

/ou

tput

IO

OB

I In

/out

Option

Port

B input

/out

put

11

PB

2 In C

MTIN

Port B input(output. Cassette tape data inpu

t.

I2

P83

In GND Domestic/export specific

ation

select pin

(domesti

c)

vcc

(Export)

13

PB4

In GNO

Us

erarea detennination pin

14

PB5

In µPDl990C Clock input from TP terminal

of

the timer IC

15

P86

In

µPDI990C Data input from the DATA

Otrr

terminal

of

the

timer IC

16

PB7

In Key

BR

E

AK

keyinput (interrupt input)

17

p~

In GND

PC

port

latch clock input

18

PCO

Out µPD l990C Data ou

tput

to

the DATA IN terminal to the timer

IC

19

PC

! Out µPDl990C Strobe

output

to

the

ST

B tenminal

of

the

timer

IC

20

PC2

Out µP

Ol9

90C Cl

oc

k o

utput

to the LKtenminal

of

the timer

IC

21

PC3

Out µPD1990C Timer IC

con

trol signal

outp

ut

22

PC4

Out µPOI990C Timer ICcontrol

signal

out

pu

t

23

PC

S Out µP01990C Timer ICcontrolsignal

out

pu

t

.

24

PC6

Out B

uzur

25

PC7

26

cso

In

CPU

Chipselectinput connected

to

ADl2

27 CSI In

CPU

Chip select input conn

ec

ted

to

A013

28 CS2 In Decoder IC Chip select in

put

connected

to

Y3

of

the chip

' sele

ct

decoder IC

11

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at

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1/0

port

{LH5810

)

Signal

In/out Connection Functional de

scri

ption

N

o.

N

ame

29

RSO

In

CPU

Internal register and operation

se

lect

signal

? ? ? i

~

32

RS3

In

CPU

Internal register and operation

se

lect

signal

33

R/W

In

CPU

Read/write input

34

ME

O In

CPU

Memory enable and

1/

0 port controller enable

35

MEI

In

CPU

Memory

ena

b

le

36

WO In Option

Wait

condition

inp

ut

37

WI

In Option Wait

co

ndition

in

put

38

GND

In Power

OV

39

V

CC

In Power +

SV

40

DM

EO

Ou

t

RO

M, option R

OM

e

na

ble

41

DM

EI

Out Decoder

ROM

enable

42

WA

IT

Out C

PU

Wait

$i

gn

al to the

CPU

43

IN

T

Ou

t CPU Interrupt

re

q

uest

to

the

CPU

44

RE

SF.T

In

RESE

T

Ini

ti

al

rest

signal

circuit

45 IRQ In Option Interrupt re

qu

est i

np

ut

46

</>OS

In

CPU

B

asic

clock in

pu

t

47

CLI

CLO

Not used. Serial

da

ta

r

ece

ptionclock input

48

SDI

(VCC)

No

t used. Serial data reception input

49

LC

NC

Not used.

LC

Dd

ri

ver synchronizing

signal

50

CLO

lo CLl

Serial

data transmission/reception clock

51

SDO

In

CMT

Serial

transmission/reception data.

cassette tape data output.

Use

for the

52

DO

In/out

CPU

Data bus

> ? ? ? ?

59

D7

In/out

CPU

Data bus

60

PAO

Out Key P

or

t Ainput/output. Used

as

the

key

strobe.

12

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Read/write timings for

1/0

port

Yl'Al1'

*

__

_

D0

-7

-----<====>-

(a)

Data read from

1/0

port

MREQ'i: _

_,

R1w-----.

~---~

WAIT

*--

~

vo-1

--

c=======>

-

(b) Data wire

to

1/0

port

Do

notsale this PDF

!!!

NOTE:

Clock

q,

is furnished

to

the

¢OS input

of

the I/O port.

MREQ• is

an

inversion

of

MREQ

of

Z-80

and

furnished

to

the

MEO

of

the I/O port.

WAIT•

is an inversion

of

WAIT

of

the

I/0

port

and

furnished

to

the

WAIT

input

of

Z-80.

13

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at

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4.

CIRCUIT

DESCRIPTION

1

4-1

..

Chip

Select

Circuit

c

p

u

I/o

p

0 DM£1

DllEO

R

T

ME

O

MEI

ADS

TC40Hl89F

TC

40Hl

·

38F

VGG

so

To

RAMS

(

TC55

1?

AF)

S I

52

Tu

MOOJle

Un

il

sa

S7

Y4

Y5

Vss

n

SG

vee

WEX

Th

1/

0 Port

V2

To Oi

Sp

lay chip

1.3

L......

f---Q=va

To

Dis

play <;l1ip2.4

'-

-

--

- -

--

-+

To RAllj,

2(

T

C,:~~14r)

'-

--

---

-

----

- -

----

-

-+

To

VO

PORT(LH5810)

'--+To

R0ll(CS6

13 1

28

F)

'-

--

-

---

----

---

- -

--

-•To

MOOu

l

lh

i t

'--

--

-

---

-

----

- -

-----+To

Mcdvl

lhit

tt

.t

ou

1i

• Internal logic

Truth

Table

VO

A

In

put

EN

A

.BL!

Sl>L1$CT

Output

Vi

••

•1£8

A • c

~

2'.1

Y!

VJ

...

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..

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H

II

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Y2

• "

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( · 0

<:>

II

II II II

"

II

"

...

..

" (,;-

Ii:.

~

II

II II

H

II II II II

Vi

II

L L L L L I. " " H

II

c

Yi

II

L L

II

L L

II

L

II II

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II

L

I.

L " L " " L H H " "

II

{CIA

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Gt

ll

C l

VJ

" L L " H L

!I

II

" L " " "

II

" L L I. L H

II

"

II

H L H H H

H L L

II

L

II II II

"

II

L

II

H

" L L L H

II

H

II II

H L H

II

L L

II

H H H

II

H H "

II

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not

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!!!

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0

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ll

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at

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Truth Table

Input

Er.ISLE

SELECT

Output

G A B

YO

Yf

Y2

YT

YO

Yi

H * * H H H H

L L L L H H H

Y2

L H L H L H H

L L H H H L H

L H H H H H L

Y3

l*=

Irrelevant

--

• Selection

of

I

YO

- I

Y3

by the decoder

IC

(TC40Hl39H)

is

done when

the

gate signal (GI) input

BFO

is

low_

YO

With

low

state

of

AD

14

and

AD

IS.

the

YO

output

becomes

low

to

select

the

system

(!

YO)

ROM area

of

the module unit.

(0000-

3FFF

address setup)

YI With high state

of

ADl4

and

low

st

ate

of

ADl5,

the

YI

output becomes low to select

(IYI)

the gate (G2A)

of

the

IC

(TC40HB8F).

(4000-

7FFF

address setup)

Y2 With low state

of

AD14 and high state

of

AD15, the Y2 output becomes low to select

(IY2)

the

expansion

ROM

area

of

the module unlt.

(8000-

BFFFaddress setup)

Y3 With high state

of

AD14 and AD15, the

Y3

output becomes low

to

select the system

(IY

3) program

ROM

(CS-613128F) and the

1/0

port (LH5811).

(COOO

-FFFF address

setup)

• Selection

of

SO

-S7

by

the decoder

IC

(TC40Hl38F) is done when t

he

gate signal input

MEO

(GI)

is

high,

YI

(G2)

low,

and

G2B

is

low

{which

is

normally

low)

.

SO

With

all

of

AD

II,

AD

12, and

AD

B

in

low state,

SO

goes

to

thelow state and selects the

(YO)

RAM3 (TC5517AF).

(4000-47FF

address setup)

SI

With high state

of

ADI I and low· state

of

AD12 and AD13,

SI

goes to the low state to

(Y

I) select the option user

RAM

area.

(4800-49FF

address setup)

S2 With low state

of

AD

11

and

high

state

of

AD

12 and l

ow

state

of

AD13,S2goes

to

the

(Y2) low state to select the option

RAM

area. (5000-57FF address se·tup)

S3 Wi

th

high state

of

ADii

and

ADl2

and

low state

of

ADl3, S3 goes to the low state

to

(Y3) select the option user

RAM

area.

(6000-

67FF address setup)

S6 With low state

of

AD

11

and high state

of

AD

12

and

AD

13, S6goes to the l

ow

state

to

(Y6) receive the interrupt input from an option into the

1{

0

part

. (

1000

-77FF address

setup)

S7 With all

of

AD11,

AD

12, and

AD

13

in

hi

gh

state,S7 goes to the low state to select the

(Y7) system memory

RAMI

and 2 ('TC5514P). (7800 -7FPF addres setup) RA

M!

and

RAM2 are 4·bit

RAMs

, independently used to assume low order and high orderbits

to

comprise one byte with a pair

of

4 bitseach.

• Selection

of

2Y2 and 2Y3 by the decoder

IC

(TC40Hl~is

done when the gate

C>f2G

becomes

active with the selection

of

the TC40H

J38F

output, S6 (Y6).

2Y2 With low state

of

ADS

and high state

of

DMEO,

t

he

2Y2 output goes to the low state so

(V2)

tha

t the

NAND

gate output V2 is turned hlgh to select the display chip I and 3.

2Y3 With high state

of

AD8

and

DMEO

.•the 2Y3 output

go

es to the· low state so that the

(V3) NANO gate out V3 is turned high to select the display chip 2 and

4.

• Display chip (SC882G) is a 4·bit

RAM,

comprised

of

one byte

of

data

wit1

14 low order bitsand

4 high order bits of data, so that even the chip

sel

ect signals are used

in

pair

of

chip I withchip 3

and chip 2 with chip 4.

15

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1500 at http://www.PC-1500.info

2) Buzzer cir

cu

it

CJ.IT

OUT

10

I

SDO

1

\6

PC6

l:-,-.

--

~<1-

-...21

9

L..)

p 4

O

PB2~

1

~

1

--+--k1-__.

R

T

CMT

IN

Vee

BUZZER

a O

tt---.

The control signal CMT OUT

is

setnt out from thepin

SDO

of

lhe

1/0

portwich sounds the buzzer

in oombination with the low state

of

either the programmed output from the

1/0

port or CMT

IN

sent from the cassette tape deck.

3)

RAM

R/W signal circuit

R/W

RAJ.II

R/W

•

CPU

1-AD~l~O:.._l>l--_....,/W

:__,-

F:..:.:..--f:>t---t

6.6KO TC5614PX2

pcs

4)

ON key double action preventive

circuit

16

Vee

OAP

202

560KO

BF

I -

-W"l'-_.

-

+-"-1

5

~

4

C........._

-

.Q

I

/0

PORT

SFI

--""

TC50HOOI

~""'-asr~·~39PF

...-----~

PS7

---'

P87

This

cir

cuit prevents writing if

ADIO

is

in

high

state during the

write mode (when

R/W

is

low).

This is

to

prevent wrong operation

when a specific key,

[!]

or

[I]

is

pushed without performing "NEW

0 ENTER" after battery replace-

ment.

This cir

cu

it consists

of

the Schmitt

circuit that prevents the possibility

of

setting the input flag

of

the

LH5B

11

1/0

porl

which

d e

pend~

on

how the

ON

key

is

pushed.

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5) Timer/cou

nter

circuit

-

....

0

...,

0

"'

'"l

r

=

(ft

""

-

No

.

I

2

3

4

5

P

CS

C2

PC4

Cl

PC3

CO

PC1

t--

-

-+

-1

STB

Reset

ILSBI

"

...,

0

-

.,

0

>

(")

Yoo

XTALI-----~

~ITt

---

....J

l

rJ

s2.

1

ssKHz

liTAL

0

~

:!::

1.

Ou~lino

>--~

"[__J

As

shown in the left,

,;.

the µPD!990AC is used

for

the

time keeping

IC

to

co

un

t hour/minu

te/

secondfmonth/day.

2. M

ain

fu

n

ct

ion

of

µPD

1990AC

Time data

is

in the

BCD

form

and i;;judged

by means

of

compari-

so

n. However,

day

of

week is

not

used with

this chip and hour

is

represented by 24·hour

system.

IMSBI

DIN

9 4 3 2 2 5 2 B

--

Seco

nd$ Minutes

Hours

Day

Week

Monti\

4 4 I 4

Bits Bits 4 I 4

Bits

4 4

Bits Bits Bits

Signal

In/out

Description

na

me

C2

In

Mode sele

ct

signal C2=0

Ci

In

Mode select signal Cl

co

Mode

Da

ta

In/out mode

co

In

Mode select signal 0 0 0 Resister hold

0 1 I Registered shirt

I 0 2 Time set

I 1 3

Time

re

ad

STB In Strobe. Command

is

latched by the strobeSTB.

cs

In Chip select: disables

CLK

and STB input and DATA OUT

outpu

t by

the CS input. All input/output are invalid unless CS

is

high.

STB

"\_

J Internal STB (commandlatch clock)

cs

./

~

CLK

] ) Internal

CLK

(40-bit

se

rial clock)

] "\_ Internal OE (gate input

of

DAT OUT)

OE

../ 17

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6 DATA IN

In

Data input signal (40-bit serial data)

7

CND

In

ov

8 CLK Jn 40-lbit shift register clock (Data

input/output

is

carried

out

in

synchronization with CLK.

9

DA

TA

Out

Data

output

signal (40-bit serial

data)

OUT

10 TP Out

Timer

pulse output: to

CO,

CI,

C2

during command assignment.

11

OUT

In

Output

enable: input to control the

output

of

DATA OUT.

ENABLE

12 XTAL

In

Basic clock,32.768KHz

13 XTAL

In

Same

the

above

14 YDD In Source power input, connected to

VGG

(4.7V).

6)

Power supply

circuit

The

power supply

is

lllCOrporated in 3 Single resin molded IC

that

consists

of

the s

tab

ilizer circuit,

temperature compensation circuit, and bleeder circuit.

18

VBATU----,

HI-MIC

18

r

i>t-+-14"°"1'""""2'SB7_Jc0,.__--:2:.:;:SB77.9~-~~~~f-<o------O

' ' Vee

ADAPTER

Jack

I

SS98

-

-:"UM

-8

X4

2SCl628

9

SFO

7

6

VR

8

--

-ovA

3

2

Vi.r

+---OVs

'--<>-

.....

----

-1--------<>--+

----

-.--------+--6

..J

.._...._

____

--OVotsP

5

2S

J84

4

GNO

Supply voltage: I.SY x 4 =

7Y

±0.05V

VCG:

4.7V

VCC:

4.

7V

!0

.02V

VDISP: 3.7V ±0.0IY

(In

the

case

of

2S°C)

Do

not

sale this PDF

!!!

Sharp PC-1500 User manual

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