Sharp PC-1500 Product manual

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FOREWORD
S in ce the release of the P C-15 00 on market. we have had great
rnnnbcr ofq ues ti on sfr om use rs rega rd ing the ma c hin elan guage
of t he PC -I 51X l.
To meet with such d ema nd from ardent users, we arc no w
sending
th is text fors tud y of the ma chine language of the Sha rp's
or iginal design L!-1 5801 Microprocess or and LH5 81I Pe ripheral
Contro l LSI in concern with the PC- 1500 syst em . Be caus e the
text is edited
on the basis of user questions. it may not sup po 11
qua lit y as a gu ideboo k. In such an event. you are suggested to
make reference to mi
cro processor gu id ebooks published on
mark et. in addition to this text.
Vo ur opinions an d questions ar e welcome through ou r products
distributor.
No ·rE: Machine l an guage r rog ra1n, \Vhic Q1 c on l f( )IS hard\van: dir CC L}y,
gi ves )'( ) \J 11 l ( )f C va ri () lf S functions than ll ASI( ~ pro gr ar ns. 1-Jo,ve vc r. y ou
s ho uld ch ec k y ou r 111 (lc hinc langu ag<.: pr <1g ra n1 <.: nough to rnakc n<> crr c.>r
be for e executing it b c<.< lu sc single 'vr ong ike y operation rn a. y u pse t the
pr ogra 1n or occas io na ll y rnakc the rna chi ru :: break dO\\' rl.
Sharp C'o rpora 1i on a ss u mes no l ia b il i 1y or responsibili1y or any kind
a ris in g from t he u se of pro g ra ms or pr o gra m m at er ia ls or any pan
1here of.
SPECIAL NOT ICE TO PC-1500A CUSTOMERS
Be cause rhc P( : .. 1 500/'. \ provi des rn o1·c R/\ M th an the PC -1 500 .son1cof the
d csc 1·ip 1io ns of t he CHIP SELECTSI GJ\AL. MEMO RY MA I '. a nd 40 ·
Pl)';
CO NNEc ·r o R (for 111 c nH>r y 1no du l cs) require 1n odil ic atio 1l S10 suit
t he PC-I SOOA.
1\ SlU1 1rnar y of 1he di ffe ren ces bet \\· ce n the P( '. J500A and th l' pc._· 1500 is
gi ven in the <:td <lc ndurn on the p ag.;. · 16J.
·rake notice of these differ<. ·nces \\•hen u:-. i ll!; nlachinc la.og ua gc .
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CONTENTS
1. Mac hine Language .. . . •. ... .. .. .. ... .•.. . . .. . .. . . .. . . .. . .. . . ..•. .. . ••••. •.•.. ..•.•.•. 1
2. LH 5801 Microprocessor . .. . .. . .......... . .. . .. .. : .. . . .. . .. . . .. . . .. . .. .. .. .. ... .. .•.. . 5
2·1. Outline of LH5801 . . . . . . . . . . . . . . • . . . . . . . . . . . . •. . . • . . . . •. . . . . . . . . . • . . . •. . . . . . . . • . . 6
2-2.
Internal structu re . .. . .•.. .. .. .. ••. ..• •. .••. ..•. ..•.. .. •. .. •. .. •. •••. ••. .. •. •.. •. . 7
2-2· 1. Block diagram.. .. . .. . .. .•. .. , •. .• , .. ... .. .. ... .... .. . . •.• •. .••. . .. ••.. •. . 7
2-2-2. Internal registers .... • .. .. . .. , ...... .. . . .. .. ... . . .. .. .. . .. ,. .. .•.. ... .. •. . 8
2·2·3. St at us fl ags . .. . . .. . .. . . .•... .. .. . •..•.. . .•. .. ... .. .. .. . . •. .. ... .. . •. .. .. . 8
2· 2·4. CPU pin descri pt i on .. . . .•..•.•.•••.. .•. .. •. .. •. ...•. .. . .. .. .. .. ..•. .. . .. . 9
2·3. Functions . .. . . .. . .. . . .. . .•.. .. ••. .• .. .. ••... •. .. •. ... . .. .. . .. . . •••. •.. ..• •. .. . •. 14
2-3-1.
2-
3-2 .
2-3-
3.
Timer .. .. .. ... .•...•. .. •• . .. •. . .•. . ..•. .. •. .. .. ... . . . . • . .•...•. .. ........ 14
Interrupts .. . .. . . .. . . .. . .. . .. . .. . •. ..• . .. •• .... .. .. •. ..• .• . .. .. .. .•. ..•.. . 17
Resel .. . . .. •.•.. .. .. ... .. .••. .. •. . ..•. .. ••. ..•.. .. •. . . . .•. ...•. ..•. .. . .. . 20
2-3- 4. CPU system sequence .. . . .. . . .. . .. . .. . . .. •. .. .. .. •••. •. . . .•.•. •. . .. •.•.•. 21
2- 3-5. BF fli pflop .. . . .. . . .. . .. . . .. ... .. .. .. ... .. .. .. ... .. .. .. . . .. .. ... .. ... .. .. . 22
2-3-6 . WAIT funct i on .. . .. ... .......... . .. . .................. . . . .. . .... .......... 23
2-4. LH5801 i nstructions . .. . . . ........................ .. . ......... .... ................ 24
2-4 · 1. Outline .. . .. . . .. •.•.•.. . . .. . . .. . .. . . .. . .. •.. . ••. . •••.. . .. .. .• .. . . .. •.•.• . 24
2-4-2.
Add . subtract, and loglcal Ins tructions .. . . .•. ..•.. . .. . .. •. .. .. . .. .. . .. . . .. . 25
2-4-3.
Compare and bit test . .. ... . . ..... . .. ..... .. . .. . . .. .. ... .... .. ,. . . . .. .. . . . 31
2-4-4 . Transfer and search instructions .. . .. . . .. . •...•.. .. •. .. . .• •. .•.. ..••... .. . 33
2-4-5. Block transfer and search Instructions .. . . .. . .. •. .. ..•.. •. ••.. .. ... •. . . .. •. 38
2·4· 6. Rotate and shift instrucllons .. . . .. . .. . . .. .. ...•. ..•.•.. .. ••..•. . .. . . .. . .•. 39
2·4·7. CPU control instruction s. •.•,. , .,,. ,. , . .. .. .... ... -.- .. .. ••.. •. ...•. .. ... . 42
2-4-8. Jump in struction s . .. . . .. . .. . . .. . ••..•. .. •. .. .. .. . . •. .. .. •. .. .. .. .•. ... . .. 45
2-4-9. Subroutine jump i nstru ctions .... .. •..•. ..•. . .. •. . .. .. . . ..•. .. ••. .. •. ... .. . 49
2-4-10. Return in structions .. . .•.•.. .. .. .••..•. .. . .. . .•. .. .. •. . ..•.•.•.. . .•. ..•.•. 53
2·5. Comm and list ..... .. . .•.•......•..... . .• .. . .. _. ___ .. •. __. • ... ... .. .•. .....•...•. 54
2·6. Elec lr ic al characteristics and timings _ .. .. _. _. _ .... __ ........ __ . _ .... ........... __ 63
3. LH5810/LH5811
1/ 0 port controller ... . •....•.• . .... .•.•........ . . .......... . ...... . .. 67
3-1. Outline .. .... . ... .. •.. .. .. . ...• . •.•.....••..•• . ..•. .... . ... . . .• . .. . .•• •..•.•.. . .. 68
3·2. Functions . . . .. .. . .. . . .. .. . .. . . •. .. ••. .. .. ... •. . . •. . .. .. . .•. . . . .. •. . . .. .. . .. .. .. . 68
3-3. Inf ernal structure .. . .. . . .. . . .. .•. ..•. .. . •. .. .. .. . •. ... .. . .. . .. .. •••. .. •. .. •. .. .. . 70
3-3-1. Bl ock diagram ....... .. .•. . .• ... ., . .. .. .. .. .. .. .. . . .. . .. .. . ... . ... .,. .. . . . 70
3-3-2. Internal registers .. .. ... .. ..•. .. •.. ..• •. .. . . .. .. .. .•. .. .. ... .. .. .. ..•.•.. . 70
3-3-3. Pin descripli on . ....... . .•..... .• . ....... •. . .. •. . .. ,•.. .. , ... , .... , . .. •.. . 73
3-4. Functions . ..... ....... . .. , ... . .. . . .... •. _ .. •. . . _ .... •• .. • ...... •• _. _ •. .. , . .. . .. . 74
3-4· 1. Operation .... . . ...... .. •. . .•. .. ••. .. .. .. .• ... . . . . . • .. . .. . . .. . • . .. • • .. . ... 74
3-4-2. Wait control .. . .. . . .. . ..•. .. •. ..•• •. •• . .. ••. .. •. . . .. . .. .. •.. ..•. .. •• ... .. . 75
3-4-3. Serial data i npuL .. .. ...•. ..•. ... •. ..•. .. .. .... . ... .. .. ... . .. .. . ... .. .. .. . 76
3-4·4. Reset ...... ..................... .. .. . .. . . __ .. • .. .• .•.. .. . . .. •• •..•. •. •. •. 77
3-5. Specification __ . _. __ .. .... .......... . .. _. _. _ .... ___ .... _____ .. .. . .. . . .. . . .. . .. . . . 78
3-5 -1. 1/0 port controller inpul/output circuits.................... .. . ....... . . .. . . 78
3-5-2. Pad la yout and struc ture .. . .... .. . ...... .... ... ... . .. . . . .. . . .. •. ...• •. . .. . 79
3-5-3. Electrical characteristics .•.••. . . .••. .••. .
.. . .. •. .. •. •. . ..•.•.•.. . . .. ..•.. . 79
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4. PC- 15 00 ha rd ware descr i ption .. . .. . .
....... . ... .. ... .. . . .. .. . ... . .. . ... ..... .. . 85
4- 1. PC-1500 sys te m conf igura ti on .. .. .. • .. .. .. .. . .... .. . . .. •. .. ... ..•. .. .. .. . ... . .. . 86
4-1-
1. Ou tl ine . .. .. .. .. . .. .. .. .. .. . . . .. .. .. . .. .. .. .. .. . .. .. .. .. . .. .. • .... .... . .. 86
4-1-2. Bl oc k di ag ram. .. .. . ..... .. .. . . . . ...... ... .. . .. ...... . .. . .. . ... .... ... . .. 87
4-1-3. Power supplies (
PC -1500. CE-150, CE-158, CE-159) . ... . ... •. .. •. .. •. • .... . 87
4-2 . PC-150 0.. . .... .. .. . .. ........ . .. .. . . .. .. . .. .. .. .. . . . .. .. . •. .. •. ..•. ••. .. . 89
4- 2·1. Outline .. .. ... .. .. . ..... . ·
·· ······· ···· ····· ···· · · · · · · · · · · · - · · ·· · 89
4-2-2. Block di agram .. . .... .. .. .. .. - . . .. . . .. .•. ..•. .. .•. . .••... .. .. .• .. ••. . . . . .. 90
4-2-3. Chip sele ct cir cuit . .. . . .. . .. . - . . .. • •... •. . . .•... .. .. •. ..•.. . . .•..• •. . . .. .. 91
4-2-4. PC-1500 system m emor y map _... ... .. .. . .. .. .. . .... . . .. . ... . .. . . .. .. .. . .. 94
4-3.
Connector signal s/ LSI signals . .... .. - ... . • .. .. • .. ..• .. ••. .. .... .. . ..... .• .. .. .. .. 102
4-3-1. 40 -pin co nnect or .. . .. . . .. .. . ... ..... .. . . .. . ...... . .. . .. .. .. .. . .. . . .... . . 102
4-3-2. 60-pin co nnector . ... . .. . .. .... .. . . . .. . . .. . ... .. .. . .. . ... .. .. . . . .. . .. . ... . 103
4-3-3. LH 580 1 Mi cro processor. .. ... • ... ••. .. .• .. ... .. • .. .•. ... .. .... .. . . . .. .. ... 104
4-3-4. 1/0 PC .. . . .. ........ . .. .. ... ... .. . .. ... . .. . ... . ... .. .. .. . .. .. ...... . .... . 105
4-4. Key m at rix and key code chart
.. .. .. . ... ... ..... .. . .. .. . . .. .. . ...... . ... ..... . 109
5. PC -1500 soft ware .. .. .. . . .. . .. . . .. . . . .. .. .. . ... . .. .. . . .
.. .. . . .. .. .... ...... .. .. . .. . 1 11
5-1. BASIC com mand related PC-1500 mac h ine la ng uage .... . ... .• .... •. .. . . . .. . . .. . 112
5-1-1. NEW.
.. .. . ... .. . .. .. .. . . . ... ... .... . .. .. .. ... .. .. .. . .. . . .. . ... .. ..... .. . . 11 2
5-1-2. STATUS . .. .. .. .. . . . .. . .. .. . . ...... .. . .. .. .. . .. .. .. .. . . .. .... .. . .. . .. ... . 112
5-1-3. PEEK .. .... .. .. ... .. . . .. . . .. . .. . ... .. .. .. . ... .. .. ..
.... .. . .. ... .. ... .. .. 113
5-
1- 4. POKE ... .. .. ...... .. .. ...... .. .. . .. .. . ... . .. .. ..
. . .. .. .. . .. .. .. .. • .. .. .. 113
5-1- 5. CA LL. . ... . .. ... I • • •• • • • ' ' • ' • ' • ' ' ' •• ' ' ' • ' • ' • • •••
5- 1-6. CS AVE M ..... .. . . .. ..... .. . _. . .. . .. •. .•. .. .• . .. . •. .. ••. .. • ... .. . .. .. .
5-
1-7 . CLOAD M .. ..... . .... . ... .
·· ················ ·· ······················
114
11 4
114
5-:2. I
nt e rn al c od e ch art . .. . .. .. .. .. .. . .. .. . .. .. . .. .. • .... .. .. .. .. . .. .. •. .. •. . .. • . .. 115
5-3. Expressi
on of v ar iable and pr ogram . .. . ...... .. . . .. .. .. .. . ....... .. . .. .. . . .. . . .. 116
5-3-1. Expression
of de ci mal numb er . .. . . . .. . ... . .. .... .. . .. . . .. .... . . .. .. . .. .. . 116
5- 3-2. Exp ression of binary nu mber . . .. . . .... . .. ... .. . .. .. .... ... ..... .. . .. . .. . 116
5- 3- 3. Expressi on of ch aract er str ing . . .... . .. .. . . .. .. .. . . .. .. .... .... .... .. .. .. . . 116
5-3-
4. Structure of varia bl e name ...... .. . .. . .... .. . . . .. . .. ... . .... . ... .. . . . ..... 117
5-3-5. Structure
of program . .. . . .... .. .. ... .. ... .. . ... . . .. . .. .. .. .. ... . .. ..... .. 117
5-3-6. Struc
ture of reserve area .. ....... .• .. . .•• .. ••. .. • ... . .. . .. . .. .• .. . • .•. .. . . 118
5-4 . System subr o utines ........ . .. . ... .. .. .. .. . .. .. ... .. .. .. . . ... .. . . .. .. . .. .. ... . 120
5· 4·1. Character fu ncti o ns . .. . . . . .. . . .. . . .. .. . .... . ... .. . .. . .. ... . .. .. .... 122
5·4· 2. A rit hmetic su br outines . .. .. . . .. .. .. . . .. . .. . .. . .. . . ...... ... .. . . . ... .. ... .. 127
5-4-3. Co mpar ison .. . . .. . . .. . .. . .•. . .. .. . . .. . . .. . .. . .. •. . . •. ..• •. .. . . .. •. . •. . . .. 128
5-4-4. Search .. .
.. . .. . .. . .. . .... .. . . . .... . ... . ... .. . .... . .. .. . .... . . .. . . .. 129
5-4-5. Display . .. .. .. . .•. ... ..
.. . ... .. . .. ... . ... .. . . .... .. ...... .. . .. . .. . 131
5-4-6.
Pr i nter .. .. .. .
..... . . .. . .. . .. ... .. .. . ..... . .... . . .. . .. 1 35
5-4-7. Cassette tape
.. . .. . .. . ... .. . ... .. .. ... .. .. .. .. .. . . .. . .. ... 1 38
5-4-8. Caution for system sub r out i ne call . .. .. . .. ... .. ... . .. .. . ..... . . ... .. . . . .. . 141
6. Mac hin e language programming exa mp les .. . .. . .... .. . . . ... .. ... .. . . .. ... ...... . .. .. . 143
6· ·1. Binary to hexadeci ma l conversi on .. . . .... .. .. . . ... . .. . ... . ... .. .. .. . .... . ..... 144
6-2. Display
inve rsi on .. .. .. ....... .. . ... . .. . ... .. . ... . .. . . ...... . ... .. .. .. .. .. . . .. ... 145
6-3. S
ingl e dis pl ay d ot le ft sh if t .. ...... .. . .' ... . .. .... ... .... .... .. .... ... .. .. ..... . .. . 146
6-4 . Si n gl e di splay dot right sh il l. .. . . .. .. .. . .. . . .. . .. .......... . . .. . .. . .. . . ..... .. . . .. 147
6-5 . Conversion of USING for ma t expressed numerical data i nto charact er string . .. ... .. 148
6-6. Power
off that does not ac ti va te the p ri nter upon p ower on . .. . .. . .. . ..
.... .. 148
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(REFERENCE]
1.
Determining printing cha racter size and dire cl ion .. . . .. .. .. .. . .... . . .. ... .. .. .. .. . . .. .. 150
2. Restoration of ar r ay and two-characler vari able ... . ............... . ... . ..... ... .. . ..... 150
3. Knowin g the use of CE- 15 0 ........ .. ......... ..... . . ... .. .. .. ... . ... . .... . ..... .. .... 150
4. CMT formal ...... ..... ... .. .......... .. . .. .. . . ... . ... ... .. ..... . ... . . ... . . .. .. . .. ... 151
5. Circu it diagram ... .. .... . ... .. ...... ... .. .. .. . .. ... . .. ... .. .. . .. ........ ... .. .. . .. .. . 153
5-1. PC-1500
.. . . .. .. .. .. . . .. ... .. . . .. . . ... .. . . .. ... .. . . .. . .. . . .. .. ... .. . .. . .. ..... .. . 154
5-2. CE-150. .... . .. .. .. .. ... . ... . .. .... . ..... . .. .. . .... . .. ..... .. . .. . .... ... ... ...... 155
5-3. CE-151 ... .............. . . .... ... .. ...... ..... .... .. .... .... . ... .. ... . .. . .. .. ... . 156
5-4. CE-153. .
.. ... . .... . .. . . . .. . .. .. .. . .. . .. .. .. . . .... .... . ... .. . .. . . .. . . .. .. . .. .. . 156
5·5. CE- 1 55 ..... .. . .. .... . .. . .. . .. .. . .. . . ... .. . . .. ... . .... .. . . .. .. .. . .. . .. .... . .. ... . 157
5 ·6. CE-156 ..... .. . . .... .. . .. .... . . .. ... .. . . .. . .. ....... .... .. .. ... .. . . . .. . ... .. .. . .. 156
5-7. CE-159 .. . . .
.. . .. . .. . . .. .. . .. . . . .... ... . ... .. ...... .. . .. . .... . .. .. . . . .... . .. .. .. . 159
[
ADDENDUM]
Di fferences between the PC-1500A and lhe PC-1500 ... . . .. • .. .•. .. .. . ... ..... •......... . 161
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Machine Language
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1. Machine language
2
There are many program languages for each purpose. PC -1 500 . for exa mp l e. is
designed to carry out
bo th BASIC and machine language. BASIC iseasy to u se .
however. execution speed is sl
ow . On the ot her hand. machine language is
difficult to understand but execution speed is fast.
Usually. machine language program would be written with the assemble
lan
guag e. wh ich consists of mnemonic codes. and then the assemble language
will
be translated into machine langua ge .
[EXAMPLE] DISPLAY REVERSE PROGRAM
I. f> rc p an: thi: progranl ,,· ith asscn 1h le J ;,ngtu1~.: co n sis ting of nl ncinon ic codc::i. .
LOI UH.78H l i . f fi · b ffi dd
LOI U l. .4 DH I prepare or:1"1gnmcn1 o the 1n.1 d"pl a) u er a ress.
D EC UH advance the adclr<-,,,
LDA U take data in the a cc umula tor
EA i FFH
ta ke l hc C<H n(llc 111 cnt
STA u return datu i 111 0 n1c 111 ory
LOP 06H
CPI Ull. 77 1-1 makc the loop
BCS
OEH
RT:'< return to B1\SIC
2. T ran~latc th e abo,·e progr.l rn in to 111achine language. 1 he a!'>. qon1b l cr 1r:tn~latc~ the
as:i.cn1blc l anl:!uag:c in to 1he n1a chinc l;t n guagc au l<lrnatic-dlly acco r ding tt> t hl' li~ t.
1 -1 <>\\l'\cr. a l) ho r1 p rogr a rn can he 1 ransla1cd n1a nually. (h and ;1~~c 111 b l c)
· rh e ab o,·c pro£ra n1 c"n be tr an~k 1L c d a:-. follo,,
11
;:
6X 78 6/\ 41) FO 62 25 l.ll)
FF 2E 88 0(1 6(' 77 93 OE
9A
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3. After the completion of the machine language program. write it in l'C-1500by using
PO KE in struc ti on. And execute the program together with B AS IC by CALI.
in s truct ion.
Execute the followi ng program. Y -011 can ru"n the BAS IC pr ogram with [filJ ® and the
machine language program \\
it h I '.J F l (Bl. Di.playreverse in machine language program
i, faster than that of BASIC. You would kn ow how functional the machine L~nguagc
program is.
EX. Write the following program after execut in g NEW &4100 C@.
10 "A" WAI T 0
20 PRINT" sh o r e oocke t c omo u 1e r "
30 FOR A-0 TO 155
40 GC URSOR A
~ GPRI NT 25 5- PO ! NT A
flJ NEXT A
70 GOTO 30
80 END
100 "B" WA 11 0
IW PRINT •• sh ar o oocket comou 1er
11
120 PO KE St-0C5 ·&68 •&?8 •& 6A •&4D•
&F0 •&62 ·&
25 • &6D •&FF · &2 E• &88 ·&06
130 POKE &4 00 1· &6C ·&?? ·& 93 · &O E· &9A
140 CA LL &40C5
l :'Q WA IT 2 0:PRI NT : GO TO 140
160 END
111is manual is di ,id cd into three ma jor section•: description of LSI (pp. 5-84 : l.11 5~01
Mi cr oprocessor & 1.H 58 1011.H5 81 I 110 p or t controller). l' C·1500 hardware description
(pp . 85 - 109). and PC-1500 so ft ware de scription (pp. 11 1- 141).
If you wm1l to know
about l'C'-1500 ~) 'S tem li rst. read from p. 86.
3
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4
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LH5801 Microprocessor
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5

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2-1. Outline of LH5801
6
The L.H580 I Mic rop roce ssor is " CMOS static 8-bit microprocess or th at features l ow
po, ve r di ssi patio n p cr forrna ncc inhere nt 10 Civ lO S l .. SJ and hu· ge c apa city data
pr
ocess in g. '.\lot <1n ly th at. it enab le ~ to to configu re a variety of sys .t cn1 s \ Vi th .a fc \v
additi ona lchips because such as the LCD backplate signalgen er ato r. i npu t port. e.xtcrnal
l atch clock. and ti mer a re built in the 1. H5 80 1.
Features of the LH5801
<D 8 -b ii t parallel darn processing
CD Dir ec t 11 ccc ss ing of I28K b,·tcs
(j) Us <:: of a 6-bytc general purpose register. in addi ti on to the accu m.u l :uor . allows to
con ·1pr ise th re e pa irs of 2 ~ hy t e date poi nte rs .
(•) 9-bit timer cap abi l it y
0 Th ree ki nds of interrupts
• Non-maskable int errup t
• Ma s kab lc inter rup t
• ·ri rncr i nter r upt
© 82 instruction set
0) WAIT functi on (memor y access co ntro l possibl e)
© Clock P <b fo r input po n (8-bit) a nd exte rna l l atc h
CD M emory b<1ck up functi on (BFJ. BF O)
@ LCD backpl at e signal co ntrol
@ Exte rn al cry s ta l co n ne ction for c loc k gl~n c ra ti on
@ ) ~ ed u c i ng pr ogr arn ste ps by n1 e an s of 28-ki nd ~ i n g l t step v ec t or s ul>rout ine jurnp
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2-2. Internal Structure
2-2-1. Block diagram
F ig . 1- 1 B lo ck diagram of LH5801
VG G
'IC C
v ss
s
T A
D
XLO Xll
!n :; t ;uc lKin ~ ~ ooo e ~
& (:P l) (;(ln ltOI
tP 0S 'NAil HA N Y. I Ml
Clock, !1 :!( :111 1pt
C~'l t ru l con11 ol
T1rne1
(; (l! i lJ (,11
PO .,..,X: t
$ UP I> ¥
00ti :r l)l
Pu Pv 01 .sP I
0;>( BA K ! ~ RQ atst r 0 -0 Rt\ \• M(OM £10f 0 Sfl 00 -0 1 I NO-tN7 PU PV UISP
Fig. 1-2 Internal register & flipflops
PH 'I PL
'I P:
Pr ~ ra m counter
VA
VO
VM
VDIS
SL • S: Stack po i nte r
Carr; a 11d bouo v;
(b y« > to byte )
XH
YH
I UH
•1 XL
8
X r~g f Da1 a po intc-f.
8 YL 8
Yreg : or
8
~ Ur~g H < ~n<nal pu r po s ~ :e. regis ie r
A
•J
A: Ac cu mul a:t or
TM
'I T
1.1: Tin,e1
Cl
PU l
: Ge r.oral pur pose fl ip fl op
I_] Pl/
j 1) O ISP : L CO oa /o ff coo 1 10 !
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-· Z: Zero
'- -- -V: Ove r f.Jo "v
- H: Car e; ·
(d1 g1 l 10 di p, it)
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2-2-2. Internal registers
Symbol Name Bit si ze ocsc1iptlon
p P
rogr arn C< ninter 16 I ndi cates the addr ess ne xt to the ;)(!dre ss t he CPU
is no\•1 in exe cution
II wi ll be in cremen1ed by " 1-
'.. ' Jhe n t ho next instruc li on is 1e1 c::ho <f .
s s~a c k 16 l ndi ca 1cs th e st ack a ddr ess.
p oir nc'
A Accv m ul atoc
s Used t or retenti on of c p. eral iona l <e su ll or for data
!rans.fer •v il h th e e x1 cr na 1 mcrnofy .
Xrc g XL 8 XL.
XH . YL .YH . Ul . UH compris-e ind ependen; 8·
XH
8 b
it re giste rs.
Also. used as 1&.b it data poin;ers. xrcg. Yrcg. and
YL
I 8
Ur cg. ..... hen used in a pair.
Y
reg
YH
Oeta regist er
8
UL 8
Ur eg
UH
8
TM Timer co un 1c r 9
v.
1
hen ' 'O., is s et to !he T M. it steps t he c oun ler
ac~ 1 on . Whc r' a n;•th 1ng Olhcr lhan "O.. is SCI. 1;
p uts the counter into ac?ion. When the TM lu ~ ns
fu ll of .. 1·· · 11it h ti'~ in1 euu pt e nab le sign <) l IE on .
CPU executes an 1 ntcrtup 1p roc essi ng .
PU 1 Genefal Pt•rpose fl ip-Hep.
PV
1
DI SP 1 LCO oo /o lf co 1 nro 1.
T S 1;;. 1o s re~1 i st et
8 LO\v otdef 5 b
it s fOpfes an1 one of f1\'Cs ta tus of
opeta11o na l result
2-2-3. Status flags
S1 at us fl a g ~ . C. \'. f~. Z. 1 1' ·: a rc c<u1ta in cd in the 8-bit st atu s re gist er . In gene ral . tl a g.'\( Hhcr
than
IE change their scatc af ter the execution of ar it h £n etical instructio n.
Status register T = [ 0 ' 0 I0 HIV Z j1E C I
(i) Ca:rry flag c
Cat"ry flag C is set \vhcn there is <' carry f ro n1 t l1i: MSll and r cs t.:t \vh r,; 11there is n<> carry.
~ : o .. Sl JBTR. t\Cl ', the nag is :se t \ Vh Cn t he re is no borrO\Vor r l'f\C t \Vht n th ere is.
<D Ha If carry flag H
Halfca rr y lla g H is se t when there is a carry from the bit position "3" (digit-to- dig it
ca r .ry) a nd reset \vhcn t he re is no ca l' ry .
<D Zero flag Z
Zero nag z is s r: t \Vhc n the ()p er'ational l' C'S llh is 7Cl' Oanti re set \\ -' hen n<H .
© Overflow flag V
Overn ow na g V is se t or r ese t d epe n din g on theop era ti onal r es u lt of ..C6 <:b CT: where.
the c ar ryfrom the bit position 6 of a single b yt edata is a ss umed to b ~ C6 and t h c carr~ ·
fr om the bit pos iti on 7 to be C7.
Single by te da ta
87 9695 94 9382 8 1 BO
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2-2-4. CPU pin description
~ :::~ ~ = e C O t--. l MN -
U OOO OOO~c~z o88 3ooo8
Z<<<<<<<><C<<<<<<<<
R/ l'I
~-E~~ ~~~ G G47•e«CG 4 1 ~B
~ .07
p4,
59
37
06
PV
60
36 05
PU
61 3S
04
4, os
62 34
03
XLO
63
33 02
X LI
64
32 01
V'°AI T 65 31
DO
I N7
66
LH 5801
30
MEO
I NG
67
29
M EI
INS
68
(T OP VIEW)
28
OD
I N4
69
27 HO
IN3
70 26 Hl
IN2
71
25
H2
INl
72
24 H3
1 1\'I)
73
23
H4
NC 74 22
HS
NC 75
21 H6
NC 76
20 H7
1 2 3 4 s 6 7 8 9 1 01 11213 14 15 1617 18 19
....
w
(/) o oou.. :s::u c ~ -
w O m~o~&cuo~OC~~ - 1 ~cm
~z mm> m om>>>>>>Z~zzo
0 XLO , XL1
The se ar c external Cr )'S tal co rmcc1 io n pins. X 1.0 is the i nput pin and XLI is the o utput
pin. Clock frequency is div id ed by t wo inside the C PU. Wh en the 2.6M H 7. cr ys tal is
c onnecttd. the CP U o ~ra1 es 1111d cr I.3MHz of internal machine cycle.
(j) ADO -AD15
A ddr e ss bus. Ou tput s from th ese pins arc 3-srnte (three omp ut statesof high. l ow and
high impe da nce) and go h ig h imp eda nce with BR Q (Bus Rc Qu cst). Basica ll y. MK
bytes of 1nc rn ory area i :s ~uppo r t c d r(>r dir ec t ac cc~ :sin g, hut it isn la dc po ssi b le to acc ess
even I28K
area of memory ar ea wh en MEO and ME I ar e used.
(i) 00 - 07
l~ idi rec tiona l da ta bu s \Vhich i:s used co 'vrite or data to / f ront the exte rnal n1 cn 1ory.
©MEO, ME1
Mc rn o.-y enable signals. As m emor y ar ea of 64K bytes isaccessed by M EO and anot h er
64K by tes by MEI. it permits dir ect acc es s of m emory area of 128K bytes in t ota l.
Since f\1 EOis us ed fol' instru ct i on fet ch an d s tack opera tion. acce ss in g by n1cans o. fthc
progr a1l1 C< ltirtter J "> an d stack p <>i nter S is lin1itcd t <> a n)axinttHtl of 64K bytes.
As for darn accessing. bo th m emo ry area s co vered by MEOand M El can be co ntrolled
by a CPU i ns tru cti on .
9
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® 4>0$
Through th is li ne can be supplied t he clock 10 an externalsystem since 1he clock in the
same ph;,sc as the CPU internal basic clock is on this line. C onn cc ci on of the 2.6M H1
crystal oscilla to r lo XLO and XLI will supp ly ihc cl ock of l .JMHz .
©RIW
Me 1n ory \Vri te si g rHtl. ./\ l o\v on th is lin e caus es th eC l> U t c> se nd dat a on L he d ata bus .
Q) OD
Ompul disablesignal. A high on this line causes theCPU IO prohihi1 data ou1put 10 th e
external de v ice . It is used in \Vriting da ta ro the me rno ry.
4>0S
AOO -
AD 15
I
~AEOo f~
ME1 I
OD ~- -' '- ----- -~ - __,/
' . ~----
'I
'<.__ _
00-07' ...... --- -~< MEMORY O ATA D >--- - < CPlJ DA TA ) >--- --
' ~--- -~.--'
k4 cmo 1y < cad c· ; cle
Men lO I'; ·1• ote e ye ~
©R ESET
C PU reset input. High stale or this si gnal 1·cscts the CPU and t he con1cn1s of 1h c
addre ss FFFEH is sci IO the register PH ;ind the contents of the addres s FFFFM lothe
rcgisier PL. When ii !ur ns from hi gh to low level. it si ar ts programexecution from the
address or !he program counter.
CD NMI
Non1 -maskablc in1 cr rup1 input. Highstale of this signalcaus es in1crmp1 10 the CPU .to
\v hi ch the CPlJ uncondit i onaJJ yr es pond sa nd sta rt sthei nt e rrupt proc e ssing ro utin e of
which hi gh order byte addre ss is re pr esented by 1hc addr ess FFFC H and l ow order
byre addr ess by FFFD H.
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@Ml
Maska bh! int cn upt input. Wh en the interrupt enab le nag IE is acti ve .a high on th e pin
Ml req u es ts interr upt . to wh ic h t he CP Ustarts 10 e xecute th e inte r rupt pr ocess in g
routine whos.: h ig h order byte address is re presented by the add ress FFF8 H and l ow
o rd er byte addrcs' by FFF9 H.
How ins tr uc tion exe cu tion address is determined against the reset and inter rup t
input
E Jt tCfn.itl memory
Addie ss
EOOOH
E 171 H
E22 BH
C22Cll
fff8H
9
A
8
c
D
E
FFFFH
~
~
i...-:--..
ElH
71H
( 2H
2CH
E2H
2 0!1
lOH
OO H
v-- ·
1--
l
r
I
r
I
I
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-
-
-..
Start address
by RESET onp.; t
S t:'l. rl add• C-SS
by Ml 1np v1
S1art n dd ress
by NMI input
Start address
by timer 1 ntetrupt
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@BRO
Bu s r <:q u cs t :; i gn al.
@BAK
flu s req ue st ackowlcdgc signal. Wh en BRQ goes hig h. the CPU issu esa high leve l of
s ig n.al on BAK in r es pon se to it. The CPU k ee psaddress bus (ADO -ADl5). data bus
(00.-07) . MEO . ME I. R/ W. and OD high impedan ce wh en BAK is in hi gh le ve l.
@OPF
O per at ion C« ><.l e fetch sig nal \ \l hich is se nt out \vh en CP lJ fetc hes operation C <><ic
(insll'uc ti on code).
0 l'F is iss ued only wh en op er a1 ionco de is fow h cd nnd will not be i ss ued in fcwh ing
addr ess data. i n1m edi a1 e data. a nd sec ond by 1e of the \\VO- ste p in s tr uct i on .
4> 0$
A~Ao t s _ ____ ~X~ ------- -~L
M EO
OPF
@ INO-IN7
-,---------.
I I
~-~ -~
-
Las i
I Cye ie
_ ,,_ __ Ope r at i on cooe _ _ __,
toteh
Inp ut p ort through \Vhich the C l)\ J n:c-:i vt s 8- hi1 dat ai nt< ) theaccu n1u lat or.. ;\ si nt erna l
pu ll up re sist or is us ed . the CPU assum es it to be high le ve l when n.ol co nn ec ted.
@ p<P
External latch clock. With high l eve l of this cl ock. the conten ts of li te <1ccumu lator is
sent on the data bus. Addition of IC will co mp r ise an outpul port.
REFERENCE: ATP in structio n.
@PU , PV
Th c:sc arc CPU internal nipflo1>outputs. PUand PV arc furnish ed w ilh se l and reset
in s1r uciions.
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@ WA IT
CJ> U wait signal. A high on this line stops the clock '1> so that the CPU halts it>
operation. 1 \s soo n "' WA IT turns lo", the Cl' U rcM1mcs the operation.
Rt1s ic CIOCk 4>0$ / \'- _ __, /
\'-- ___, / \ '--__, / \ '-- ___,/
\
Clock
~ I
\~--'I
\ ._ _ _____ .....JI
\
\'lAIT
'-- --- ---- -- ---- -- ----- - --- - --~-~
NOTE. WA is th~ Jlipllopdedi<:aled to WA IT. by which the WAITinput is received a1 the talhng
edge or the ctock 4> 0$ Because the CPU operating cloc k 4> stopswhen WA is hogh. 11
makes the CPU
0 stoppe<j. consequently.
@ HO -H7
I.CD b ackphll c sign;il o ut p uc. As the li quid cry stal tfa play (lC f>l is d ri,c n by
backplate s ig nals an d scg 1n cnt si gna1s. the (' l> U co ntrols the ba ckplate sign ;, d s.
@ VA , VB , VM, VDIS
I.CD bac kp l at e pow er s 11 pply inp1 11 s.
@ HIN
I npu t signal 10 the counter from which tl tc LCD backplalc signal;, M0 - 117 arc
generated. 1'om1all}. connected 10 pin llA or th e CPU .
@HA
CPU internal divid er ou tp ut pin. It is used for the ba;ic clock that dri ve, the LCD t hat
ctlnncctcd \ Yi ch tll!\1 and the s.cg n1tnt signal gcncrating l .S J.
@ DI SP
l. (' f) on/off control l\ig nal output \v hi ch ca 1l be se t or re set by n1 c an s <lf instru ct ion.
@ BFO, BFI
BF nipOop output ( llF O) and i nput (B FI). The H I' OipOop is rc "Sc t bi• the OFF
instruction from the CPU. and "ill be set when the input 13FI is turned to high level.
ll FO is in low level when the BF OipOop is se t and in hi gh level when R'.SCI.
As VG G is power su pply to the BF OipOop. the conle n t' or the OipOop are retained as
lo
11 g as VGG is in supp ly.
No rrna ll y. it is u ~cd for rn c n1 ory back up sy stcn1 .
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2-3. Functions
14
2-3-1. Timer
Th e ti ntt cr is a 9- bit poly norn inal co un te r. ·rhc cou nter va lu e c an be set by t he AMO or
AM I instructi on of the CPU. Shown in .. POLI NO MINAI. CO UN'rE R.. is th e li st of
h cxadcc in 1al data of cou nter \v ith d cc in1 al count nurnb cr .
TI1e t i1 ner ope rat es co nt in uo us ly at a lJ ti rn c s. \\ ih cn the co un te r va l ue reach es 11 =- i-:H. it
i ssues interrupt reque st to t he CPU. IfIE( lnt cn upt E nable) fl ag isac ti ve at that poim. the
Cl)U j u n1ps to t he t in 1cr in t errupt pro ce ss in g ro utine \vh os c high order byte addre ssis
represented by the contents of the addr ess F FFAH a nd l ow order b y1c addr ess by the
co nt en ts of the ad dre ss FFFl3H. TI 1c tim er has 10 be set to OOO H when it is not used.
S in ce it cou n ts in sync hroni 1; · 11 ion \Vith th ecl oc k <l>F . eac h one c ycle or <J> F in cr~ nt c n ts th e
co unter one st ep.
L. __ D_iv_id_ ,e _r_ _,I - <I> F
\Vhen chc 4rvtHz cr ys ta l os cillator is in co n nec tio n. th e ti n1e r is incre n1 en ted at C(lch
32µscc. because <PF is 3I.25k Hz.
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