Siemens 6ES5-424 Product manual

SIEMENS
d Counter Module
Technical Reference Manual
Version 18: 10. 1986
Preface
This document providesdetailed hardwareand software information on configurationsfor the five front connectors,are also included. The final
the 6ES5-242 Counter Module. The types of information and their portioninthis chaptercontainsthe module's memory map.
locationswithin this manual are listed below.
Chapter 3 Register Description and Use
Chapter 1 Hardware Desgiption
Coverage examines manipulation of the module's internal registers.
This chapter presentsa general descriptionof the module and the two A description of each of the available counting modes is also
LSI chips that perform all counting and interrupt functions. Also, a presented.
generaldescriptionof eachof theregisterscontainedinthecounterchip,
the interrupt chip and the remaining registers of the module is given.
Chapter 2 Module Setup
lnformationconcering initial setup, switch setting and jumper configu-
rations is provided. Specifications on the module's
110, as well as pin
Contents
Chapter 1 Hardware Description
1 .l General Description
1
.l.l Gate Control
1.1.2 Inputs
1.1.3 Outputs
1.1.4 lnterrupt
1.1.5 Scaler
l
1 .l .6 Scaler 2
1.2 6ES5
- 242 Block Diagram
1.3
The AM 9513 Counter Chip
1.3.1 Master Mode Register (AM 9513)
1.3.2 CounterMode Register (AM 9513)
1.3.3 Load Register (AM 9513)
1.3.4 Hold Register (AM 9513)
1.3.5 Alarm Register (AM 9513)
1.4 6ES5 - 242 Module Registers
1.4.1 Control Register
1.4.2 Function Number Register
1.4.3 lnterrupt Mask Register
1.4.4 lnterrupt lnformationRegister
1.4.5 ErrorSignal Register
1.4.6 Result of CounterRegister
Chapter 2 Module Setup Procedures
2.1 Switch S1 - Addressing
2.2 Switch S2 Group Interrupts
2.3 Switch S3 - System Interrupts
2.4 Switch S4 - Gate Signal Conditioning
2.5 Switch S5 - Counter lnput Routing
2.6 Switch S6 - Gate lnput Routing
2.7 Jumper Assignmets
2.8 lnputsand outputs
@a 2.8.1 Plug Connectors
2.8.2 Counterand Gate Inputs
2.8.3 CounterOutputs
2.8.4 Signal Conditioning
2.9 Module Pin Out
2.10 6ES5 - 242 Module Memory Map
Chapter 3 Register Details and Use
3.1
INTM - lnterruptMask Register (AM 9519)
3.2
INTl -Interrupt lnformation Register
3.3 MM - Master Mode Register (AM 9513)
3.3.1 Real - Time Clock: MM1 - MM0
3.3.2 Comparators 1 and 2: MM3 - MM2
3.3.3 Scaler
2 (FOUT) Pulse Source: MM7 - MM4
3.3.4 Scaler 2 (FOUT) Scaling Factor: MM11
- MM8
3.3.5 Scaler 2 (FOUT) Enable: MM12
3.3.6 Scaler 1 Counting Mode: MM15
3.3.7 Bits MM14 and MM13
3.4 CM-Counter Mode Register (AM 9513)
3.4.1 Output Selection: CM2 - CM0
3.4.2 Counting Direction: CM3
3.4.3 Counting Mode: CM4
3.4.4 CountingType: CM5
3.4.5 ReloadingSelection: CM6
3.4.6 Special Function Enable: CM7
3.4.7 Pulse Source Selection: CM1
l - CM8
3.4.8 CascadingCounters
3.4.9 Pulse EdgeSelection: CM12
3.4.10 Gate Control Selecion: CM15
- CM13
1) 3.5 Counter Modes
3.5.1 ModeA
3.5.2 Mode B
3.5.3 ModeC
3.5.4 Mode D
3.5.5 Mode E
Page
Chapter 4 Standard Software Function Blocks
The two standard function blocks available for the 6ES5 242 module,
FBI58andFB159, areexamined. Functionblockparametersarelistedand
explained in detail. The chapter closes with a few helpfulprogramming
hintsso you can manipulatethe module's firmware.
Page
3.5.6 Mode F 55
3.5.7 ModeG 56
3.5.8 Mode H 56
3.5.9 Mode
l 56
3.5.10 Mode
J 56
3.5.11 Mode
K 56
3.5.12 Mode
L 56
3.5.13 Mode N 57
3.5.14 Mode
0 57
3.5.15 ModeQ 57
3.5.16 Mode
R . 57
3.5.17 Mode S 57
3.5.18 Mode
V 58
3.5.19 Mode
X 58
3.6 CTRL - Control Register 58
3.6.1 Control Words: CTRL7 - CTRL5 58
3.6.2 Additional Functions 59
3.6.3 Counter Selection: CTRL4
- CTRLO 59
3.7 FNR - Function Number Register 59
3.8
FEM - Error Signal Register 59
3.8.1 ErrorDescriptions 60
3.9 Ex - Results of Counter Registers 60
Chapter 4 Standard Software
45 4.1 Function Block 158
45
4.1.1 OrganizationBlocksfor 158
46 4.1.2 Explanationof FB 158
47 4.1.3 ParameterBGDB
47 4.1.4 Parameter.P/Q
47 4.1.5 ParameterPAFE
47 4.1.6 ParameterBFEH
48 4.1.7 ParameterSFEH
48
4.2 Function Block 159
48 4.2.1 Explanationof FB 159
49 4.2.2 ParameterBG
49 4.2.3 ParameterPQ
50 4.2.4 Parameters24-1 and Z--5
50 4.2.5 ParameterBEF
4.2.6 ParameterDBDW
4.2.7 ParameterINTL
4.2.8 ParameterFEML
4.2.9 ParameterPAFE
4.3 Standard Software DataBlocks
4.4 FB 159 Usage
4.4.1 Access Time
4.4.2 MM and INTMRegisters
4.4.3 Alarms Registers
Appendix A
Appendix B
Figures
1-1 6ES5-242 Counter Module BlockDiagram
2-1 242 Module Plug Connector Block Diagram
2-2 242 Module Plug Connector Pinout
2-3 Counter & Gate lnput Circuitry
2-4 Counter
& Gate lnputTTL LevelCircuitry
2-5 Counter
& Gate lnput 24 V Level Circuitry
2-6 Counter Output Circuitry
4-1 Function Block 158
4-2 Function Block 159
Tables
4-1 OrganizationBlock Calls
4-2 Data BlockAssignments

Chapter 1
Hardware Description
1 .l General Description
The 6ES5-242 module consists of five high speed counters
which can be independent of each other, or cascaded. The
following is a general discussion of capabilities available with
the 6ES5-242 Counter Module. Details of these capabilities
and how to configure the module is presented in Chapter 2
of this manual.
1 .l .l Gate Control
Each counter can be enabled with either an external field
signal or an internailly generated signal. A variety of signal
configurations isavailablefor the gate inputs.
1.1.2 Inputs
Internallygeneratedsignalsfromtheoutput of oneof theother
counters, or output from one of the two internal scalers are
provided. External inputs are provided from each of the
counters, which can be connected to a user application.
1 .l .3 Outputs
The outputs may be used internally to feed another counter
or to trigger an interrupt; or externally connected to a user
function.
1 .l .4 Interrupts
Counters 1 & 2 allow you to programthe counter to generate
an interrupt when a specific count is reached. All of the
counters can generate an interrupt (if enabled) when the
counter's output becomes active. The counter's active state
can be defined bythe user.
Gate inputs 1, 2,
& 3 are connected directly to the interrupt
controller, and can be enabledto generatean interrupt when
they are active. The gate inputs signals can be selected for
active highoractivelowstates.Thesethree interrupts operate
separately and are not influenced by counters 1, 2, or 3.
1 .l -5 Scaler 1
An internal scaler is available whose five fixed frequency
outputs can be routed to the input of any of the counters or
the input of Scaler 2. The 2 MHz system clock is used as the
inputfrequency to the scaler.Theoutputs arescaledinfactors
of 10 or 16 from the input frequency.
1 .l .6 Scaler 2
Scaler2 isusedtoscaleitsinputbyaselectablefactor between
1and 16. The input can be selected from any of the counter
inputs, gate inputs, or Scaler1outputs.The output of Scaler2
can be connected by a jumper, selectable on switches S5
or S6 to the counter inputs, or gate inputs of any of the five
counters.
1.2 6ES5-242 Block Diagram
The 6ES5-242 counter module is an intelligent peripheral
controlled by a 8085 microprocessor system. The module
uses the AM 9513 Counter Chip, which contains five
independent, high-speed 16-bit counters to perform the
counting operations. The AM 9519, an interrupt controller, is
used to control the user-programmable interrupt structure.
The firmware for the module is stored on a 4K byte EPROM.
A 1K byte CMOS RAM chip is used for data storage.
The counter and gate inputs and the counter outputs are
optically to the front connectors of the module. Figure 1-1 is
a blockdiagramof the logiconthe6ES5-242 countermodule.
Thecontrol logic handlesthe interface betweenthe 6ES5-242
and the PC.
Counter Module
Block Diagram
1 8085 11 8KEpm 1 I I
Microprocessor
(4 K firrnware)
(4
K user) (tempstorage)
Interrupt
Controller
Figure 1-1 6ES5-242 Counter Module Block Diagram

Chapter 1
Hardware Description
1.3 The AM 9513 Counter Chip
The AM 9513 counter chip contains five high-speed counters
which can be programmed to perform various counting and
scaling functions. A general description for each of the 16-bit
registers that control these counters is given below.
1.3.1 Master Mode Register (AM 9513)
The MasterModeregister(MM) is usedto enableand perform
special functions which are common to each individual
counter.Thereisonemastermoderegisterforallfivecounters.
These functions include:
W Definingandenablingtheinputs,outputs,andscalingfactor
for Scaler
2. This is the main function of the MM register
W Providing an enable bit for the output of Scaler 2. The
output of Scaler 2 will be referredto as FOUT
W Providing enable bits for the two comparators that are
availablefor Counters1and
2
Providing a bit to select the operating mode of Scaler 2.
Either binaryscaling or BCD scaling is allowed
B Providing two bits which are used to control and enable
the real-timeclockfunction
1.3.4 Hold Register (AM 9513)
There is one Hold register (H) for each of the five counters.
The Hold register is used as a storage buffer for the counter
value. The contents of the counter will be transferred to the
Holdregistervia a software command. Thisfeature allowsthe
user to check the current value of the counter without
interrupting the counting operation.,
The Hold register cannot be read directly; its data is first
transferred to the result of counter register. You must then
readthe result of counter register to retrieve the value stored
inthe Hold register.The resultof Counterregisterisdescribed
in Section 1.5.1.
1.3.5 Alarm Register (AM 9513)
There are two Alarm registers (A); one for Counter 1, and one
for Counter 2. The Alarm register is used in conjunction with
the comparators available to Counters 1 and 2. The Alarm
register.is used to store the value which will be compared
with the counter value. If the comparator is enabled in the
Master Mode register, the output of the counter will become
active only when the Alarm-registervalue equals the counter
value. The Alarm register may also be referred to as the
Interruptregister.
1.3.2 Counter Mode Register (AM 9513)
There is one Counter Mode register (CM) for each of the five
1-4 6ES5-242 Module Registers
counters. The counter mode registers are used to provide The 6~~5-242module has several registers which are not
control, setup, and operation of each individual counter. found in the AM 9513 or the AM 9519 chips. These registers
These functions include: are usedfor various functions which are not available on the
W Providing four bits to select one of 16 available pulse AM 9513 or the AM 9519, but are necessaryfor the operation
sources to the counter of the AM 9519, but are necessary for the operation of the
W Providingabittoenableordisablethegatecontrolfunctions module. A brief description of these registers is presented.
W Providing three bits to select the operating mode of the
1-4.1mntrOl~~~i~t~~
aate controlfunction
-
TheControlregister(CTRL) isusedtocontrolvariousfunctions
Providing a bit to select the counting pulse edge, either
and counter selections of the AM 9513. This register is not
rising or falling edge
+@
normally addressed directly by the user; the function blocks
W Providing a bit to select one of two registers from which used to communicate with the 6ES5-242 module will handle
the counter value can be loaded any data transfers to this register.These functions include:
W Providinga bitto select one of two counting modes, either
W Providingthree bits to select from one of eight possible
continuous or onecycle mode chip operations which include: parameter assignment,
W Providingabittoselectthecounter's operatingmode,either counter manipulation,andselection of additionalfunctions.
binary or BCD counting
W Providing five bits, one for each counter, which are used
Providing a bit to select the counting direction, either up
counting or down counting. to specify which counter or counters are to be involvedin
theoperationselected bytheotherthreebitsof theregister.
W Providing three bits to select the output configuration of
the counter
1.4.2 Function Number Register
The Function Number Register (FNR) is used to identify the
1.3.3 Load Register (AM 9513)
user-stored functions. These functions can be stored on a
4K byte EPROM.
There is one Load register (L) for each of the five counters.
The Load register is usedto providethe counter with a preset
count value which isset by the user.

Chapter 1
Hardware Description
1.4.3 lnterrupt Mask Register
The 6ES5-242 module has one 16-bit lnterrupt Mask register
(INTM); the eight low order bits of the interrupt mask register
are usedto enableand disable the eight interrupts generated
bythe AM 9519. Only two of the eight high order bits of the
interrupt mask register are used. These two bits are used for
enabling a group interrupt for a Ready signal and an Error
signal, which will be described in detail later in this manual.
1.4.4 lnterrupt lnformation Register
The lnterrupt lnformation register (INTI) is a 16-bit register
which is a mirror image of the lnterrupt Mask register. It is
usedto storeany interrupts that haveoccurred.You may read
the contents of the lnterrupt lnformation register to determine
which interrupt has occurred.
1.4.5 Error Signal Register
The Error Signal register (FEM) is a 16-bit register which may
be read to determine if one of several errors has occurred.
A group interrupt will be sent to the PC if the error bit in
the lnterrupt Mask register is set.
1.4.6 Result of Counter Register
There is one Result of Counter register (El - E5) for each of
the five counters. The Result of Counter register is used to
store the current count of the counter when the register is
read. Reading the register does not affect the operation of
the counter
The Hold register cannot be read directly; its data is first
transferred to the Result of Counter register. You then read
the Result of Counter register to retrievethe value stored in
the Hold register.

Chapter 2
Module Setup Procedures
Thissection will describe indetailthesetup of thesixswitches SWITCH S1 Jumper Assignments
located on the 6ES5-242 module. Jumper Address
2.1 Switch S1 - Addressing
The S1 switch is used to select the module's address within 6-11
a PC. It is connected to the address lines A4
- A1 l. The 5-12
addressing range is selected from 128 to 240 decimal. The 4-13
- ..
following figures show the details of the S5-150, S5-135U,
3-14
and S5-115U. 2-15
1-16
All A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
xxxx1sssoooo
module address sub address
Q
X = irrelevant if jumper E-F is removed. If jumper E-F is
installed, All
- A8 should be open. Note that jumper
E-F should only be installed for the S5-210 system.
I = selected or jumper closed. A7 must be closed to have
an addressof at least 128.
s = selectablejumpers. With jumpers A6 - A4 there are eight
different addresses selectable for the module.
o
= representsthe sub 'address, A3 - AO. Each module has
16 internal addresses which are relativeto the madule's
address.
AllA10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Decimal Hex
X X
X X 1 0 0 0 0 0
0
0 128-143~~80-~~8F
X X
X X 1 0 0 1 0 0 0 0 144-159~~90-~~9F
X X
X X 1 0 1 0 0 0 0 0 160-175xxAO-xxAF
X X'
X X 1 0 1 1 0 0 0 0 176-19lxxBO-XXBF
X X X X
1 1 0 0 0 0 0
0 192-207xxCO-XXCF
X
X X X
1 1 0 1 0 0 0 0 208-223xxDO-XXDF
X X
X X 1 1 1
0
0 0 0 0 224-239xxEO-XXEF
X X X X
1 1
1 1 0 0 0 0 240-255xxFO-XXFF
X = irrelevant itjumper E-F is open. If jumper E-F is closed,
jumpers must be open.
1
= jumper closed.
0 =jumper open.
For the S5-210 system busthe addressing range is between
FOlxH and FFFxH. A maximum of 255 modules may be
addressed.
All A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ss ssssss0000
module address sub address
Jumper E-F should be installed for the S5-210 system.
s = selectablejumpers. With jumpers All - A4 there are 255
different addresses selectable for the module.
o
= represents the sub address, A3 - AO. Each module has
16 internal addresses, which are relativeto the module's
address.
2.2 Switch S2 Group Interrupts
NOTE:
If your PC is not the S5-150S, all jumpers on Switch S2
should beopenandthe settingof switch
S2 isnotnecessary.
Switch S2 is used inconjunction with the 150s PC. The 150s
does not have a hardware interrupt line on the backplane of
the PC as do the 135U, 115U, andthe 210 PCs. Insteadthe 150
uses IBO (input byte 0) to provide interrupt capabilities. To
allowthe useof IBOthe 242 moduleprovidesspecial circuitry
which allows it to simulate IBO.
The 150ssystem may contain up to eight 242 modules. If the
interrupt capabilities are to be used, each of the modules
used within the PC must be assigneda group interrupt code.
This isaccomplished with switch S2.
The first module used within the PC must beassigned as the
Mastermodule. Ifonly onemoduleisused,itmustbeassigned
as the Master.When an interrupt occurs itwill appear on IBO,
bit 0 for the modulethat iscoded as the Master.
The remainingmodulesusedinthePC willbeassignedaslave
number, slaves
l - 7. These slave numberscorrespond to the
remainingbits in IBO; i.e., slave 2 will be 180.2.
The 150s interrupt system has a priority organization, IBO.0
has the highest priority and IB0.7 has the lowest priority.
This in turn will be true for the 242 modules installed within
the PC. The Masterwill haveinterrupt priorityover the slaves,
slave 1will have priority over slave 2 and so on.
Also used in conjunction with switch S2 will be jumper G-H.
The jumper G-H is used to determine if the module is the
Master or a slave. The following table reflects the correct
settings for each of thr eight possible modules.
IB0.x S2 Jumper Description OBX 'Jumper G-H
Master
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave
7
open
closed
closed
closed
closed
closed
closed
closed

Chapter 2
Module setup Procedures
Coding Rules For The Master Module:
1. Jumper G-H must be open.
2. Jumper 8-9 on S2 must be closed. This will identify the
module as the Master.
3. The remainingjumpers on S2 will be closed, unless there
is a slave module assigned to that jumper; then it should
be open.
Coding Rules For Slave Modules:
1. Jumper
G-H must be closed.
2. Jumper 8-9 on S2 must be open.
3. Only the jumper on S2 for the appropiate slave number
should be closed. The remaining jumpers on S2 must
beopen.
NOTE:.
Because an interruptwill occur on any transition at IBO the
user must program the OBs not to respond when the inter-
ruptsare reset,a transitionfrom
1 to 0.The OBs should only
respond when the transition is from
0 to 1. The following
statements could be installed at the beginningof the OB to
provide interrupt reaction only on a 0 to
1 transition.
OBx
A l 0.x
BEC
Note:
If the
6ES5 242 module is installedand the group interrupts
are used, an input module cannot be assigned to byte
address
0 (IBO). Ifthere isaninputmoduleinstalledwith byte
address
0 (IBO) assigned,thegroupinterruptwill notoperate;
instead,the input module will operate.
2.3 Switch S3 - System Interrupts
Switch S3 provides the module a choice of which system
interrupt itwill be connected to within the PC. The 6ES5 242
can be connected to one of seven different interrupt lines
by closing the proper jumper on switch 53. Which interrupt
is used is dependent on which type of PC the module is
installed in. A brief description of howto handlethe interrupts
for a particular system is given below.
NOTE:
All jumpers on switch
S3 which do not pertainto the system
beingused should be left open.
SS-210
The S5-210 system has four system interrupts available and
a 210 bus interrupt (PL4) available. The program responseto
each of the available interrupts must be written in assembly
language.Theinterrupt handlingsystemfortheS5-210 system
is beyond the scope of this manual and the reader should
refer to the instruction manualfor the S5-210 system.
Jumper Description
8-9 System InterruptIRA'
7-10 System Interrupt IRB'
6-11 System Interrupt IRC'
5-12 System Interrupt IRD'
1-16. 210 Bus InterruptPL4' (EANK')
S5-135U
The S5-135U hasonly onesysteminterruptfor each of thefour
available CPUs. This is
a hardware interrupt, and is handled
by062. Becausethere isjust one interruptfor eachCPU, you
shouldidentifywhich moduleissuedthe interruptbychecking
each of the interrupt information registers of the counter
modules connected to that CPU. This is done inOB2 of each
CPU. Each counter module may be connected to more than
one interrupt; i.e., one counter module may be connected to
the interrupts of CPU 1 and CPU 2, while another counter
module isjust connected to the interrupts of CPU 2.
082 Jumper Description
0 B2 8-9 System interrupt IRA' for CPU 1
OB2 7-1
0 System interrupt IRB' for CPU 2
062 6-11 System interrupt IRC' for CPU 3
OB2 5-12 System interrupt IRD' for CPU
4
S5-115U
The S5-115U has two system interrupts. These are hardware
interrupts, and are handled by two organization blocks. You
have to specify which modules will be connected to which
interrupt, and handle the interrupts via the availavle OBs.
For example, if more than one module is connected to IRA',
theneachof themodulesconnectedmusthavetheirlnformation
Registersreadtodeterminewhich moduleissuedtheinterrupt.
OBx Jumper Description
OB2 8-9 System interrupt IRA'
OB3 7-10 System interrupt IRB'
S5-150
The S5-150 does not use switch S3; instead Group lnterrupt
switch S2 is usedto assign interrupts. When using a S5-150,
all of the jumpers should be open. Refer to the previous
section for interrupt handlingwith the S5-150.

Chapter 2
Module Setup Procedures
2.4 Switch S4 = Gate Signal Conditioning
Switch S4 is used to change the transition direction of the
gate input signals that feed the interrupt system of the
6ES5242module.Thefirst three externalgatesignals, G1-63,
are fed to three of the interrupt lines of the AM 9519 interrupt
controller chip.
This allows use of any of the three external gate inputs to
trigger an interruptfor the module.TheInterruptMaskRegister
must be set accordingly to enable the gate interrupts. Note
also that the external gate signals are first routed through
switch S6.
TheAM 9519 interruptcontroller chip isfirmware programmed
'to allow a 0 to 1transition. You must determine which type
of external gate transition will be used (1 to 0 or 0 to l), and
set switch S4 accordingly.
@
Jumper Description
G1 externalgate input to AM 9519.
G2 external gate input to AM 9519.
G3 externalgate input to AM 9519.
G4 external gate input, not used.
Jumper closed
= 0 to 1transition, rising edge.
Jumper open
= 1 to 0 transition, falling edge.
2.5 Switch S5 - Counter lnput Routing
Switch S5 is used to physically connect the input to each
of thefive counter inputsof theAM 9513toeither theexternal
counter input or the FOUT signal. The external counter input
is routed through optocoupling from the connectors located
onthe front of the module(seesection 2.8.1, PlugConnector).
The FOUT signal is an output of the AM 9513 counter chip
which can be programmed by the user (see section 3.3,
Master Mode Register).
For example, if you connect the counter input of counter
l to
the FOUT signal and you would like to use the FOUT signal
for an input to counter 2, you would specify counter 1 as
the pulse source inthe counter mode register of counter
2.
Counter External Input F2 Scaler (FOUT)
1 1-20 2
- 20
2 3
- 18 4-18
3 5-16 6-16
4 7-14 8
- 14
5 9
- 12 10
- 12
2.6 Switch S6 - Gate lnput Routing
Switch S6 is used to physically connect the input to each of
thefive gate inputs of the AM 9513 to eitherthe externalgate
input or the FOUT signal. The external gate input is routed
through optocoupling fromtheconnectorslocatedonthefront
of the module (see section 2.8.1, Plug Connector). The FOUT
signal is an output of the AM 9513 counter chip which can
be programmed by the user (see section 3.3, Master Mode
Register).
Forexample, if you connectthe gatecontrolinputof counter
1
to the FOUT signal, and you would like to use the FOUT
signal for an input to counter 2, you would specify counter
1asthe pulsesourceinthecounter moderegisterof counter
2.
Gate External Input F2 Scaler (FOUT)
2.7 Jumper Assignments
There are several solder type jumpers which are installed on
the 6ES5 242 module. Their meaningsare listed below.
Jumper Delivery State Description
A
- B closed Usedfor testing
C-D open Usedto enablede coding of
byte
a
E-F closed Usedfor module addressing
in conjunction with swith S1.
G-H open Usedto determine if the
module is a master (open)
or slave (closed).
I-K closed Usedto determine if the
module is resetwith the
system CPKL' signal
L- M open Is used to enable (closed)
the TRAP interrupt routine
stored infirmware for 8085.

Chapter 2
Module Setup Procedures
Plug Connector Block Diagram
2.8 Inputs And Outputs
2.8.1 Plug Connectors
The connection of the 6ES5 242 counter module to the user
inputsandoutputsisaccomplishedviaa%pin plugconnector.
There are five such connectors mounted on the front plate
of the module, one for each of the five counters. (See
Figures 2-1 and 2-2)
9. Counter Ext Volt. (-)
[ fji i 5. Gate Input (-) I
Plug
n
Pin Signal Description
Externally
Supplied
DC
Voltage
8 Counter Outp~t Signal
4. Gate Input Signal
I Indicates Connection for Common Ground
I
1 Shield Cable shield connection
2 lNxM CounterInput
X, M terminal (minus)
7.NOtCiXmCkd 6 3. Counter Input Signal
3 INx CounterInput X, signal
4 Tx
6. Counter Ext. Volt. (+)
Gate Input X, signal 0
2. Counter Input (-)
5 TxM Gate Input X, M terminal (minus
6 AxP
1. Shield
CounterOutput X, externalvoltage
7 not connected
8 Ax CounterOutput X, signal
9 AxM CounterOutput X, externalvoltage (minus)
NOTE:x= 1-5
Figure 2-2 242 Module Plug Connector Pinot
figure 2-1 242 Module Plug Connector Block Diagram
PlugConnector Pinout
Connector
2.8.2 Counter and Gate Inputs
The counter and gate inputs which are connected through
the front connectors of the module are galvanically isolated
by means of optocouplers.The input circuitry is identical for
both types of inputs and can be configured for
TTL levels or
24 vdc levels.
The counter inputs are pulse edge sensitive. The gate inputs
can be programmed in the counter mode (CM) registerto be
either pulse edge sensitive or level sensitive.
Figure 2-3 illustratesthe circuitry of the counter input gates.
The circuit is supplied with an input resistor (Rx) to allow
different input voltage levels to be selected. A capacitor
(W)
can be added to the output to suppress noise spikes. Note
that the counting frequency is affected when capacitors are
added.
*
lNX T-f-q
l NxM
Figure 23Counter & Gate lnput Circuitry

Chapter 2
ModuleSetup Procedures
TTL Level Specifications
The input circuit for lTLlevelsshould bedesignedto provide
a +5 vdc at INx continously, and provide an open collector
configuredcircuit at the lNxMinput, which doestheswitching.
This circuit configuration is show in Figure2-4.
Figure
2-4 Counter & Gate lnputTTL LevelCircuitry
Description Value Notes
INx 4.75 - 5.25 Vdc
lNxM 0.5 -. 0.8 Vdc Low Level
lNxM l maleakage High Level
current
lnput current approx. -6.5 ma lNxM
= 0.4 V, INx = 5 V
lnput Resistance approx. 500 ohm
Rx Jumper
24 Vdc LevelSpecifications
Figure2-5 illustratesthenecessaryconfigurationfor24Vinput
to the gate input circuitry
Figure
2-5 Counter & Gate.lnput 24 V Level Circuitry
Description Value Notes
lNxM 0.0 v
INx 13 - 33 Vdc High Level
INx 35 - +4.5 Vdc Low Level
lnput Current approx. 12 ma lNxM
= OV, INx= 24Vdc
lnput Resistance approx. 2 k ohm
Rx 1,5 k ohm
2.8.3 Counter Outputs
The output of each of the five counters is routed to the plug
connectors on the front of the module. These outputs are
galvanically isolated by means of optocouplers. The outputs
are the equivalent of
P switches and are current limited.
Driving distance is a function of the external voltage source
and, of course, the type of wire used. Distancesof 200 meters
and beyond are attainable. Figure 2-6 illustrates the counter
output circuitry configuration.
Figure
2-6 Counter Output Circuitry
Description
Ax High Level
Ax Low Level
Short Circuit
AxP
Switching Freq
DelayTimes
Low to High
High to Low
RiseTime
FallTime
Value
22v
200 ma
20 - 30V
lOkHz
20 usec
20 usec
1 usec
5 usec
Notes
Residualvoltage approx. 2V
Output Current
= -100 ma
Resident current
= -100 ua
AxP = 24V, AxM = OV, Rext = 0
External supplyvoltage
Rext
= 330 ohm
Rext
= 330 ohm
Rext
= 330 ohm
Re* = 330 ohm
Rext
= 330 ohm
NOTE: Rext
= external loadresistance
2.8.4 Signal Conditioning
The Cx and Rx.numbers for each of the counters and gates
are listed below.
CounterIGate Counter Cx Rx Gate Cx Rx
1 C15 R21 C22 R26
2 C16 R22 C23 R27
3 C1
7 R23 C24 R28
4 C18 R24 C25 R29
5 C19 R25 C26 R30
The values for Cx and the maximum counting frequency are
listed below.
Maximum Counting Freq. Cx value
approx 2000 kHz no capacitor installed
approx 200 kHz 100pf
approx 20 kHz 1 nf
approx 2 kHz 10 nf

Chapter 2
Module Setup Procedures
2.9 Module Pin Out
The 6ES5 242 module is supplied with a 48-pin connector
which conforms to DIN 41612. The pin out of the module is
listed below.
Pin d b
z
2 0 v +5 v
4 PESP
6 ADB 0 CPKL
8 ADB 1 MEMR'
10 ADB 2 MEMW'
12 ADB 3 RDY'
IRA' ADB 4
IRB' ADB 5
IRC' ADB 6
IRD' ADB
7
IRE' ADB 8
IRF ADB 9
.IRG' ADB 10
ADB 11
DB 0
DB 1
DB 2
DB
3
DB 4
DB 5
DB 6
DB
7
PL 4, EANK'
2.1 0 6ES5 242 Module Memory Map
Setting of the physicaladdress of the 6ES5-242 modulewas
discussed inan earliersection. Inthat sectionthe subaddress
was shown to have
16 possible addresses. This section will
map out these 16 subaddresses.
Direct reading and writing operations to the module are
accomplished through peripheral words (PWxx). This is
particulary useful when you need to develop a "custom"
software function. See Chapter 4 for detailed information on
Standard Software Blocks. Exercise extreme caution when
usingthis featurewith standard software, as thesetwo opera-
tions may interferewith each other.
Sub Register name
Address Write Operation
xxxO Control
xxxl not assigned
xxx2 FunctionNumber
xxx3 notassigned
xxx4 lnterrupt Mask - High*
xxx5 lnterrupt Mask - Low*
m6 Master Mode - High*
xxx7 Master Mode - Low*
xxx8 CounterMode - High*
xxx9 Counter Mode - Low*
xxxA Load-High*
xxxB Load-Low*
xxxC Hold - High*
xxxD Hold-Low*
xxxE Alarm - High*
xxxF Alarm - Low"
Registername
ReadOperation
lnterrupt Information
- High
lnterrupt Information
- Low
Error Signal
- High
Error Signal
- Low
not assigned
not assigned
Result Counter 1
- High
Result Counter 1
- Low
Result Counter 2
- High
Result Counter 2
- Low
Result Counter
3 - High
Result Counter
3 - Low
Result Counter 4
- High
Result Counter 4
- Low
Result Counter 5
- High
Result Counter 5
- Low
*: The value inthis register will besentto any of thecounters
specified during the parameterassignment.
NOTE:
The Standard software offering does not read the alarm
i
registerwhen parametersareassignedtocounters 3,4, and 5.

Chapter 3
Register Details And Use
The counter module's operation is totally software driven.
Complete manipulation of the five counters is accomplished
by writing software which set various registers with values
predefined in the module's firmware. In this section, detailed
information is presented on the registers and the selections
available.The registers and their abbreviations are:
lnterrupt Mask Register
- INTM
lnterrupt lnformationRegister
- INTl
Master Mode Register - MM
Counter Mode Register
- CM
Control Register
- CTRL
Function NumberRegister
- FNR
Error Signal Register
- FEM
Result of Counter 1
- El
Result of Counter2
- E2
Result of Counter3
- E3
Result of Counter4
- E4
Result of Counter5
- E5
Load Register
- L
Hold Register
- H
Alarm Register
- A
3.1 INTM - lnterrupt Mask Register
The interrupt mask register allows you to enable or disable
thegroup interrupt(setviaswitchS2)andthesysteminterrupts
(set via switch S3) for each of the interrupts available.
To enable an interrupt, write a logic 1 in the corresponding
bit of the INTM register. The AM 9519 interrupt controller chip
is an edge sensitive device and will generate a group and a
system interrupt when a transition of the enabled interrupt
input is detected.
lnterruptprocessingrequiresaproperlydefinedorganizational
block for the type of PC used to handle these interrupts.
This includes the use of a reset call using the standard
function block which will be described indetail inChapter 4
of this manual. The setting of switches S2 and S3 was
described in Section 2.2 and 2.3.
a INTM - Low Order Byte Subaddress xxx5, Write
Bit 76543210
Z1 22 23 24 25 T1 T2 T3
'I
CounterOUT signals Gate signals
Z1 - 25 = The counter OUT signal from the AM 9513. These
signals must have the CM register set to active
high or active low.
T1 - T3 = The gate input signals for gates 1 - 3. The inputs
may be manipulated by the setting of the S4
switch. See Section 2.4.
INTM - High Order Byte Subaddress xxx4, Write
Bit 15 14 13 12 11 10
. 9 8
REOOOOOO
T
not used
Error Signal
P
Ready Signal
1
= interrupt enabled
2
= interrupt disabled
When theerror signal enablebit of the INTM isset toa logic
1,
a group interrupt will occur when an error occurs inthe FEM
register. You must check the IN1 register to identify the
interrupt within the INTM register, and then check the FEM
registerto identify the initial cause of the interrupt.
When the readysignal enablebitof the INTMissettoa logic 1,
a group interrupt will occur when the 6ES5 242's internal
8085 microprocessor has completed its internal program
processing and is availableto be accessed.
NOTE:
The INTM register is used only to enable the group and
system interruptsforthemodule. Ifan interruptoccurs
it will
appear inthe INTl register, regardless of the setting inthe
INTM register.
Referto Chapter4 for setting the INTM registerwith standard
software blocks. The INTM register can be set using the PA
mode of FB 159. Care must be taken when using the PA
modebecausethe INTMregisterisset eachtimethe PA mode
is usedfor a particular counter.
3.2 INTl - lnterrupt lnformation Register
Theinterruptinformationregisterisusedtostoreanyinterrupts
that mayoccur on the module.The bitassignmentsof the INTI
register are the same as the INTM register. An interrupt is
identified by a logic 1.
When an interrupt occurs, you must read the value of the INTl
register to identify which interrupt has occurred. The INTl
register may be read directly using a "L PWxx" instruction or
by checking the value of the dataword assigned to represent
the INTl register within the data block (defined when using
thestandardsoftware).Thisprogrammingisdescribedinmore
detail inChapter 4 of this manual.
INTM - Low Order Byte Subaddresxxxl
, Read
Bit 7.654321 0
Z1 22 23 24 25 T1 T2 T3
'I
Counter OUT signals Gate signals
Z1 - 25 = The counter OUT signal,fromthe AM 9513.
T1 - T3 = The gate input signals for gates 1 - 3.
INTM - Hig Order Byte Subaddressxxx0, Read
Bit 15 14 13 12 11 10 9 8
REOOOOOO
T
not used
Error Signal
Ready Signal
NOTE:
The INTl register will provide an indication of an interrupt
whenever an interrupt occurs, regardless of the INTM regis-
ter's settings.

Chapter 3
Register DetailsAnd Use
3.3 MM - MasterMode Register (AM 9513)
The MM register is used to enable and perform special
functions commonto each of thefivecounters onthe
AM 9513
counter chip.This sectionwill describethemeaningof eachof
thesefunctions, and howto set the
MM registerto accomplish
the special function.
The
MM register,a 16-bit registerdivided into seven sections,
is used to enable and assign parameters for the various
functions performed bythe
MM register. The bit assignments
of the
MM register and their meanings are listed below.
Refer to Chapter
4 for setting the MM register with standard
software blocks. The
MM register can be set using the PA
mode of FB159. Care must be taken when using the PA mode
because the
.MM register is set each time the PA mode is
usedfor a particular counter.
MM - LowOrder Byte Subaddress xxx7, Write
Bit
7654321 0
...
PulseSource
for Scaler
2
Time
Clock
1 1 Comparator 1
1 comparator 2
MM - High Order Byte Subaddress m6,Write
Bit
15 14 13 12 11 10 9 8
I
ScalingfactorScaler 2
I Scaler 1
Counting mode Scaler
2 enable
3.3.1 Real-Time Clock: MM1 - MM0
The AM 9513 can perform a real-time clock function but this
function is not supported by the
8085 firmware. A custom-
made function block is required to support this feature.
Unlessyou havecreatedthisfunction block, thevalue of
MM1
and MM0 should be 00 to leavethis function disabled.
MM1 MM0 Description
0 0 Real time clock disabled
0 1 Input frequency scaled for 50Hz
1 0 Input frequency scaled for 60Hz
1 1 Input frequency scaled for 100 Hz
3.3.2 Comparators 1 and 2: MM3 - MM2
The comparator function of the AN 9513 will allow Counters 1
and 2 to perform a 16-bit compare function. The actual value
of the counter is compared to the value stored in the alarm
register for the counter.
Enabling the compare function for the counter will enable
special circuitry in the
AM 9513, which will configure the
counter output to go to the active state when the comparison
istrue.Thecomparisonisconsideredtrueonlywhenthevalues
are equal to each other.
When the count value changes from the true state, the output
will again appear in the false state. The active state of the
counter may be set to active high or active low in the CM
register
(CM2 - CMO).
MM3 MM2
Description
X 0 Comparator 1 disabled
X l Comparator 1 enabled
0 X Comparator 2 disabled
1 X Comparator 2 enabled
X = irrelevant
3.3.3 Scaler 2 (FOUT) Pulse Source: MM7 - MM4
Descriptionof pulse source
Output Scaler
1 F1
Counter input l
Counter input 2
Counter input 3
Counter input 4
Counter input 5
Gate input 1
Gate input 2
Gate input 3
Gate input 4
Gate input 5
Output Scaler 1 F1
Output Scaler 1 F2
Output Scaler 1 F3
Output Scaler 1 F4
Output Scaler 1 F5
NOTE:
The reset or default value for MM7 - MM4 is 0000.
3.3.4 Scaler 2 (FOUT) ScalingFactor: MM11 - MM8
The scaling factor of the pulse source signal, which was
@
selected in bits MM7 - mm4, can now be selected using bits
MM11 - MM8. A scaling factor from 1-1 6 may be selected.
Scaler
2 nowscalesthe selected pulsesourcebythe selected
scaling factor. The results is routed to the output of scaler
2
(FOUT).
Scaling Factor
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Chapter 3
Register DetailsAnd Use
3.3.5 Scaler 2 (FOUT) Enable: MM12
This bit of the MM register is usedto enable and disable the
output of scaler 2 (FOUT). The default value of 0 will enable
the FOUT signal.
MM12 Description
0 FOUT enabled
1 FOUT disabled
3.3.6 Scaler 1 Counting Mode: MM1 5
I
This bit is used to set the counting mode of Scaler 1. The
default value of 0 will place the output of Scaler 1 in the
binary counting mode.
I
MM15 Description
0 Scaler 1 in binarycounting mode
1 Scaler 1 in BCD counting mode
Scaler 1 Outputs
- Input Frequency: 2MHz
Output BCD Mode . BinaryMode
F1
:l 2000kHz :l 2000kHz
F2 :l0 2OOkHz :l6 125kHz
F3 :l00 20kHz :256 7.812kHz
F4
:l 000
2 kHz :4096 488.3Hz
F5 :l 0000 200Hz :65536 30.5Hz
3.3.7 Bits MM14 and MM 13
Bits MM 14and MM13 of the MM register are not availableto
the user on the 6ES5 242 module. These bits are used by
the 8085 firmware. The condition of these bits is irrelevant.
3.4 CM -CounterModeRegister (AM 9513)
There are,five CM registers on the AM 9513, one for each
counter. The CM register is used to assign the operation
parametersfor the counters.
The CM register is a 16-bit register that is divided into nine
sections. These ninesectionsare usedto select theoperating
mode of the counter. The bit assignmentsof the CM register
and their meaningsare listed below.
CM-Low Order Byte Subaddresxxx9, Write
Bit 7654321 0
ReloadingSelection
CM-High Order Subaddressxxx8, Write
Bit 15 14 13 12 11 10 9 8
PulseSource
Selection
Pulse EdgeSelection
I Gate Control
3.4.1 Output Selection: CM2 - CM0
Bits CM2 - CM0 of the CM registers allow selectionof several
different counter output modes. The output of each counter
is connected to the'AM 9519 interrupt controller and also to
the respectivefront connector of the module.
CM2 CM1 CM0
0 0 0
0 0 1
0 1 0
0 1
l
l 0 0
1 0 1
1 1 0
1 1 1
TC
= Terminal Count
Description
lllegal
Active high, TC Pulse mode
TC Toggled mode, start low
TC Toggled mode, start high
lllegal
Active low, TC Pulse mode
lllegal
Illegal
DEFINITIONS:
Terminal Count: The point in time where the counter value
reaches a value of zero. This is the point where the counter
output will change state. The following is a listing of the
conditions that will cause TC to occur on the next count.
Counter Value Direction CountingMode
0001 down BCD or,binary
9999 UP BCD
FFFF UP binary
When using the counter outputs of the AM 9513 you must
remember that all outputs switch on TC, which means that
all counting operationsdepending on a switched output must
either count down to TC, or count up to TC, to achieve the
expected output.
TC Pulse mode: This mode will produce an output when the
count value equalszero. The output will becomeactiveonthe
leadingedge of TC. The width of the output pulsedependson
thetimethecounterisatazerovalue.Activehighandactivelow
simplymeanthe stateof the pulseduringthetimethecounter
is at zero value.
TC Toggle mode: This mode will produce an output level
insteadof a pulse. This levelwill toggle betweenthe high and
the low states on the trailing edge of TC.
1 Special Function enable

Chapter 3
Register DetailsAnd Use
3.4.2 Counting Direction: CM3
This bit is used to determine the counting direction of the
counter.
CM3 Direction
0 Down counting
.l Up counting
3.4.3 Counting Mode: CM4
This bit isusedto determinethecountingmodeof thecounter.
CM4
. Mode
0 Binarycounting
1 BCD counting
NOTE:
Bits
CM7 - CM5 and CM15 - CM13 are used together to
determine a particular counter mode. These modes will be
described indetail later inthis section. First, eachofthe bits
mentionedabove will
be describedseparately.
3.4.4 Countig Type: CM5
This bit is used to determine which type of counting is to
be used.
CM5 Type
0 Count once (one-shot)
1 Count repetitively (periodic)
Count once: This type of counting will allow the counter to
count until TC occurs. At TC the counter will be disarmed
automatically.
Count repetitively:This type of countingwill allow the counter
to count inthe mode specified until disarmed.
3.4.5 Reloading Selection: CM6
This bit providesa selection of which register the counter will
be loaded by when TC occurs. The selection of the Hold
register or the Load register is dependent on the counter's
operating mode. These modes are described indetail later in
this section.
CM6 Reloadingregister
0 Reloadingfrom the Load register
1 Reloadingfrom the Load or Hold registers
3.4.6 Special Function Enable: CM7
This bit is used to enable or disable special functions which
areassociatedwithgatecontrol, bitsCM1
5 -CM13. Thesetting
of this bitisagaindependentonthecounter's operatingmode.
CM7 Gate Control
0 Special Function disabled
1 Special Function enabled
3.4.7 Pulse Source Selection: CM11 - CM8
CM11 CM10 CM9 CM8 Description of pulse source
Counteroutput n-l
Counter input
l
Counter input 2
Counter input 3
Counter input 4
Counter input 5
Gate input 1
Gate input 2
Gate input 3
Gate input 4
Gate input 5
Output scaler 1 F1
Output scaler 1 F2
Output scaler 1 F3
Output scaler 1 F4
Output scaler
1 F5 C
3.4.8 Cascading Counters
Counter output n-l "0000" can "feed"theoutput of a previous
counter into the input of the next counter, according to the
following flow:
Counter PreviousCounter
Input Output
1 5
2 1
3 2
4
3
5 4
3.4.9 Pulse Egde Selection:.CMI2
This bit will set edge triggering selection on the input pulse
that begins the counting process.The choices are:
CM12 Counting Egde
0 The leadingedge of the inputtriggers counting
1 The trailing edge of the inputtriggers counting
3.4.10 Gate Control Selection: CM15 - CM13
Bits CM15 - CM13 are used to configure the gate control
options.
CM15 CM14 CM13 Gate Control
0 0 0 No gate control
0 0 1 counter output (TC) n-l, active high
0 1
0 Gate n+l, active high level
0 1 1 Gate n-l, active high level
1 0 0 Gate n, active high level
1 0
1 Gaten, active low level
1 1 0 Gate n, active high edge
l 1 0 Gate n, active low edge

Chapter 3
Register DetailsAnd Use
3.5 Counter Modes
The AM 9513 can implement numerous counting modes
through software commands. These modes can be selected
by using the proper codes in CM15
- CM13 and CM7 - CM5.
For more details on each of the modes including waveform
diagrams, the readershould referto the AM 9513 data sheet.
Some of the modes do not exist or are not supported by the
6ES5 242 module.Modesthat maynotbeusedare:M, P, T, U, W.
The name of each of the modes availableis listed below.
Mode
A
B
c
D
E
F
G
H
I
J
K
L
N
0
Q
R
S
v
X
Title
Software triggered with no hardware gating
Software triggered with level gating
Hardwaretriggered strobe
Rate generatorwith no hardwaregating
Rate generatingwith level gating
Non-retriggerableone-shot
Software triggered delayed pulse One-shot
Software triggered delayed pulse one-shot with
hardware gating
Hardwaretriggered delayed pulse strobe
Variable duty cycle rate generatorwithout hardware
. .
gating
Variable duty cycle rate generator with hardware
gating
Hardwaretriggered delayed pulse one-shot
Software triggered strobe with level gating and
hardware retriggering
Software triggered strobe with edge gating and
hardware retriggering
Rate generatingwith Synchronization
Retriggerableone-shot
Selectable reloading source
Frequencyshift keying
HardwareSave
3.5.1 ModeA
Counter Register Setup
CM1
5 CM1 4 CM13 CM7 CM6 CM5 Special Function:
I
not enabled
CountingType:
Count once
000 0 0 0 Reloading:
Load Register
This mode will allow the counter to start counting when an
ARM command is received. The counter will reloadfrom the
Loadregisterand count untilTC occurs. Countingwill resume
when the ARM command is received again.
3.5.2 Mode B
Counter Register Setup
CM15 CM1
4 CM13 CM7 CM6 CM5 Special Function:
not enabled
CountingType:
Count once
LEVEL
0 0 0 Reloading:
Load Register
This mode is the same as mode A with the exception that
i)
the counter will only be allowed to count when the gate input
is in itsactive state. This allows the user to shut the counting
process off by placing the gate input to an inactivestate.
3.5.3 Mode C
Counter RegisterSetup
CM15 CM1
4 CM13 CM7 CM6 CM5 Special Function:
not enabled
CountingType:
Count once
EDGE
0 0 0 Reloading:
Load Register
This mode is again the same as mode A. The difference is
that this mode will only allow the counter to start counting
upon receiving the first active edge from the gate input after
the counter is armed. Once the counting process begins,
other gate inputedges are ignored.Thecounterwill stopatTC.
3.5.4 Mode D
Counter Register Setup
CM15 CM1
4 CM13 CM7 CM6 CM5 Special Function:
not enabled
CountingType:
Count repetitivey
0 0 0 0 0 1 Reloading:
Load Register
This mode once started will continuous count to TC then
reload from the Load register and count to TC again. It is
not affected by gate control. It can be used to generate
waveforms whose period, betweenTCs, is determinedbythe
value inthe Load register.
3.5.5 Mode E
Counter RegisterSetup
CM1
5 CM1 4 CM13 CM7 CM6 CM5 Special Function:
not enabled
CountingType:
Count once
L E V E L
, 0 0 1 Reloading:
Load Register
This mode is the same as mode D with the exception that
the output will only be enabled while the gate input is in an
active state. This allows you to stop and start the output
waveform bydisabling/enabling the gate input.
.
3.5.6 Mode F
Counter RegisterSetup
CM15 CM1
4 CM13 CM7 CM6 CM5 Special Function:
not enabled
CountingType:
Count once
EDGE
0 0 1 Reolading:
LoadRegister
The counter inthis mode, after it is armed, will start counting
when the first gate edge is received. If another gate edge
occurs it will be ignored once the counter is started. The
counter will stop when TC occurs and reload from the
Load register. The counter will remain stopped until the next
gate edge occurs after the counter has stopped.

Chapter 3
Register DetailsAnd Use
3.5.7 Mode
G
Counter Register Setup
CM15 CM14 CM13 CM7 CM6 CM5 Special Function:
not enabled
Countig Type:
Count once
000 0 1 0 Reloading:
Load or Hold Register
Inthis mode the counter will count to TC twice, once armed.
The counter will initially be loaded from the Load register.
Once counting has started and the counter reaches TC the
first time, the counter will reload from the Hold register and
proceed to count until TC is again reached. After the second
occurrence of TC, the counter will automatically disarm and
reloadfrom the Load register.
3.5.8 Mode H
Counter Register Setup
CM15 CM14 CM13 CM7 CM6 CM5 Special Function:
not enabled
Counting Type:
Count once
LEVEL
0 1 0 Reloading:
Load Registe
This mode is the same as mode G with the exception that
the counter will only count while the gate input is active.
The counter will count to TC twice. Reloadingoccurs the first
time from the Hold register and the second time from the
Loadregister. The counting process will stop afterthesecond
TC is reached.
3.5.9 Mode I
Counter RegisterSetup
CM15 CM14 CM13 CM7 CM6 CM5 Special Function:
not enabled
Counting Type:
Count once
EDGE
0 1 0 Reloading:
Load Register
This mode also performs the same as mode G with the
exception that the counter, once armed, will start counting
with thefirst active edge received at the gate input. Oncethe
countinghasstartedanyothersignalsappliedtothegateinput
are disregarded. Once the counter has counted to TC twice,
itwill haveto be armed and another signal applied to the gate
input in order for it to start the counting process over.
This modeallowsyoutocreatean outputwaveform which has
two differentcycletimes.Thecounter, oncestartedbyanARM
command, will count continuously until it is stopped by a
DISARM command. The counter will first be loaded with the
value in the Hold register and will then count until TC is
reached. Upon occurrence of TC, the counter will be loaded
from the Load register. Each time TC is reached the counter
will alternate between loading from the Hold and the Load
registers.
3.5.11 Mode K
Counter Register Setup
CM15 CM14 CM13 CM7 CM6 CM5 Special Function:
not enabled
CountingType:
Count once
LEVEL
0 1 1 Reloading:
Load Register
@b
This mode is the same as mode J with the exception that
the gate control is used to enable counting. With the gate
input active the counter will count all input pulses to it. With
thegate inputinactivethe counterwill ignoreany inputpulses
to it. Once armed, the counter will be loaded from the Hold
register and on the next occurrence of TC will load from the
Load register. This alternating loading will continue until the
counter receivesa DISARM command.
3.5.12 Mode L
Counter Register Setup
CM15 CM14 CM13 CM7 CM6 CM5 Special Function:
not enabled
CountingType:
Count once
EDGE
0 1 1 Reloading:
Load Register
This mode operates the same as mode
K with the exception
that the counter, once armed, will start counting when an
active edge is applied to the gate input. After the first TC, the
counter will load from the Hold register and count to until
the second TC. At the second TC, the counter will load from
the Load register and stop. The counter will start counting
again when the next active edge is applied to the gate input,
thus starting the count cycle again.
3.5.10 Mode J
Counter RegisterSetup
CM15 CM14 CM13 CM7 CM6 CM5 Special Function:
not enabled
Counting Type:
Count repetitively
000 0 1 1 Reloading:
Load Register

Chapter 3
Register Details And Use
3.5.13 Mode N
Counter Register Setup
CM15 CM14 CM13 CM7 CM6 CM5 Special Function:
enabled
CountingType:
Count once
LEVEL 1
0 0 Reloading:
Load Register
This counting mode allows you to trigger the counter via
software to start the counting cycle and use a hardware
retriggerthereafter. Once counting has started, all pulsesfed
to the counter will becounted if thegate input isactive (level).
When the counter reaches TC the counter will disarm and
reloadfrom the Load register.
Counting will resume with the issuing of an ARM command.
The gate input will nowfunction differently than it did before.
When an activeedgeisreceivedat the gate inputthe counter
will store the counter contents into the Hold register.
The first active edge-received at the counter input while the
gate input is active will cause the counter to reload from the
Loadregister. The secondactive edge receivedatthe counter
inputwhile the gate isactivewill cause the counter to resume
counting. The counter will operate is this fashion until
disarmed.
3.5.15 Mode 0
Counter Register Setup
CM15 CM14 CM13 CM7 CM6 CM5 Special Function:
not enabled
Counting Type:
Count once
EDGE 1
0 0 Reloading:
Inthis modethe counter must bearmed beforecounting can
occur.Oncearmedthecounterwillcountallactiveedgesatthe
counter input while the gate input is active. The counter will
count to TC repetitively.
Thecounter will bereloadedfromtheLoadregisteroneachTC.
Thecounter may behardwareretriggeredbyplacinganactive
edge at the gate input. When retriggered, the contents of the
counter will be stored into the Hold register. With the gate
level active, the first active edge input to the counter will
reloaded the counter with the contents of the Load register.
The second edgewill cause counting to resume.
3.5.1 6 Mode R
Counter RegisterSetup
CM15 CM14 CM13 CM7 CM6 CM5 Special Function:
not enabled
CountingType:
Count repetitively
EDGE 1
0 1 Reloading:
Load Register
This mode is similiar to mode
Q. The difference is that the
input to the gate is edge-sensitive instead of level-sensitive.
Once armed, the counter will count until TC, at which time it
will stop and be reloadedfrom the Load register.
Countingwill beresumedwhenthefirst activeedgeisreceived
at the gate input. The counter will be retriggered on each
occurrence of an active edge while the counter is counting.
Thisretriggeringsequenceincludessavingthecontents of the
counter to the Hold register. The counter will be reloaded
from the load register when the first active edge input is
received at the counter input.Thecounting will resumewhen
the second active edge is received.
h@
the gate input, to an armedcounter. The counter once started CM15
CM14 CM13 CM7 CM6 CM5 Special Function:
a will count to the first occurrence of TC, at this time it will not enabled
disarm and reloadfrom the Load register. CountingType:
A new ARM command and an active edge input at the gate
input must used to start the counter again. The counter will
nowberestarteduponeachoccurrence of anactiveedgeinput
to the gate input (hardware retrigger).
When an active is received the contents of the counter will
be placed inthe Hold register. Upon receiving the first active
edge at the counter input after retriggering, the counter will
be reloadedfrom the Load register.The next active edge will
start the counting process again.
3.5.15 Mode Q
CounterRegisterSetup
CM15 CM14 CM13 CM7 CM6 CM5 Special Function:
not enabled
Counting Type:
Count repetitively
LEVEL 1
0 1 Reloading:
Load Register
Count once
0 0 0 1 1 0 Reloading:
Load Register
In this mode the gate input is used only to determine which
registerwill loadthe counter.The gate inputinthis modedoes
not control counting operations. When the gate input is high
the Hold (High-Hold) register is used, and when the gate is
low the Load (Low-Load) register is used. Once armed, the
counter will count to TC twice, each time reloading from the
register selected. Once the second TC has occurred, the
counter will disarmitself.A newARM commandwill berequired
to start the counter cycle again.

Chapter 3
Register DetailsAnd Use
3.5.1
8 Mode V
Counter Register Setup
CM15CM14 CM13 CM7 CM6 CM5 Special Function:
not enabled
Counting Type:
Count re~etitivelv
000 1 1 1 Reloading:
Load Register
In this modethe gate input isused, as inmodeS, to determine
which registerwill loadthe counter. Thecounter willbeloaded
from the Load register when the gate input is low, and from
theHoldregisterwhen the gate input ishigh.Thecounter will
be loaded when a LOAD command is issued, or when a TC
occurs. The counter will count repetitively once it is started.
A DISARM command is requiredto stop the counter.
3.5.1 9 Mode X
HardwareSave (available inAM 9513 A only)
CM1
5 CM14 CM13 CM7 CM6 CM5 Special Function:
enabled
Counting Type:
Count repetitively
EDGE 1 1 1 Reloading:
Load Register
Mode
X, providesahardwaresamplingof thecounter contents
without interruptingthe count.A LoadandArm commandor a
Load command followed by an Arm command is required to
initialize the counter. Once armed, a Gate edge starts the
counting operation; gate edges applied to a disarmedcounter
are disregarded. After application of theTriggering Gate edge
the counter will count all qualified source edges until the first
TC, irrespectiveof the gate level.All gateedges applied during
thecounting sequencewill storethe current count intheHold
register, but they will not interrupt the counting sequence.
On each TC, the counter will be reloaded from the Load
register and stopped. Subsequent counting requires a new
triggering Gate edge; counting resumes on the first source
edge following the triggering Gate edge.
3.6 CTRL - Control Register
There isonly one control register for the module.Itis usedto
assign parameters and manipulateeach of the counters. The
CTRL register must be addressed by peripheral byte (PBxx)
and is only available as a write operation. If the user is going
to use the standard software (FB159), the CTRL register will
not be addressed directly. A description of each of the
functions is given in the preceding sections, along with the
equivalent "BEFn parameterassignmentsfor FBI59. FBI59 is
described inChapter4.
NOTE:
Because of the processing time required by the
6ES5 242
module when a control word is received, you must allow a
period of
500 microseconds for the moduleto process the
control word.
Ifthemodulereceivesanother controlword inless than
500
microseconds, the first processwill be interrupted. You can
test the Ready bit of the INTl register to be sure that the
module has processed its last control word and isavailable
for communication.
CTRL
- Byte Subaddres xxx0, Write
Bit 7 6 543210
I I
Control Words Counter Selection
3.6.1 Control Words: CTRL7 - CTRL5
These three bits are used to determine which function will
be performed.
CTRL FBI59 Title and Description
7 6 5 "BEF"
000 PA Parameterassignment;theparametersfor
the selected counters will betransferred
from transfer memory areaonthe module
to the counters.
001 ST Start counter; the selected counters will
be started. This is a software start.
010 L0 Load counter; the selected counters will
beloadedfromeithertheLoadortheHold
register depending on which counting
mode is used.
011 LS Load
8 Start counter; the selected
counters will be loaded and started in
the same operation. This can also be
considered an ARM command for a
counting modewith a hardware trigger.
100 CO Copy H to E; for the selected counters,
the contents of the Hold register will be
transferred to the counter.
101 SA Save counter; for the selected counters,
the contents of the counter will be
transferred to the Hold register. This
operation does not affect the operationof
the counter.
110 SP Stopcounter;theselectedcounterswill be
stoppedor disarmed. DISARM command.
111 Addition functions oftheCTRLregisterare
called. These functions are described in
the next section. Bits4 thru
0 of theCTRL
register perform differently than they do
inthe abovementioned funtions.

Chapter 3
Register Details And Use
3.6.2 Additional Functions
The additionalfunctions of the CTRL register are listed below.
It is necessaryfor bits 7
- 5 to set to "1" to call the additional
functions.The equivalent "BEF" titles for FBI59 are also listed
for each of the functions.
CTRL FBI59 Title and Description
4 3 2 1 0 "BEF"
00001 RB Reset module; this function will per-
form an overallresetof themodule.All
parameters assigned will be deleted.
00010 FL Loadpredefinedfunction; thisfunction
will load the predefined function
whose number has been previously
placed in the FNR register. See
Section 3.7 for a detailed description
of the FNR register.
00011 RI Reset interrupts; this function is used
l
to reset the interrupts in the INTl
register to "0". See Section 3.2 for a
I detailed description on the INTl
register.
l 01001 S1 step counter; this function will step
1 01010 S2 theselectedcounter byacountof one.
l
01011 S3 The counter will be incremented or
01
100 S4 decrementeddepending on thevalue
01101 S5 of bit CM3 for the selected counter.
NOTE:
All codes not described above are illegal.
3.6.3 Counter Selection: CTRL4 - CTRLO
The counter selection bitsCTRL4 - CTRLO, are usedfor those
functions described in Section 3.6.1. These bits are not used
for counter selection when the additional functions of the
CTRL register are used (see the previous section).
CTRL Bits'4 3
2 1 0
Counter 5 4 3 2 1
0 = not selected 1 = selected
When using the functions described in Section 3.6.1, any or
all of the counters may beselected bysettingthe appropriate
bits. To ensure the proper operation of a particular function,
it is important to ensure that all of the registers involved
have been loaded or preset before executing the function.
For example, if you would like to perform a start operation
on counters 1 and
3, it is important to have the appropriate
values in the CM, MM, Load, and Hold registers for each of
the counters prior to the execution of the start function.
When executing a predefined function, it.is first necessary
to store in the FNR register the function number that will be
performed.Then byusingtheControlRegister,the predefined
function may be loaded into the counter.Thiswas described
inthe previoussection. Ifyouare usingthe standardsoftware,
then the "BEF" parameter of FBI59 will be set to
"R" to
performa load of a predefined function.
Thefirmware for the module contain five predefinedfunctions
(firmware version V04). These function numbers and their
meanings are described below.
FNR Description
OOH Test for AM 9513, counter chip
01H Test module RAM
02H Test module EPROM
03H Test for
AM 9519, interrupt controller
04H LOZl
The LOZl function will cause Counters1-3 to be loaded from
Load register after an interrupt has occurred from the gate
interrupts 1
- 3. These gate interruptsare causeddirectly from
the gate inputs
l - 3 and are maskedbythe INTMregister.See
Section 3.1 for more informationabout the INTM register.
Theoperation of the first four function of the V04 firmware can
be checked by reading the FEM register. The FEM register
isdescribed inthe next section.
3.8 FEM - Error Signal Register
The FEM register allows you to determine which error has
occurred when the Error bit of the INTl register is set (INTI,
bit 14).
FEM
- Low Order Byte Subaddressxxx3, Read
Bit 7654321 0
l
TTTTTTT
IN NR CO PA TI R0 RA
I not assigned
FEM
- High Order Byte Subaddressxx2, Read
Bit 15 14 13 12 11 10 9
8
I
not assigned
0 = no error l = error
3.7 FNR - Function Number Register
TheFNR registerisusedto point the moduletothepredefined
function that is to be performed. These predefined functions
can be stored in a 4K byte user EPROM installed on the
module. Up to 254 function numbers can be assigned (OOH
thru FEH). There are also severalpredefinedfunctions located
inthe modulesfirmware. Thesefunctions aredescribed below.

Chapter 3
Register Details And Use
3.8.1 Error Descriptions
FEM Name Title & Description
Bit
0 RA RAM test; will be set if an error has
occurred while performing FNR 01H
1 R0 EPROM test; will be set if an error has
occurred while performing FNR 02H
2 TI AM 9513 test; will be set an error has
occurred while performing FNR OOH
3
P A Parameter assignment; will be set if a
parameter has been assigned incorrectly
4 CO Command;will beset if an incorrect control
word has been used inthe CTRL register
5 NR Functionnumber; will beset if apredefined
function that does not exist isstored inthe
FNR register
6 IN
AM 9519 test; will be set if an error has
'-' occurred while FNR 03H
7-15 not assigned.
3.9 Result Of Counter Registers
The Result of Counter registers are 16-bit registers that allow
you to read the current counter value. The counter contents
are transferred to the transfer memory area of the module
andare then availableto the user. Readinga resultof counter
register does not affect the counter operation.
While using the standard software, the "BEF" parameter of
FBI59 will be "LE" in order to read the result of counter
registers. This parameter is described in detail in Chapter 4
of this manual.
Counter Add
1 xxx6
xxx7
2 xxx8
xxx9
3 XXXA
XXXB
4 xxxc
xxxD
5 xxxE
xxxF
Byte Description
High El;Resultof Counter Register 1
Low
High E2; Result of Counter Register2
Low
High
E3; Result of Counter Register 3
Low
High E4; Result of Counter Register 4
Low
High E5; Result of Counter Register 5
Low