Toshiba TMP91C824F Product guide

REV2.6July. 12, 2002
Rev. 2.6 12/July/2002
16bit Micro controlle
r
TLCS-900/L1 series
TMP91C824F
Data Book

contents
Table of Contents
TLCS-900/L1 Devices
TMP91C824F
1. OUTLINE AND DEVICE CHARACTERISTICS ……………………… 91C824-1
2. PIN ASSIGNMENT AND PIN FUNCTIONS ……………………… 91C824-4
3. OPERATION …………………………………………………………91C824-9
3.1 CPU …………………………………………………………………… 91C824-9
3.2 Memory Map ………………………………………………………… 91C824-11
3.3 Triple clock, Stand-by function, Noise reduction ………………………… 91C824-12
3.4 Interrupts ……………………………………………………………………91C824-36
3.5 Functions of Ports …………………………………………………………… 91C824-51
3.5.1 Port 1 ……………………………………………………………… 91C824-55
3.5.2 Port 2 ……………………………………………………………… 91C824-56
3.5.3 Port 5 ……………………………………………………………… 91C824-58
3.5.4 Port 6 ……………………………………………………………… 91C824-61
3.5.5 Port 7 ……………………………………………………………… 91C824-62
3.5.6 Port 8 ……………………………………………………………… 91C824-66
3.5.7 Port B ……………………………………………………………… 91C824-67
3.5.8 Port C ……………………………………………………………… 91C824-70
3.5.9 Port D ……………………………………………………………… 91C824-73
3.6 Chip Select / Wait Controller ……………………………………………… 91C824-78
3.7 8-bit Timers(TMRA) ……………………………………………………… 91C824-88
3.8 Memory Management Unit ……………………………………………… 91C824-108
3.9 Serial Channel ……………………………………………………………… 91C824-119
3.10Serial Bus Interface ………………………………………………………… 91C824-151
3.11 Analog / Digital Converter ………………………………………………… 91C824-179
3.12 Watch Dog Timer ………………………………………………………… 91C824-189
3.13 RTC ………………………………………………………………………… 91C824-195
3.14 Melody / Alarm Generator ………………………………………………… 91C824-209
4. ELECTRICAL CHARACTERISTICS ……………………… 91C824-215
5. TABLE OF SFR ……………………………………………………… …91C824-227
8. PACKAGES …………………………………………………………………… 91C824-252

Data Book modification history
Rev./Date page Modification item Reason
109 Bank Operation S/W Example in MMU
218 Recommended Crystal oscillation Circuit
165 Stop condition generation
Rev12/Mar-15-2001
166 Timing diagram for TMP91C824 Restart
Rev14/July-16-2001 12-24 DFM(triple cock modify)
17,240 EMCCR3
159,168
Add ed the sentence and diagram at SBI
155 Modify bit6(TRX)
Rev14/July-26-2001
114 Added the diagram and sentence of MMU
Rev21/August-21-2001 14 CPU: modify the figure
Rev22/September-21-2001
222 Electric Specification
Rev22/September-7-2001 226 Murata factory URL added
Rev23/October-26-2001 217 33MHZ AC added
216 Syntax err
“2V SLOW ICC”-> “2V NORMAL ICC”
Unit “uA”-> “mA”
Rev24/January-18-2002
221 Spec modify
AD converter
IREF max 1.20mA -> 1.35mA
contents
Remove “TENTATIVE”of ELECTRICAL
CHARACTERISTICS
1Add the comment about JTMP91C824
Modify the frequency of Micro DMA Change the reference
2Add the comment about package Mistake
16,240 Modify the input frequency of (DFMCR1) Mistake
29 Modify the name SBI0BR1àSBI0BR0 in the
table 3.3.2 Mistake
30,251 Add the limitation about HALT mode Mistake
*Important
matter
48,236 Add the comment to the register IIMC bit6
Mistake
55 Modify the comment in the figure Mistake
87 Add the figure for connecting SRAM Shortage
97,98 Modify WàR/W and remove the note Mistake
100,104
106 Modify the name of the register in the program P7àPB Mistake
146 Modify the name of the register in the
program P9àPC Mistake
208 Add the limitation about RTC Mistake
*Important
matter
212 Modify the name of scale in the table Change
expression
226 Change the comment about MURATA at
the bottom Change expression
Rev2.5/June-21-2002
240 Remove the note Mistake
15,239 Add the word “IDLE1”to the bit0 of
(SYSCR2) register MistakeRev2.6/July-12-2002
30,251 Add the INTALM0 to 4 in the(note) Mistake
※Each page number depends on the revision when it’s made.

TMP91C824
91C824-1
CMOS 16-Bit Microcontrollers
TMP91C824F/JTMP91C824-S
1. OUTLINE AND FEATURES
TMP91C824F is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale
equipment.
TMP91C824F comes in a 100-pin flat package and a 100-pad Dice form. JTMP91C824-S is a chip form
product.
Listed below are the features.
(1) High-speed 16-bit CPU (900/L1 CPU)
• Instruction mnemonics are upward-compatible with TLCS-90
• 16 Mbytes of linear address space
• General-purpose registers and register banks
• 16-bit multiplication and division instructions; bit transfer and arithmetic instructions
• Micro DMA: 4 channels (0.5 µs/2 bytes at 33 MHz)
(2) Minimum instruction execution time: 121 ns (at 33 MHz)
(3) Built-in RAM: 8 Kbytes
Built-in ROM: None
(4) External memory expansion
• Expandable up to 106M bytes (shared program/data area)
• Can simultaneously support 8-/16-bit width external data bus
…Dynamic data bus syzing
• Separate bus system
(5) 8-bit timers: 4 channels
(6) General-purpose serial interface: 2 channels
• UART/Synchronous mode: 2 channels
• IrDA Ver.1.0 (115.2kbps) mode selectable: 1 channel
(7) Serial bus interface: 1 channel
• I2C bus mode/clock synchronous mode selectable
Purchase of TOSHIBA I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components in a
n
I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and
Reliability Assurance / Handling Precautions.
• TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when
utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product
could cause loss of human life, bodily injury or damage to property. In developingyour designs, please ensure that TOSHIBA products are used
within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions
set forth in the TOSHIBA Semiconductor Reliability Handbook.
• The products described in this document are subject to foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA
CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is
granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice.
980508TBA1

TMP91C824
91C824-2
(8) Timer for real-time clock (RTC)
• Based on TC8521A
(9) 10-bitA/D converter : 8 channels
(10) Watch dog timer
(11) Melody/Alarm generator
• Melody: Output of clock 4 to 5461Hz
• Alarm: Output of the 8 kinds of alarm pattern
• Output of the 5 kinds of interval interrupt
(12) Chip select/Wait controller: 4 channels
(13) Memory Management Unit
• Expandable up to 106M bytes (4 local area/8bank method)
(14) Interrupts: 37 interrupts
• 9 CPU interrupts: Software interrupt instruction and illegal instruction
• 23 internal interrupts: 7 priority levels are selectable
• 5 external interrupts: 7 priority levels are selectable (among 4 interrupts are selectable
edge mode)
(15) Input/output ports: 35 pins (@External 16-bit data bus memory)
(16) Stand-by function
Three Halt modes: Idle2 (programmable), Idle1 and Stop
(17) Triple-clock controller
• Clock doubler (DFM) circuit is inside
• Clock gear function: Select a High-frequency clock fc/1 to fc/16
• RTC (fs=32.768kHz)
(18) Operating voltage
• VCC = 2.7 V to 3.6 V (fc max = 33 MHz)
• VCC = 1.8 V to 3.6 V (fc max = 10 MHz)
(19) Package
• 100-pin QFP: LQFP100 - P -1414 - 0.5D
• Chip form supply also available. For details, contact your local Toshiba sales
representative.

TMP91C824
91C824-3
Figure 1.1 TMP91C824F Block Diagram
8KB RAM
CPU (TLCS-900/L1)
PC
10-BIT 8CH
A/D
CONVERTER
H-OSC
SIO/UART/IrDA
(SIO0)
8BIT TIMER
(TMRA0)
32 bit F
SR
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
IX
IY
IZ
SP
TXD0
(
PC0
)
RXD0 (PC1
)
TXD1
(
PC3
)
RXD1 (PC4)
DVCC [3]
DVSS [3]
X1
X2
D0 toD7
A0 to A7
A8 to A15
P10 to P17(D8 to D15)
P20 to P27
(A16 toA23)
A
N0 to
A
N7
(P80 to P87)
AVCC, AVSS
VREFH, VREFL
SCOUT(PD5)
RESET
AM0
AM1
WDT
(Watch
DogTimer)
Clock Gear,
Clock Doubler
SIO/UART
(SIO1)
RD
WR
HWR(P52)
WAIT (P53)
BUSRQ (P54)
BUSAK(P55)
R/W (P56)
L-OSC
EMU0
EMU1
PORT 5
CS/WAIT
CONTROLLER
(4-BLOCK)
PORT 2
CS0 toCS3
,CS2A〜CS2E
INTERRUPT
CONTROLLER
INT0 to INT3
MELODY/
ALARM-OUT MLDALM(PD7)
8BIT TIMER
(TMRA1)
TA1OUT (PB1)
8BIT TIMER
(TMRA2)
8BIT TIMER
(TMRA3)
TA3OUT (PB2
)
( ) : Initial Function After Reset
B C
D E
H L
ADTRG(P83)
SCLK1/ CTS1(PC5
)
(P60 to P67)
PORT 1
PORT 6
PORT 8
PORT B
PORT C
PORT D
(PB3 to PB6),
SCLK0/CTS0 (PC2)
OPTRX0,SCK
(
P70
)
OPTTX0,SO/SDA
(P71) SERIAL BUS
I/F(SBI)
SI/SCL
(P72
)
RTC ALARM,MLDALM(PD6)
XT1
XT2
TA0IN (PB0)
NMI
MMU

TMP91C824
91C824-4
2. PIN ASSIGNMENT AND PIN FUNCTIONS
The assignment of input/output pins for the TMP91C824F, their names and functions are as follows:
2.1 Pin Assignment Diagram
Figure 2.1.1 shows the pin assignment of the TMP91C824F.
VREFL
TMP91C824
QFP100
TOPVIEW
1
5
10
15
20
25
30
35
40
45 50
55
60
65
70
75
80
85
90
95
100
AVSS
P80/AN0
P81/AN1
P82/AN2
P83/AN3/ADTRG
P84/AN4
P85/AN5
P86/AN6
P87/AN7
AVCC
P70/SCK/OPTRX0
P71/S0/SDA/OPTTX0
P72/SI/SCL
TA0IN/PB0
TA1OUT/PB1
TA3OUT/PB2
INT0/PB3
INT1/PB4
INT2/PB5
INT3/PB6
P55/BUSAK
DVCC1
A11
A12
A13
A14
A15
P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
DVCC2
NMI
DVSS2
P26/A22
P27/A23
P17/D15
P16/D14
P15/D13
P14/D12
P13/D11
P12/D10
P11/D9
P10/D8
D7
D6 D5
D4
D3
D2
D1
D0
PD7/MLDALM
PD6/ALARM/MLDALM
PD5/SCOUT
SCLK1/CTS1/PC5
RXD1/PC4
TXD1/PC3
SCLK0/CTS0/PC2
RXD0/PC1
TXD0/PC0
EMU1
EMU0
XT2
XT1
RESET
AM1
X1
DVSS1
X2
P64/EA24/CS2B
P56/WAIT P65/EA25/CS2C P63/CS3
P62/CS2/CS2
A
P61/CS1 P60/CS0
P67/CS2E PZ3/R/W PZ2/HWR WR
RD
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
VREFH
AM0
A
10
P66/CS2D
P54/BUSRQ
Figure 2.1.1 Pin assignment diagram (100-pin QFP)

TMP91C824
91C824- 5
2.2 Pad Layout
(Chip size 4.37mm ×4.37mm) unit (μm)
PIN
no Name X point Y point PIN No Name X point Y point PIN No Name X point Y point
1 VREFL -2050 1721 35 PC0 -140 -2050 69 P21 2045 939
2 AVSS -2050 1596 36 PC1 -14 -2050 70 P20 2045 1075
3 AVCC -2050 1470 37 PC2 112 -2050 71 A15 2045 1207
4 P80 -2050 1337 38 PC3 238 -2050 72 A14 2045 1337
5 P81 -2050 1209 39 PC4 365 -2050 73 A13 2045 1464
6 P82 -2050 1076 40 PC5 491 -2050 74 A12 2045 1592
7 P83 -2050 943 41 PD5 618 -2050 75 A11 2045 1721
8 P84 -2050 810 42 PD6 744 -2050 76 A10 1720 2045
9 P85 -2050 677 43 PD7 871 -2050 77 A9 1591 2045
10 P86 -2050 544 44 D0 998 -2050 78 A8 1464 2045
11 P87 -2050 416 45 D1 1124 -2050 79 A7 1337 2045
12 P70 -2050 148 46 D2 1251 -2050 80 A6 1197 2045
13 P71 -2050 15 47 D3 1377 -2050 81 A5 1058 2045
14 P72 -2050 -118 48 D4 1504 -2050 82 A4 918 2045
15 PB0 -2050 -251 49 D5 1630 -2050 83 A3 778 2045
16 PB1 -2050 -384 50 D6 1757 -2050 84 A2 639 2045
17 PB2 -2050 -517 51 D7 2045 -1750 85 A1 499 2045
18 PB3 -2050 -650 52 P10 2045 -1614 86 A0 359 2045
19 PB4 -2050 -783 53 P11 2045 -1478 87 /RD 219 2045
20 PB5 -2050 -916 54 P12 2045 -1341 88 /WR 80 2045
21 PB6 -2050 -1049 55 P13 2045 -1205 89 PZ2 -59 2045
22 P54 -2050 -1182 56 P14 2045 -1069 90 PZ3 -199 2045
23 P55 -2050 -1315 57 P15 2045 -933 91 P56 -338 2045
24 AM0 -2050 -1448 58 P16 2045 -796 92 P60 -478 2045
25 VCC -2050 -1581 59 P17 2045 -660 93 P61 -618 2045
26 X2 -1551 -2050 60 P27 2045 -524 94 P62 -757 2045
27 VSS -1330 -2050 61 P26 2045 -388 95 P63 -897 2045
28 X1 -1205 -2050 62 VSS 2045 -234 96 P64 -1037 2045
29 AM1 -1075 -2050 63 /NMI 2045 -80 97 P65 -1176 2045
30 /RESET -948 -2050 64 VCC 2045 240 98 P66 -1316 2045
31 XT1 -822 -2050 65 P25 2045 394 99 P67 -1456 2045
32 XT2 -520 -2050 66 P24 2045 530 100 VREFH -1725 2045
33 EMU0 -394 -2050 67 P23 2045 666
34 EMU1 -267 -2050 68 P22 2045 803

TMP91C824
91C824-6
2.3 Pin Names and Functions
The names of the input/output pins and their functions are described below.
Table 2.2 Pin names and functions.
Pin Name Number
of Pins I/O Functions
D0 to D7 8 I/O Data (lower): bits 0 to 7 of data bus
P10 to P17
D8 to D15
8 I/O
I/O
Port 1: I/O port that allows I/O to be selected at the bit level
(When used to the external 8bit bus)
Data (upper): bits 8 to15 of data bus
P20 to P27
A16 to A23
8 Output
Output
Port 2: Output port
Address: bits 16 to 23 of address bus
A8 to A15 8 Output Address: bits 8 to 15 of address bus
A0 to A7 8 Output Address: bits 0 to 7 of address bus
/RD 1 Output Read: strobe signal for reading external memory
/WR 1 Output Write: strobe signal for writing data to pins D0 to D7
PZ2
/HWR
1 I/O
Output
Port Z2: I/O port (with pull-up resistor)
High Write: strobe signal for writing data to pins D8 to D15
PZ3
＿＿＿＿
R/W
1 I/O
Output
Port Z3: I/O port (with pull-up resistor)
P54
/BUSRQ
1 I/O
Input
Port 54: I/O port (with pull-up resistor)
Bus Request: High-Impedance used to request Bus Release
Read/Write: 1 represents Read or Dummy cycle; 0 represents write cycle.
P55
/BUSAK
1 I/O
Output
Port 55: I/O port (with pull-up resistor)
Bus Acknowledge: signal used to acknowledge Bus Release
P56
/WAIT
1 I/O
Input
Port 56: I/O port (with pull-up resistor)
Wait: pin used to request CPU bus wait
P60
/CS0
1 Output
Output
Port 60:Output port
Chip select 0: Outputs “0” when address is within specified address area.
P61
/CS1
1 Output
Output
Port 61:Output port
Chip Select 1: outputs “0” when address is within specified address area
P62
/CS2
/CS2A
1 Output
Output
Output
Port 62: Output port
Chip Select 2: outputs “0” when address is within specified address area
Expand Chip Select: 2A: outputs 0 when address is within specified address area
P63
/CS3
1 Output
Output
Port 63:Output port
Chip Select 3: outputs “0” when address is within specified address area
P64
EA24
/CS2B
1
Output
Output
Output
Port 64: Output port
(Address 24: Expand address)
(Expand Chip Select: 2B: outputs “0” when address is within specified address area)
P65
EA25
/CS2C
1 Output
Output
Output
Port 65: Output port
(Address 25: Expand address)
(Expand Chip Select: 2B: outputs “0” when address is within specified address area)
P66
/CS2D
1 Output
Output
Port 66: Output port
(Expand Chip Select: 2D: outputs “0” when address is within specified address area)
P67
/CS2E
1 Output
Output
Port 67: Output port
(Expand Chip Select: 2E: outputs “0” when address is within specified address area)
.

TMP91C824
91C824- 7
Pin Name Number
of Pins I/O Functions
P70
SCK
OPTRX0
1 I/O
I/O
Input
Port 70: I/O port
Serial bus interface clock I/O data at SIO mode
Serial recive data “0”
P71
S0
SDA
OPTTX0
1 I/O
Output
I/O
Output
Port 71: I/O port
Serial bus interface send data at SIO mode
Serial bus interface send/recive data at I2C mode
Open drain output mode by programmable (with pull up)
Serial send data “0”
P72
SI
SCL
1 I/O
Input
I/O
Port 72I/O port
Serial bus interface recive data at SIO mode
Serial bus interface clock I/O data at I2C mode
Open drain output mode by programmable (with pull up)
P80 to P87
AN0 to AN7
/ADTRG
8 Input
Input
Input
Port 80 to 87 port: Pin used to input ports
Analog input 0 to 7: Pin used to Input to A/D conveter
A/D trigger: Signal used to request A/D start (with used to P83)
PB0
TA0IN
1 I/O
Input
Port B0: I/O port
8bit timer 0 input: Timer 0 input
PB1
TA1OUT
1 I/O
Output
Port B1: I/O port
8bit timer 1 output: Timer 0 input or Timer 1 output
PB2
TA3OUT
1 I/O
Output
Port B2: I/O port
8bit timer 3 output: Timer 2 input or Timer 3 output
PB3
INT0
1 I/O
input
Port B0: I/O port
Interrupt request pin0: Interrupt request pin with programmable level / rising /
falling edge
PB4 to PB6
INT1 to INT3
3 I/O
input
Port B4 to B6: I/O port
Interrupt request pin1 to 3: Interrupt request pin with programmable level / rising
/falling edge
PC0
TXD0
1 I/O
Output
Port C0: I/O port
Serial 0 send data: Open drain output pin by programmable
PC1
RXD0
1 I/O
Input
Port C1: I/O port
Serial 0 recive data

TMP91C824
91C824-8
Pin Name Number
of Pins I/O Functions
PC2
SCLK0
/CTS0
1 I/O
I/O
Input
Port C2: I/O port
Serial clock I/O 0
Serial data send enable 0 (Clear to Send)
PC3
TXD1
1 I/O
Output
Port C3: I/O port
Serial send data 1
Open drain output pin by programmable
PC4
RXD1
1 I/O
Input
Port C4: I/O port
Serial recive data 1
PC5
SCLK1
/CTS1
1 I/O
I/O
Input
Port C5: I/O port
Serial clock I/O 1
Serial data send enable 1 (Clear to Send)
XT1 1 Input Low Frequency Oscillator connecting pin
XT2 1 Output Low Frequency Oscillator connecting pin
PD5
SCOUT
1 Output
Output
Port D5: Output port
System clock output: f
SYS
or f
S
output
PD6
/ALARM
/MLDALM
1 Output
Output
Output
Port D6: Output port
RTC alarm output pin
PD7
MLDALM
1 Output
Output
Port D7: Output port
Melody / Alarm output pin
/NMI 1 Input Non-Maskable Interrupt Request Pin: interrupt request pin with programmable
falling edge level or with both edge levels programmable
AM0 to 1 2 Input Operation mode:
Fixed to AM1=”0”,AM0=”1” 16-bit external bus or 8/16-bit dynamic sizing.
Fixed to AM1=”0”,AM0=”0” 8-bit external bus fixed.
EMU0 1 Output Open pin
EMU1 1 Output Open pin
/RESET 1 Input Reset: initializes TMP91C824. (With pull-up resistor)
VREFH 1 Input Pin for reference voltage input to AD converter (H)
VREFL 1 Input Pin for reference voltage input to AD converter (L)
AVCC 1 High-frequency oscillator connection pins
AVSS 1 Power supply pin for AD converter
X1/X2 2 GND pin for AD converter (0 V)
DVCC 3 Power supply pins (All Vcc pins should be connecyed with the power
Supply pin).
DVSS 3 GND pins (0 V) (All pins shuold be connected with GND(0V).

TMP91C824
91C824-9
3. OPERATION
This following describes block by block the functions and operation of the TMP91C824F.
Notes and restrictionsfor eatch book are outlined in “ 7,Precautions and Restrictions at the end of thismanual.
3.1 CPU
The TMP91C824 incorporates a high-performance 16-bit CPU (the 900/L1-CPU). For CPU operation, see
the “TLCS-900/L1 CPU”.
The following describe the unique function ofthe CPU used in the TMP91C824; these functions are not
covered in the TLCS-900/L1 CPUsection.
3.1.1 Reset
When resetting the TMP91C824 microcontroller, ensure that the power supply voltage is within the
operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the
/RESET input to Low level at least for 10 system clocks (ten states: 80 µs at 4 MHz).
After Reset, Clock doubler circuit is set to x1 mode, and also Clock gear is set to x1/16 mode. It means
that the initial clock mode starts x1/64 speed mode against the maximum speed of TMP91C824.
When the reset is accept, the CPU:
•Sets as follows the program counter (PC) in accordance with the reset vector stored at address
FFFF00H to FFFF02H:
PC<0 to 7> ←value at FFFF00Haddress
PC<15 to 8>←value at FFFF01Haddress
PC<23 to 16>←value at FFFF02Haddress
•Sets thestack pointer (XSP) to 100H.
•Sets bits <IFF2:0> of the status register(SR) to 111 (sets the interrupt level mask register tolevel
7).
•Sets the <MAX> bit of the status register(SR) to 1 (MAX mode).
(Note: As this product does not support MIN mode, do not write a 0 to the <MAX> )
•Clears bits <RFP2:0> of the status register(SR) to 000 (sets the register bank to 0 ).
Whenreset isreleased,the CPU starts executing instructionsinaccordance withtheprogramcounter
settings. CPU internal registers not mentioned above do not change when the reset is released.
When the reset is accepted, the CPU sets internal I/O, ports,and other pins as follows.
•Initializes the internal I/O registers.
•Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or
output port mode.
(Note1) The CPU internal register (except to PC,SR,XSP) and internal RAM data do not change by
resetting.
Figure 3.1.1 is a reset timing chart ofthe TMP91C824.

TMP91C824
91C824-
10
read
wri
te
f
FPH
A23∼
0
DATA-IN
D0∼
15
D0∼
15
sampling
(After reset released,,startting 2 wait read cycle)
Note
)
Pull-up (internal) High-z
DATA-OUT
sampling
(P
52 input mode)
RESET
RD
WR
HWR
/CS0,1, 3,
0FFFF00H
/CS
2
DATA-IN
XT1,XT2
Figure 3.1.1TMP91C824 Reset Timing Chart

TMP91C824
91C824-11
3.2 Memory Map
Figure 3.2.1 is a memory map of the TMP91C824.
000000H
001000H
16Mbyte area
(R)
(−R)
(R+)
(R +R8/16)
(R +d8/16)
(nnn)
Direct
area
(n)
64Kbytearea
(nn)
Internal I/O
(4KByte)
Internal RAM
(8K Byte)
003000H
010000H
( =Internal area)
FFFF00H
FFFFFFH
Vector table
(256
Byte)
External memory
000100H
000FE0H
Figure 3.2 1 Memory Map
Note : Address 000FE0H –00FFFH is assigned for the TOSHIBA reserve area, user can’t use.

TMP91C824
91C824-
12
3.3 Triple Clock Function and Standby Function
TMP91C824 contains (1) aclock gear, (2) clock doubler (DFM), (3) stand-by controller and (4)
noise-reduction circuit. It is used for low-power, low-noise systems.
This chapter is organized as follows:
3.3.1 Block diagram of system clock
3.3.2 SFRs
3.3.3 System clock controller
3.3.4 Prescaler clock controller
3.3.5 Clock doubler (DFM)
3.3.6 Noise-reducing circuit
3.3.7 Stand-by controller

TMP91C824
91C824-
13
The clock operating modes are as follows: (a) Single Clock Mode (X1, X2 pins only), (b) Dual Clock Mode
(X1, X2, XT1 and XT2 pins) and (c) Triple Clock Mode (the X1, X2, XT1 and XT2 pins and DFM).
Figure 3.3.1shows a transition figure.
UsingDFM
instruction
Reset
(f
OSCH
/32)
release Reset
instruction
interrupt
STOP mode
(Stops all circuits)
NORMAL mode
(fOSCH/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
(a) Single clock mode transition figure
(b) Dual clock mode transition fiigure
STOP
mode
(Stops all circuits)
SLOW mode
(fs/2)
Reset
(f
OSCH
/32)
release Reset
NORMAL mode
(fOSCH/gear value/2)
IDLE2
mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
IDLE2
mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
Reset
(f
OSCH
/32)
release Reset
NORMAL mode
(fOSCH/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator)
STOPmode
(Stops all circuits)
SLOW mode
(fs/2)
NORMALmode
(4 ×fOSCH/gear
value/2)
IDLE2 mode
(I/O operate)
IDLE1mode
(Operate oscillator and
DFM)
IDLE2mode
(I/O operate)
IDLE1mode
(Operate only oscillator)
(c)Triple clock mode trasision Figure
instruction
instruction
interrupt
interrupt
instruction
instruction
interrupt
interrupt
instruction
instruction
interrupt
interrupt
instruction
interrupt
instruction
instruction
interrupt
interrupt
instruction
instruction
instruction
interrupt
*NOTE
*NOTE)
・It’s prohibited
to control DFM in SLOW mode when shifting from SLOW mode to NORMAL mode with use of
DFM.（DFM Start up/Stop/Change Write to DFMCR0<ACT1:0> resister）
・If you shift from NORMAL mode with use of DFM to NORMAL mode,
the instruction should be separated into
two procedures as below. Change CPU clock->Stop DFM circuit
・It’s prohibited to shift from NORMAL mode with use of DFM to STOP mode directly. You should set
NORMAL
mode once, and then shift to STOP mode.(You should stop high frequency oscillator after you stop DFM.)
*NOTE
Figure 3.3.1System clock block diagram
The clock frequency input from the X1 and X2pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The
clock frequency selected by SYSCR1<SYSCK> is called the system clock fFPH. The system clock fSYS is defined as the divided clock of
fFPH, and one cycle of fSYS is regred to as one state.

TMP91C824
91C824-
14
3.3.1 Block diagram of system clock
Clock gear
SYSCR1<SYSCK>
TMRA0to 3
SYSCR0
<PRCK1, PRCK 0>
selector
fs
fOSCH
Low-Frequency
oscillator
XT1
XT2
SYSCR0
<XTEN, RXTEN>
Warming up timer (High/Low frequency
oscillator), Lock up timer (DFM)
SYSCR0<WUEF>
SYSCR2<WUPTM1, WUPTM 0>
DFMCR0<ACT1, ACT 0, DLUPTM>
X1
X2
Clock Doubler
(DFM)
fDFM =fOSCH ×4
÷2÷16 ÷4
fc/16
fc/8
fc/4
fc/2
fc
DFMCR0<ACT1, ACT 0>
SYSCR1<GEAR2, GEAR 0>
÷2÷4
fc/16
f
FPH
fSYS÷2
fSYS CPU
RAM
ADC
Interrupt
controller
WDT
I/O ports
prescaler
φT0
SIO0to1
SBI
RTC
φ
T
fs
φT0
fs
φT
SYSCR0
<XEN, RXTEN>
High-Frequency
oscillator
÷8
prescaler
prescaler
MLD/ALM
Figure 3.3.2Block Diagram of System clock

TMP91C824
91C824-
15
3.3.2 SFR
76543210
bit Symbol XEN XTEN RXEN RXTEN
RSYSCK
WUEF PRCK1
PRCK0
Read/Write
R/W
After reset 11100000
Function
High-frequen
cy oscillator
(fc)
0: Stop
1: Oscillation
Low-frequen
cy oscillator
(fs)
0: Stop
1: Oscillation
(note1)
High-frequen
cy oscillator
(fc) after
release of
Stop Mode
0: Stop
1: Oscillation
Low-frequen
cy oscillator
(fs) after
release of
Stop Mode
0: Stop
1: Oscillation
Selects clock
after release
of Stop
Mode
0: fc
1: fs
Warm-up
Timer
0: Write
Don’t care
1: Write
start timer
0: Read
end warm-up
1: Read
do not end
warm-up
Select prescaler clock
00: fFPH (note2)
01: reserved
10: fc/16
11: reserved
76543210
bit Symbol SYSCK
GEAR2
GEAR1
GEAR0
Read/Write
R/W
After reset 0100
Function
Select
system clock
0: fc
1: fs
Select gear value of high frequency (fc)
000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
101: (reserved)
110: (reserved)
111: (reserved)
76543210
bit Symbol SCOSEL
WUPTM1
WUPTM0
HALTM1
HALTM0
SELDRV
DRVE
Read/Write
R/W R/W R/W R/W R/W R/W R/W
After reset 0101100
Function
0: fs
1: fSYS Warm-Up Timer 00: reserved
01: 28/inputted frequency
10:214
11:216
HALT mode
00: reserved
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
<DRVE>
mode
select
0: STOP
1: IDLE1
Pin state
control in
STOP/IDLE1
mode
0: I/O off
1: Remains
the state
before
HALT
SYSCR0
(00E0H)
SYSCR1
(00E1H)
SYSCR2
(00E2H)
(note1) By Reset, low-frequency oscillator is enable.
(note2) In case of using built-in SBI circuit, it must set SYSCR0<PRCK1:0> to ‘00’.
Figure 3.3.3SFR for system clock

TMP91C824
91C824-
16
Figure 3.3.4SFR for DFM
Symbol
Name Address
76543210
ACT1 ACT0 DLUPFG
DLUPTM
R/W R/W RR/W
0000
DFM
LUP
select fFPH
DFMCR0
DFM
Control
Register 0 E8H
00
01
10
11
STOP
RUN
RUN
RUN
STOP
RUN
STOP
STOP
fOSCH
fOSCH
fDFM
fOSCH
Lock up
Status Flag
0: end
1: not end
Lock-up Time
0: 212 /f OSCH
1: 210 /f OSCH
R/W R/W R/W R/W R/W R/W R/W R/W
00010011
DFMCR1
DFM
Control
Register 1
E9H
DFMrevision
Input frequency 4~6.75MHz(@2.7V~3.6V) : write“0BH”
Input frequency 2~2.5MHz(@2.0±10%) : write “1BH”
Limitation point on the use of DFM
1. It’s prohibited to execute DFM enable/disable controlin the SLOW mode(fs)
(write to DFMCR0<ACT1:0>=”10”). You should control DFM in the NORMAL mode.
2. If you stop DFM operation during using DFM(DFMCR0<ACT1:0>=”10”) , you shouldn’t execute that
change the clock fDFM to fOSCH and stop the DFM at the same time. Therefore the above executions should be
separated into two procedures as showing below.
LD (DFMCR0),C0H ;change the clock fDFM to fOSCH
LD (DFMCR0),00H ;DFM stop
3.Ifyoustop highfrequencyoscillatorduringusingDFM (DFMCR0<ACT1:0>=”10”) , you should stop DFM
before you stop high frequency oscillator.
Please refer to 3.3.5 Clock Doubler (DFM) for the details.

TMP91C824
91C824-
17
76543210
bit Symbol
PROTECT
TA3LCDE
–––EXTIN DRVOSCH
DRVOSCL
Read/Write
RR/W R/W R/W R/W R/W R/W R/W
After reset 00100011
Function
Protect flag
0: OFF
1: ON
LCDC source
CLK
0: 32KHz
1: TA3OUT
Write “1”Write “0”Write “0”1: External
clock
fc oscillator
driver ability
1: NORMAL
0: WEAK
fs oscillator
driver ability
1: NORMAL
0: WEAK
bit Symbol
Read/Write
After reset
Function
bit Symbol
Read/Write
After reset
Function
Switching the protect ON/OFF by write to following 1st-KEY,2nd-KEY
1st-KEY: EMCCR1=5AH,EMCCR2=A5H in succession write
2nd-KEY: EMCCR1=A5H,EMCCR2=5AH in succession write
bit Symbol
ENFROM
ENDROM
ENPROM
FFLAG
DFLAG PFLAG
Read/Write
R/W R/W R/W R/W R/W R/W
After reset 000000
CS1A write
Operation flag
CS2B-2G
write
operation
Flag
CS2A write
Operation
Flag
Function
CS1A area
detect control
0: disable
1: enable
CS2B-2G
area detect
control
0: disable
1: enable
CS2A area
detect control
0: disable
1: enable
When reading
“0”: not written
“1”: written
When writing
“0”: clear flag
EMCCR0
(00E3H)
EMCCR1
(00E4H)
EMCCR2
(00E5H)
EMCCR3
(00E6H)
(note) In case of Vcc=2V±10% use, fixed to EMCCR0<DRV0SCH>=’1’.
Figure 3.3.5SFR for noise-reduction