SONIX SN32F260 Series User manual

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 1 Version 1.5
SN32F260 Series
USER’S MANUAL
SN32F268/267/265/264/2641/263
S
SO ON Ni iX X 3 32 2- -B Bi it t C Co or rt te ex x- -M M0 0 M Mi ic cr ro o- -C Co on nt tr ro ol ll le er r
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 2 Version 1.5
AMENDENT HISTORY
Version
Date
Description
1.0
2016/10/12
First version released.
1.1
2017/01/04
1. Modify the description of Deep Sleep Mode wakeup source.
2. Add SN32F265J Package information.
1.2
2017/02/13
1. Add SN32F263X Package information.
1.3
2017/04/28
1. Modify typing error.
1.4
2017/12/26
1. Add Note for setting the pins which are not pin-out.
2. Modify typing error (CODE OPTION TABLE)
1.5
2018/09/19
1. Modify DP/DN naming rule.
2. Modify typing error of CT16Bn Register.

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 Version 1.5
Table of Content
AMENDENT HISTORY................................................................................................................................ 2
1
1
1
PRODUCT OVERVIEW....................................................................................................................... 10
1.1 FEATURES...................................................................................................................................... 10
1.2 SYSTEM BLOCK DIAGRAM........................................................................................................ 12
1.3 CLOCK GENERATION BLOCK DIAGRAM................................................................................ 13
1.4 PIN ASSIGNMENT......................................................................................................................... 14
1.5 PIN DESCRIPTIONS....................................................................................................................... 19
1.6 PIN CIRCUIT DIAGRAMS............................................................................................................. 21
2
2
2
CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 22
2.1 MEMORY MAP............................................................................................................................... 22
2.2 SYSTEM TICK TIMER................................................................................................................... 23
2.2.1 OPERATION ............................................................................................................................ 23
2.2.2 SYSTICK USAGE HINTS AND TIPS ....................................................................................... 24
2.2.3 SYSTICK REGISTERS.............................................................................................................. 24
2.2.3.1 System Tick Timer Control and Status register (SYSTICK_CTRL)................................... 24
2.2.3.2 System Tick Timer Reload value register (SYSTICK_LOAD)........................................... 24
2.2.3.3 System Tick Timer Current Value register (SYSTICK_VAL)............................................ 25
2.2.3.4 System Tick Timer Calibration Value register (SYSTICK_CALIB) .................................. 25
2.3 NESTED VECTORED INTERRUPT CONTROLLER (NVIC) ..................................................... 26
2.3.1 INTERRUPT AND EXCEPTION VECTORS ........................................................................... 26
2.3.2 NVIC REGISTERS.................................................................................................................... 27
2.3.2.1 IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER)....................................................... 27
2.3.2.2 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER)................................................... 27
2.3.2.3 IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR) ..................................................... 28
2.3.2.4 IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR) ................................................. 28
2.3.2.5 IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7)............................................... 28
2.4 APPLICATION INTERRUPT AND RESET CONTROL (AIRC).................................................. 29
2.5 CODE OPTION TABLE.................................................................................................................. 30
2.6 CORE REGISTER OVERVIEW ..................................................................................................... 31
3
3
3
SYSTEM CONTROL............................................................................................................................. 32
3.1 RESET.............................................................................................................................................. 32
3.1.1 POWER-ON RESET (POR)...................................................................................................... 32
3.1.2 WATCHDOG RESET (WDT RESET)....................................................................................... 33

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 4 Version 1.5
3.1.3 BROWN-OUT RESET............................................................................................................... 33
3.1.3.1 BROWN OUT DESCRIPTION........................................................................................... 33
3.1.3.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION............................................... 34
3.1.3.3 BROWN-OUT RESET IMPROVEMENT.......................................................................... 34
3.1.4 EXTERNAL RESET .................................................................................................................. 35
3.1.4.1 SIMPLY RC RESET CIRCUIT........................................................................................... 36
3.1.4.2 DIODE & RC RESET CIRCUIT......................................................................................... 36
3.1.4.3 ZENER DIODE RESET CIRCUIT...................................................................................... 37
3.1.4.4 VOLTAGE BIAS RESET CIRCUIT................................................................................... 37
3.1.4.5 EXTERNAL RESET IC....................................................................................................... 38
3.1.5 SOFTWARE RESET ................................................................................................................. 38
3.2 SYSTEM CLOCK............................................................................................................................ 39
3.2.1 INTERNAL RC CLOCK SOURCE ........................................................................................... 39
3.2.1.1 Internal High-speed RC Oscillator (IHRC).......................................................................... 39
3.2.1.2 Internal Low-speed RC Oscillator (ILRC)........................................................................... 39
3.2.2 SYSTEM CLOCK (SYSCLK) SELECTION............................................................................... 40
3.2.3 CLOCK-OUT CAPABITITY..................................................................................................... 40
3.3 SYSTEM CONTROL REGISTERS 0.............................................................................................. 41
3.3.1 Analog Block Control register (SYS0_ANBCTRL)................................................................... 41
3.3.2 Clock Source Status register (SYS0_CSST).............................................................................. 41
3.3.3 System Clock Configuration register (SYS0_CLKCFG).......................................................... 41
3.3.4 AHB Clock Prescale register (SYS0_AHBCP)......................................................................... 42
3.3.5 System Reset Status register (SYS0_RSTST) ............................................................................ 42
3.3.6 LVD Control register (SYS0_LVDCTRL)................................................................................. 43
3.3.7 External RESET Pin Control register (SYS0_EXRSTCTRL) ................................................... 43
3.3.8 SWD Pin Control register (SYS0_SWDCTRL)......................................................................... 43
3.3.9 Interrupt Vector Table Mapping register (SYS0_IVTM).......................................................... 44
3.3.10 Noise Detect Control register (SYS0_NDTCTRL).................................................................... 44
3.3.11 Noise Detect Status register (SYS0_NDTSTS).......................................................................... 44
3.3.12 Anti-EFT Ability Control register (SYS0_ANTIEFT)............................................................... 44
3.4 SYSTEM CONTROL REGISTERS 1.............................................................................................. 46
3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN).................................................................... 46
3.4.2 APB Clock Prescale register 1 (SYS1_APBCP1)..................................................................... 47
4
4
4
SYSTEM OPERATION MODE........................................................................................................... 48
4.1 OVERVIEW..................................................................................................................................... 48
4.2 NORMAL MODE ............................................................................................................................ 48
4.3 LOW-POWER MODES................................................................................................................... 48
4.3.1 SLEEP MODE.......................................................................................................................... 48

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 5 Version 1.5
4.3.2 DEEP-SLEEP MODE............................................................................................................... 49
4.4 WAKEUP......................................................................................................................................... 49
4.4.1 OVERVIEW .............................................................................................................................. 49
4.4.2 WAKEUP TIME........................................................................................................................ 49
4.5 STATE MACHINE OF PMU........................................................................................................... 50
4.6 OPERATION MODE COMPARSION TABLE .............................................................................. 51
4.7 PMU REGISTERS ........................................................................................................................... 52
4.7.1 Power Control register (PMU_CTRL)..................................................................................... 52
5
5
5
GENERAL PURPOSE I/O PORT (GPIO).......................................................................................... 53
5.1 OVERVIEW..................................................................................................................................... 53
5.2 GPIO MODE .................................................................................................................................... 53
5.3 GPIO REGISTERS........................................................................................................................... 54
5.3.1 GPIO Port n Data register (GPIOn_DATA) (n=0,1,2,3)......................................................... 54
5.3.2 GPIO Port n Mode register (GPIOn_MODE) (n=0,1,2,3)...................................................... 54
5.3.3 GPIO Port n Configuration register (GPIOn_CFG) (n=0,1,2,3)............................................ 54
5.3.4 GPIO Port n Interrupt Sense register (GPIOn_IS) (n=0,1,2,3)............................................... 56
5.3.5 GPIO Port n Interrupt Both-edge Sense register (GPIOn_IBS) (n=0,1,2,3)........................... 56
5.3.6 GPIO Port n Interrupt Event register (GPIOn_IEV) (n=0,1,2,3)............................................ 56
5.3.7 GPIO Port n Interrupt Enable register (GPIOn_IE) (n=0,1,2,3)............................................ 57
5.3.8 GPIO Port n Raw Interrupt Status register (GPIOn_RIS) (n=0,1,2,3) ................................... 57
5.3.9 GPIO Port n Interrupt Clear register (GPIOn_IC) (n=0,1,2,3).............................................. 57
5.3.10 GPIO Port n Bits Set Operation register (GPIOn_BSET) (n=0,1,2,3).................................... 57
5.3.11 GPIO Port n Bits Clear Operation register (GPIOn_BCLR) (n=0,1,2,3)............................... 58
6
6
6
16-BIT TIMER0 WITH CAPTURE FUNCTION .............................................................................. 59
6.1 OVERVIEW..................................................................................................................................... 59
6.2 FEATURES...................................................................................................................................... 59
6.3 PIN DESCRIPTION......................................................................................................................... 59
6.4 BLOCK DIAGRAM......................................................................................................................... 60
6.5 TIMER OPERATION ...................................................................................................................... 61
6.5.1 Edge-aligned Up-counting Mode ............................................................................................. 61
6.6 PWM................................................................................................................................................. 62
6.6.1 PWM Mode 1............................................................................................................................ 62
6.6.2 PWM Mode 2............................................................................................................................ 63
6.7 CT16BN REGISTERS...................................................................................................................... 64
6.7.1 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=0,1) ............................................. 64
6.7.2 CT16Bn Timer Counter register (CT16Bn_TC) (n=0,1) ......................................................... 64
6.7.3 CT16Bn Prescale register (CT16Bn_PRE) (n=0,1)................................................................. 64
6.7.4 CT16Bn Prescale Counter register (CT16Bn_PC) (n=0,1)..................................................... 65

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 6 Version 1.5
6.7.5 CT16Bn Count Control register (CT16Bn_CNTCTRL) (n=0)................................................. 65
6.7.6 CT16Bn Match Control register (CT16Bn_MCTRL) (n=0) .................................................... 66
6.7.7 CT16Bn Match Control register (CT16Bn_MCTRL) (n=1) .................................................... 66
6.7.8 CT16Bn Match Control register 2(CT16Bn_MCTRL2) (n=1) ................................................ 68
6.7.9 CT16Bn Match Control register 3 (CT16Bn_MCTRL3) (n=1) ............................................... 70
6.7.10 CT16Bn Match register 0 (CT16Bn_MR0) (n=0).................................................................... 71
6.7.11 CT16Bn Match register 0~19, 21~23 (CT16Bn_MR0~19, 21~23) (n=1) ............................... 71
6.7.12 CT16Bn Capture Control register (CT16Bn_CAPCTRL) (n=0) ............................................. 71
6.7.13 CT16Bn Capture 0 register (CT16Bn_CAP0) (n=0) ............................................................... 72
6.7.14 CT16Bn External Match register (CT16Bn_EM)(n=1) ........................................................... 72
6.7.15 CT16Bn External Match Control register (CT16Bn_EMC)(n=1)........................................... 73
6.7.16 CT16Bn External Match Control register 2(CT16Bn_EMC2)(n=1)....................................... 74
6.7.17 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=1)................................................ 75
6.7.18 CT16Bn PWM Control register 2 (CT16Bn_PWMCTRL2) (n=1)........................................... 77
6.7.19 CT16Bn PWM Enable register (CT16Bn_PWMENB) (n=1)................................................... 78
6.7.20 PWM IO Enable register (CT16Bn_PWMIOENB) (n=1 )....................................................... 79
6.7.21 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=0, 1) ................................... 81
6.7.22 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=0,1)............................................... 82
7
7
7
WATCHDOG TIMER (WDT).............................................................................................................. 84
7.1 OVERVIEW..................................................................................................................................... 84
7.2 BLOCK DIAGRAM......................................................................................................................... 85
7.3 WDT REGISTERS........................................................................................................................... 86
7.3.1 Watchdog Configuration register (WDT_CFG)....................................................................... 86
7.3.2 Watchdog Timer Constant register (WDT_TC)........................................................................ 86
7.3.3 Watchdog Feed register (WDT_FEED)................................................................................... 87
8
8
8
SPI............................................................................................................................................................ 88
8.1 OVERVIEW..................................................................................................................................... 88
8.2 FEATURES...................................................................................................................................... 88
8.3 PIN DESCRIPTION......................................................................................................................... 88
8.4 INTERFACE DESCRIPTION ......................................................................................................... 89
8.4.1 SPI ............................................................................................................................................ 89
8.4.2 COMMUNICATION FLOW..................................................................................................... 90
8.4.2.1 SINGLE-FRAME................................................................................................................. 90
8.4.2.2 MULTI-FRAME .................................................................................................................. 91
8.5 AUTO-SEL....................................................................................................................................... 91
8.6 SPIREGISTERS .............................................................................................................................. 92
8.6.1 SPI n Control register 0 (SPIn_CTRL0) (n=0)........................................................................ 92
8.6.2 SPI n Control register 1 (SPIn_CTRL1) (n=0)........................................................................ 93

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 7 Version 1.5
8.6.3 SPI n Clock Divider register (SPIn _CLKDIV) (n=0) ............................................................. 93
8.6.4 SPI n Status register (SPIn _STAT) (n=0)................................................................................ 93
8.6.5 SPI n Interrupt Enable register (SPIn _IE) (n=0).................................................................... 94
8.6.6 SPI n Raw Interrupt Status register (SPIn _RIS) (n=0)........................................................... 94
8.6.7 SPI n Interrupt Clear register (SPIn _IC) (n=0)...................................................................... 95
8.6.8 SPI n Data register (SPIn _DATA) (n=0)................................................................................ 95
8.6.9 SPI n Data Fetch register (SPIn _DF) (n=0)........................................................................... 95
9
9
9
I2C............................................................................................................................................................ 96
9.1 OVERVIEW..................................................................................................................................... 96
9.2 FEATURES...................................................................................................................................... 96
9.3 PIN DESCRIPTION......................................................................................................................... 97
9.4 WAVE CHARACTERISTICS......................................................................................................... 97
9.5 I2C MASTER MODES .................................................................................................................... 98
9.5.1 MASTER TRANSMITTER MODE............................................................................................ 98
9.5.2 MASTER RECEIVER MODE................................................................................................... 98
9.5.3 ARBITRATION ......................................................................................................................... 98
9.6 I2CSLAVE MODES........................................................................................................................ 99
9.6.1 SLAVE TRANSMITTER MODE ............................................................................................... 99
9.6.2 SLAVE RECEIVER MODE ...................................................................................................... 99
9.7 I2C REGISTERS............................................................................................................................ 100
9.7.1 I2C n Control register (I2Cn_CTRL) (n=0)........................................................................... 100
9.7.2 I2C n Status register (I2Cn_STAT) (n=0).............................................................................. 101
9.7.3 I2C n TX Data register (I2Cn_TXDATA) (n=0) .................................................................... 102
9.7.4 I2C n RX Data register (I2Cn_RXDATA) (n=0).................................................................... 102
9.7.5 I2C n Slave Address 0 register (I2Cn_SLVADDR0) (n=0).................................................... 102
9.7.6 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0) ........................................... 102
9.7.7 I2C n SCL High Time register (I2Cn_SCLHT) (n=0)............................................................ 103
9.7.8 I2C n SCL Low Time register (I2Cn_SCLLT) (n=0).............................................................. 103
9.7.9 I2C n Timeout Control register (I2Cn_TOCTRL) (n=0) ....................................................... 103
1
1
10
0
0
USB FS DEVICE INTERFACE...................................................................................................... 104
10.1 OVERVIEW................................................................................................................................... 104
10.2 FEATURES.................................................................................................................................... 104
10.3 PIN DESCRIPTION....................................................................................................................... 104
10.4 BLOCK DIAGRAM....................................................................................................................... 105
10.5 USB SRAM ACCESS .................................................................................................................... 105
10.6 USB MACHINE............................................................................................................................. 106
10.7 USB INTERRUPT.......................................................................................................................... 106
10.8 USB ENUMERATION .................................................................................................................. 107

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 8 Version 1.5
10.9 USB REGISTERS .......................................................................................................................... 108
10.9.1 USB Interrupt Enable Register (USB_INTEN) ...................................................................... 108
10.9.2 USB Interrupt Event Status Register (USB_INSTS)............................................................... 109
10.9.3 USB Interrupt Event Status Clear Register (USB_INSTSC).................................................. 110
10.9.4 USB Device Address Register (USB_ADDR)......................................................................... 111
10.9.5 USB Configuration Register (USB_CFG).............................................................................. 111
10.9.6 USB Signal Control Register (USB_SGCTL)......................................................................... 112
10.9.7 USB Endpoint 0 Control Register (USB_EP0CTL) ............................................................... 112
10.9.8 USB Endpoint n Control Register (USB_EPnCTL, n = 1 ~ 4)............................................... 113
10.9.9 USB Endpoint Data Toggle Register (USB_EPTOGGLE) .................................................... 114
10.9.10 USB Endpoint n Buffer Offset Register (USB_EPnBUFOS, n = 1 ~ 4)............................. 114
10.9.11 USB Frame Number Register (USB_FRMNO).................................................................. 114
10.9.12 USB PHY Parameter Register (USB_PHYPRM)............................................................... 114
10.9.13 USB PHY Parameter Register 2(USB_PHYPRM2)........................................................... 115
10.9.14 USB PHY Parameter Register (USB_PS2CTL) ................................................................. 115
10.9.15 USB Read/Write Address Register (USB_RWADDR)........................................................ 115
10.9.16 USB Read/Write Data Register (USB_RWDATA).............................................................. 116
10.9.17 USB Read/Write Status Register (USB_RWSTATUS)........................................................ 116
10.9.18 USB Read/Write Address Register2 (USB_RWADDR2).................................................... 116
10.9.19 USB Read/Write Data Register2 (USB_RWDATA2).......................................................... 116
10.9.20 USB Read/Write Status Register 2(USB_RWSTATUS2).................................................... 117
1
1
11
1
1
FLASH............................................................................................................................................... 118
11.1 OVERVIEW................................................................................................................................... 118
11.2 EMBEDDED FLASH MEMORY.................................................................................................. 118
11.3 FEATURES.................................................................................................................................... 118
11.4 ORGANIZATION.......................................................................................................................... 119
11.5 READ ............................................................................................................................................. 119
11.6 PROGRAM/ERASE....................................................................................................................... 119
11.7 EMBEDDED BOOT LOADER ..................................................................................................... 119
11.8 FLASH MEMORY CONTROLLER (FMC).................................................................................. 120
11.8.1 CODE SECURITY (CS).......................................................................................................... 120
11.8.2 PROGRAM FLASH MEMORY............................................................................................... 121
11.8.3 ERASE .................................................................................................................................... 121
11.8.3.1 PAGE ERASE................................................................................................................ 121
11.8.3.2 MASS ERASE................................................................................................................ 121
11.9 READ PROTECTION.................................................................................................................... 121
11.10 HW CHECKSUM....................................................................................................................... 121
11.11 FMC REGISTERS...................................................................................................................... 122

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 9 Version 1.5
11.11.1 Flash Low Power Control register (FLASH_LPCTRL)..................................................... 122
11.11.2 Flash Status register (FLASH_STATUS) ........................................................................... 122
11.11.3 Flash Control register (FLASH_CTRL)............................................................................. 122
11.11.4 Flash Data register (FLASH_DATA)................................................................................. 123
11.11.5 Flash Address register (FLASH_ADDR) ........................................................................... 123
11.11.6 Flash Checksum register (FLASH_CHKSUM).................................................................. 123
1
1
12
2
2
SERIAL-WIRE DEBUG (SWD)..................................................................................................... 124
12.1 OVERVIEW................................................................................................................................... 124
12.2 FEATURES.................................................................................................................................... 124
12.3 PIN DESCRIPTION....................................................................................................................... 124
12.4 DEBUG NOTE............................................................................................................................... 124
12.4.1 LIMITATIONS........................................................................................................................ 124
12.4.2 DEBUG RECOVERY.............................................................................................................. 124
12.4.3 INTERNAL PULL-UP/DOWN RESITIORS on SWD PINS.................................................... 125
1
1
13
3
3
DEVELOPMENT TOOL ................................................................................................................ 126
13.1 SN-LINK-V3.0............................................................................................................................... 127
13.2 SN32F268 STARTER-KIT ............................................................................................................ 128
1
1
14
4
4
ELECTRICAL CHARACTERISTIC............................................................................................ 129
14.1 ABSOLUTE MAXIMUM RATING.............................................................................................. 129
14.2 ELECTRICAL CHARACTERISTIC............................................................................................. 129
1
1
15
5
5
FLASH ROM PROGRAMMING PIN........................................................................................... 130
1
1
16
6
6
PACKAGE INFORMATION ......................................................................................................... 131
16.1 LQFP 48 PIN .................................................................................................................................. 131
16.2 QFN 46 PIN.................................................................................................................................... 132
16.3 SOP 28 PIN..................................................................................................................................... 133
16.4 SSOP 28 PIN................................................................................................................................... 134
16.5 QFN 28 PIN.................................................................................................................................... 135
16.6 QFN 33 PIN.................................................................................................................................... 136
16.7 SSOP 24 PIN................................................................................................................................... 137
1
1
17
7
7
MARKING DEFINITION............................................................................................................... 138
17.1 INTRODUCTION.......................................................................................................................... 138
17.2 MARKING INDETIFICATION SYSTEM.................................................................................... 138
17.3 MARKING EXAMPLE ................................................................................................................. 139
17.4 DATECODE SYSTEM.................................................................................................................. 140

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 10 Version 1.5
1
1
1
PRODUCT OVERVIEW
1.1 FEATURES

Memory configuration

Working voltage 2.5V ~ 5.5V
Flash ROM size: 32KB(include Boot Loader 2K).
User RAM: 2KB.

Timer
USB FIFO RAM: 256 bytes.
One 16-bit general purpose timer CT16B0 with CAP0.
One 16-bit general purpose timer CT16B1 with 22-ch

Operation Frequency up to 48MHz
PWM.

Interrupt sources

Interfaces: I2C & SPI
ARM Cortex-M0 built-in Nested Vectored Interrupt
- One I2C controller supporting I2C-bus specification.
Controller (NVIC).
- One SPI controller supporting SPI protocol.

I/O pin configuration

System clocks
Bi-directional: P0, P1, P2, P3.
Internal high clock: RC type 48MHz.
Wakeup: P0, P1, P2, P3 level change.
Internal low clock: RC type 32KHz.
Pull-up resisters: P0, P1, P2, P3.
20mA Sink/8mA Drive: P0, P1, P2, P3.

Serial Wire Debug (SWD)

Programmable WatchDog Timer (WDT)

Operating modes
Programmable watchdog frequency with watchdog
Normal, Sleep, and Deep-sleep.
clock source and divider.

Fcpu (Instruction cycle)

System tick timer
FCPU = FHCLK = FSYSCLK/1, FSYSCLK/2, FSYSCLK /4, …,
24-bit timer.
FSYSCLK /128.
The system tick timer clock is fixed to the frequency of
the system clock.

In-System-Progamming (ISP) supported
The SysTick timer is intended to generate a fixed
10-ms interrupt.

3.3V Regulator output
Driving current 60mA

LVD with separate thresholds
Power for USB D+ internal pull-up resistor.
Reset: 2.4V/3.3V for VDD.
Can be IO power for P1.0~P1.5. (3.3V IOs)
Can be power source for peripheral 3.3V devices.

Full Speed USB 2.0
3.3v regulator output for D+ internal 1.5k pull-up

Package (Chip form support)
resistor.
LQFP48 pin
Supports one Full speed USB device address.
QFN46 pin
Supports PS/2 mode.
One control EP and 4 configurable INT/BULK
Endpoints.
EP0 supports 64-byte FIFO depth.
Programmable EP1~EP4 FIFO depth.
Total 5 endpoints share 256-byte USB RAM.
QFN33 pin
QFN28 pin
SOP28/SSOP28 pin
SSOP24 pin

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 11 Version 1.5
Features Selection Table
Chip
ROM
RAM
FCPU
(Max MHz)
TIMER
SPI
I2C
PWM
GPIO
with Wakeup
Package
SN32F268F
32KB
2KB
48 MHz
16-bitx2
1
1
22-CH
42
LQFP48
SN32F267J
32KB
2KB
48 MHz
16-bitx2
1
1
22-CH
40
QFN46
SN32F265J
32KB
2KB
48 MHz
16-bitx2
1
1
17-CH
26
QFN33
SN32F2641J
32KB
2KB
48 MHz
16-bitx2
1
1
13-CH
22
QFN28
SN32F264S/X
32KB
2KB
48 MHz
16-bitx2
1
1
11-CH
22
SOP28/SSOP28
SN32F263X
32KB
2KB
48 MHz
16-bitx2
1
1
11-CH
18
SSOP24

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 12 Version 1.5
1.2SYSTEM BLOCK DIAGRAM
TEST/DEBUG
INTERFACE
GPIO0_0~15
GPIO1_0~5
GPIO2 0~10
GPIO3 0~8
SWDIO
SWCLK
CLKOUT
CT16B1_PWM[22:21]/
CT16B1_PWM[[19:0]
SCK0
SDI0
SDO0
/RESET
ARM
CORTEX-M0
CLOCK GENERATION
EEPROM
32KB SRAM 2KB
SYS
POWER CONTROL/
SYSTEM FUNCTIONS
POWER
REGULATOR 1
ILRC
32KHz IHRC 48MHz
LVD
Clocks
Controls
AHB-LITE BUS
AHB TO APB
BRIDGE
APB BUS
GPIO
USB
VCORE
VDD 2.5V~5.5V
WDT
D+
D-
CT16B0_CAP0
POWER
REGULATOR 2
VREG33
VBUS 4.0~5.5V
PMU
16-bit TIMER 0
16-bit TIMER 1
with 22 PWM
SPI0
SCL
SDA I2C

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 13 Version 1.5
1.3 CLOCK GENERATION BLOCK DIAGRAM
CLKOUT
IHRC
48MHz
ILRC
32KHz
IHRC
ILRC SYSCLK
SYSCLKSEL
CLKOUTSEL
WDTCLKSEL
WDT
Clock Prescaler
/1, 2, 4, 8, 16, 32
WDT_PCLK
HCLK
WDT
register block
WDT
clock source
AHB clock for WDT
AHB clock for AHB to APB bridge, to AHB
matrix, to Cortex-M0 FCLK, HCLK, and
System Timer, to SYS, and to PMU
AHB clock for GPIOn
GPIOnCLKEN
n=0,1,2,3
GPIOn block
AHB
Prescaler
/1,2,4,…,128
SPIn_PCLK
AHB clock for SPIn
SPInCLKEN
n=0
SPIn
register block
SPIn
clock source
CT16Bn_PCLK
AHB clock for CT16Bn
CT16BnCLKEN
n=0,1 CT16Bn
register block
CT16Bn
clock source
AHB clock for SRAM SRAM block
AHB clock for FLASH FLASH block
CLKOUT
Prescaler
/1,2,4,…,128
WDTCLKEN
HCLK
HCLK
IHRC
ILRC
AHBCP
USBCLKEN
USB
register block
USB
clock source
AHB clock for USB
USB_PCLK = 48MHz
I2Cn_PCLK
AHB clock for I2Cn
I2CnCLKEN
n=0
I2Cn
register block
I2Cn
clock source

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 14 Version 1.5
1.4 PIN ASSIGNMENT
SN32F268F (LQFP 48 pins)
VSS
D-/PSDATA
D+/PSCLK
VREG33
VDD
VDDIO1
P1.0
P1.1/CT16B0_CAP0
P1.2/SEL0
P1.3/SCK0
P1.4/MISO0
P1.5/MOSI0
48
47
46
45
44
43
42
41
40
39
38
37
P2.0
1
●
36
P2.10
P2.1
2
35
P2.9
P2.2
3
34
P2.8
P0.0/CT16B1_PWM0/CLKOUT
4
33
P2.7
P0.1/CT16B1_PWM1
5
32
P2.6
P0.2/CT16B1_PWM2
6
SN32F268F
31
P2.5
P0.3/CT16B1_PWM3
7
30
P2.4
P0.4/CT16B1_PWM4/SCL0
8
29
P2.3
P0.5/CT16B1_PWM5/SDA0
9
28
P3.8/RESET/CT16B1_PWM22
P0.6/CT16B1_PWM6
10
27
P3.7/SWDIO
P0.7/CT16B1_PWM7
11
26
P3.6/SWCLK
P0.8/CT16B1_PWM8
12
25
P3.5 CT16B1_PWM21
13
14
15
16
17
18
19
20
21
22
23
24
P0.9/CT16B1_PWM9
P0.10/CT16B1_PWM10
P0.11/CT16B1_PWM11
P0.12/CT16B1_PWM12
P0.13/CT16B1_PWM13
P0.14/CT16B1_PWM14
P0.15/CT16B1_PWM15
P3.0/CT16B1_PWM16
P3.1/CT16B1_PWM17
P3.2/CT16B1_PWM18
P3.3/CT16B1_PWM19
P3.4

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 15 Version 1.5
SN32F267J (QFN 46 pins)
P2.0
VSS
D-/PSDATA
D+/PSCLK
VREG33
VDD
VDDIO1
P1.0
P1.1/CT16B0_CAP0
P1.2/SEL0
P1.3/SCK0
P1.4/MISO0
P1.5/MOSI0
P2.8
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P2.1
1
●
32
P2.7
P2.2
2
31
P2.6
P0.0/CT16B1_PWM0/CLKOUT
3
30
P2.5
P0.1/CT16B1_PWM1
4
SN32F267J
29
P2.4
P0.2/CT16B1_PWM2
5
28
P2.3
P0.3/CT16B1_PWM3
6
27
P3.8/RESET/CT16B1_PWM22
P0.4/CT16B1_PWM4/SCL0
7
26
P3.7/SWDIO
P0.5/CT16B1_PWM5/SDA0
8
25
P3.6/SWCLK
P0.6/CT16B1_PWM6
9
24
P3.5 CT16B1_PWM21
10
11
12
13
14
15
16
17
18
19
20
21
22
23
P0.7/CT16B1_PWM7
P0.8/CT16B1_PWM8
P0.9/CT16B1_PWM9
P0.10/CT16B1_PWM10
P0.11/CT16B1_PWM11
P0.12/CT16B1_PWM12
P0.13/CT16B1_PWM13
P0.14/CT16B1_PWM14
P0.15/CT16B1_PWM15
P3.0/CT16B1_PWM16
P3.1/CT16B1_PWM17
P3.2/CT16B1_PWM18
P3.3/CT16B1_PWM19
P3.4
Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes. Strongly recommended to set these pins as input pull-up.

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 16 Version 1.5
SN32F265J (QFN 33pins)
VREG33
VDD
VDDIO1
P1.0
P1.1/CT16B0_CAP0
P1.2/SEL0
P1.3/SCK0
P1.4/MISO0
32
31
30
29
28
27
26
25
D+/PSCLK
1
●
24
P1.5/MOSI0
D-/PSDATA
2
23
P3.8/RESET/CT16B1_PWM22
VSS
3
SN32F265J
22
P3.7/SWDIO
P0.0/CT16B1_PWM0/CLKOUT
4
21
P3.6/SWCLK
P0.1/CT16B1_PWM1
5
20
P3.5/CT16B1_PWM21
P0.2/CT16B1_PWM2
6
19
P3.4
P0.3/CT16B1_PWM3
7
18
P3.3/CT16B1_PWM19
P0.4/CT16B1_PWM4/SCL0
8
33
VSS
17
P3.2/CT16B1_PWM18
9
10
11
12
13
14
15
16
P0.5/CT16B1_PWM5/SDA0
P0.10/CT16B1_PWM10
P0.11/CT16B1_PWM11
P0.12/CT16B1_PWM12
P0.13/CT16B1_PWM13
P0.14/CT16B1_PWM14
P0.15/CT16B1_PWM15
P3.1/CT16B1_PWM17
Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes. Strongly recommended to set these pins as input pull-up.

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 17 Version 1.5
SN32F2641J (QFN 28pins)
D+
VREG33
VDD
VDDIO1
P1.2/SEL0
P1.3/SCK0
P1.4/MISO0
28
27
26
25
24
23
22
D-
1
●
21
P1.5/MOSI0
VSS
2
20
P3.8/RESET/CT16B1_PWM22
P0.0/CT16B1_PWM0/CLKOUT
3
19
P3.7/SWDIO
P0.1/CT16B1_PWM1
4
SN32F2641J
18
P3.6/SWCLK
P0.2/CT16B1_PWM2
5
17
P3.5/CT16B1_PWM21
P0.3/CT16B1_PWM3
6
16
P3.4
P0.4/CT16B1_PWM4/SCL0
7
15
P3.3/CT16B1_PWM19
8
9
10
11
12
13
14
P0.5/CT16B1_PWM5/SDA0
P0.10/CT16B1_PWM10
P0.11/CT16B1_PWM11
P0.12/CT16B1_PWM12
P0.13/CT16B1_PWM13
P0.14/CT16B1_PWM14
P0.15/CT16B1_PWM15
Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes. Strongly recommended to set these pins as input pull-up.

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 18 Version 1.5
SN32F264S/X (SOP/SSOP 28pins)
VDDIO1
1
U
28
P1.0
VDD
2
27
P1.1/CT16B0_CAP0
VREG33
3
26
P1.2/SEL0
D+/PSCLK
4
25
P1.3/SCK0
D-/PSDATA
5
24
P1.4/MISO0
VSS
6
23
P1.5/MOSI0
P0.0/CT16B1_PWM0/CLKOUT
7
22
P3.8/RESET/CT16B1_PWM22
P0.1/CT16B1_PWM1
8
21
P3.7/SWDIO
P0.2/CT16B1_PWM2
9
20
P3.6/SWCLK
P0.3/CT16B1_PWM3
10
19
P3.5/CT16B1_PWM21
P0.4/CT16B1_PWM4/SCL0
11
18
P0.15/CT16B1_PWM15
P0.5/CT16B1_PWM5/SDA0
12
17
P0.14/CT16B1_PWM14
P0.10/CT16B1_PWM10
13
16
P0.13/CT16B1_PWM13
P0.11/CT16B1_PWM11
14
15
P0.12/CT16B1_PWM12
SN32F264S/X
Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes. Strongly recommended to set these pins as input pull-up.
SN32F263X (SSOP 24pins)
VDD
1
U
24
VDDIO1
VREG33
2
23
P1.1/CT16B0_CAP0
D+/PSCLK
3
22
P1.2/SEL0
D-/PSDATA
4
21
P1.3/SCK0
P0.0/CT16B1_PWM0/CLKOUT
5
20
P1.4/MISO0
P0.1/CT16B1_PWM1
6
19
P1.5/MOSI0
P0.2/CT16B1_PWM2
7
18
P3.8/RESET/CT16B1_PWM22
P0.3/CT16B1_PWM3
8
17
P3.7/SWDIO
P0.4/CT16B1_PWM4/SCL0
9
16
P3.6/SWCLK
P0.5/CT16B1_PWM5/SDA0
10
15
VSS
P0.10/CT16B1_PWM10
11
14
P0.13/CT16B1_PWM13
P0.11/CT16B1_PWM11
12
13
P0.12/CT16B1_PWM12
SN32F263X
Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes. Strongly recommended to set these pins as input pull-up.

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 19 Version 1.5
1.5 PIN DESCRIPTIONS
PIN NAME
TYPE
DESCRIPTION
VDD, VSS
P
Power supply input pins for digital circuit.
VREG33
O
3.3v voltage output from USB 3.3v regulator.
D+/PSCLK
I/O
D+ —USB Differential signal line.
I/O
PSCLK —PS/2 clock pin with internal 5K pull-up resistor.
D-/PSDATA
I/O
D- —USB Differential signal line.
I/O
PSDATA —PS/2 data pin wit internal 5K pull-up resistor.
VDDIO1
P
Power supply input pad for the IO power of P1.0~P1.5.
P0.0/CT16B1_PWM0/
CLKOUT
I/O
P0.0 —General purpose digital input/output pin.
O
CT16B1_PWM0 —PWM output 0 for CT16B1.
O
CLKOUT —Clockout pin.
P0.1/CT16B1_PWM1/
PGDCLK
I/O
P0.1 —General purpose digital input/output pin.
O
CT16B1_PWM1 —PWM output 1 for CT16B1.
I/O
PGDCLK —Flash clock pin in programming mode.
P0.2/CT16B1_PWM2
I/O
P0.2 —General purpose digital input/output pin.
O
CT16B1_PWM2 —PWM output 2 for CT16B1.
P0.3/CT16B1_PWM3
I/O
P0.3 —General purpose digital input/output pin.
O
CT16B1_PWM3 —PWM output 3 for CT16B1.
P0.4/CT16B1_PWM4/
SCL0
I/O
P0.4 —General purpose digital input/output pin.
I/O
CT16B1_PWM4 —PWM output 4 for CT16B1.
I/O
SCL0 —I2C clock input/output.
P0.5/CT16B1_PWM5/
SDA0
I/O
P0.5 —General purpose digital input/output pin.
I/O
CT16B1_PWM5 —PWM output 5 for CT16B1.
I/O
SDA0 —I2C data input/output.
P0.6~P0.15/CT16B1_
PWM6~15
I/O
P0.6~P0.15 —General purpose digital input/output pin.
O
CT16B1_PWM6~15 —PWM output 6~15 for CT16B1.
P1.0
I/O
P1.0 —General purpose digital input/output pin.
P1.1/CT16B0_CAP0
I/O
P1.1 —General purpose digital input/output pin.
I
CT16B0_CAP0 —Capture input 0 for CT16B0.
P1.2/SEL0
I/O
P1.2 —General purpose digital input/output pin.
I
SEL0 —Slave Select for SPI.
P1.3/SCK0
I/O
P1.3 —General purpose digital input/output pin.
I/O
SCK0 —Serial clock for SPI.
P1.4/MISO0
I/O
P1.4 —General purpose digital input/output pin.
I/O
MISO0 —Master In Slave Out for SPI.

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 20 Version 1.5
P1.5/MOSI0
I/O
P1.5 —General purpose digital input/output pin.
I/O
MOSI0 —Master Out Slave In for SPI.
P2.0~P2.10
I/O
P2.0~P2.10 —General purpose digital input/output pin.
P3.0~P3.3/CT16B1_P
WM16~19
I/O
P3.0~P3.3 —General purpose digital input/output pin.
O
CT16B1_PWM16~19 —PWM output 16~19 for CT16B1.
P3.4
I/O
P3.4 —General purpose digital input/output pin.
P3.5/CT16B1_PWM2
1
I/O
P3.5 —General purpose digital input/output pin.
O
CT16B1_PWM21 —PWM output 21 for CT16B1.
P3.6/SWCLK
I/O
P3.6 —General purpose digital input/output pin.
I
SWCLK —Serial Wire Clock pin.
P3.7/SWDIO
I/O
P3.7 —General purpose digital input/output pin.
I/O
SWDIO —Serial Wire Data input/output pin.
P3.8/RESET/CT16B1
_PWM22
I/O
P3.8 —General purpose digital input/output pin.
I
RESET —External Reset input. Schmitt trigger structure, active “Low”, normally
stay “High”.
O
CT16B1_PWM22 —PWM output 22 for CT16B1.