SONIX SN32F769 User manual

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 1 Version 2.0
SN32F760/750 Series
USER’S MANUAL
SN32F769/759
SN32F768/758
SN32F767/757
SN32F766/756
SN32F765/755
S
SO ON Ni iX X 3 32 2- -B Bi it t C Co or rt te ex x- -M M0 0 M Mi ic cr ro o- -C Co on nt tr ro ol ll le er r
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 2 Version 2.0
AMENDENT HISTORY
Version
Date
Description
1.0
2014/02/27
First version released.
1.1
2014/05/23
1. Fix typing errors.
2. Update 23.3 Marking Example section.
3. Update SN-LINK-V2 photos.
1.2
2015/03/06
1. Update GPIO & LCD driver characteristics in Chap 20 Electrical Characteristic.
2. Fix typing error in 16.8 LCD DISPLAY MEMORY MAP
3. Add notice for power input pads.
4. Fix typing errors.
1.3
2015/05/29
1. Update QFN46 package information.
2. Update UART baud rate sample.
1.4
2015/08/21
1. Add Note for P2.n GPIO setting if ADC function is used.
2. Update PLL recommend input/output frequency setting table.
1.5
2016/07/22
1. Fix typing errors.
2. Add Notice: HCLK MUST be equal or less than 24MHz during Flash program and
erase operations.
3. Update LQFP48 package information.
1.6
2016/12/02
1. Fix typing errors.
2. Remove SN32F74X & SN32F73X.
3. Remove SYSTICKPRE[1:0]
1.7
2017/06/05
1. Remove SYS0_ANTIEFT register.
2. Fix Deep Sleep mode wake up time.
3. Update SN-LINK-V3.0 information.
1.8
2017/07/14
1. Update WDTPRE[2:0] bits description in SYS1_APBCP1 register.
2. Update TO[15:0] bits description in I2Cn_TOCTRL register.
1.9
2017/12/21
1. Update LCD drive waveform.
2. Add Note for setting the pins which are not pin-out.
2.0
2018/10/05
1. Add Boot pin description.
2. Fix maximum FADCLK to 16MHz in Electrical Characteristics.

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 Version 2.0
Table of Content
AMENDENT HISTORY................................................................................................................................ 2
1
1
1
PRODUCT OVERVIEW....................................................................................................................... 14
1.1 FEATURES...................................................................................................................................... 14
1.2 SYSTEM BLOCK DIAGRAM........................................................................................................ 16
1.3 CLOCK GENERATION BLOCK DIAGRAM................................................................................ 17
1.4 PIN ASSIGNMENT......................................................................................................................... 18
1.5 PIN DESCRIPTIONS....................................................................................................................... 23
1.6 PIN CIRCUIT DIAGRAMS............................................................................................................. 28
2
2
2
CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 30
2.1 MEMORY MAP............................................................................................................................... 30
2.2 SYSTEM TICK TIMER................................................................................................................... 31
2.2.1 OPERATION ............................................................................................................................ 31
2.2.2 SYSTICK USAGE HINTS AND TIPS ....................................................................................... 32
2.2.3 SYSTICK REGISTERS.............................................................................................................. 32
2.2.3.1 System Tick Timer Control and Status register (SYSTICK_CTRL)................................... 32
2.2.3.2 System Tick Timer Reload value register (SYSTICK_LOAD)........................................... 32
2.2.3.3 System Tick Timer Current Value register (SYSTICK_VAL)............................................ 33
2.2.3.4 System Tick Timer Calibration Value register (SYSTICK_CALIB) .................................. 33
2.3 NESTED VECTORED INTERRUPT CONTROLLER (NVIC) ..................................................... 34
2.3.1 INTERRUPT AND EXCEPTION VECTORS ........................................................................... 34
2.3.2 NVIC REGISTERS.................................................................................................................... 35
2.3.2.1 IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER)....................................................... 35
2.3.2.2 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER)................................................... 35
2.3.2.3 IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR) ..................................................... 36
2.3.2.4 IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR) ................................................. 36
2.3.2.5 IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7)............................................... 36
2.4 APPLICATION INTERRUPT AND RESET CONTROL (AIRC).................................................. 37
2.5 CODE OPTION TABLE.................................................................................................................. 38
2.6 CORE REGISTER OVERVIEW ..................................................................................................... 39
3
3
3
SYSTEM CONTROL............................................................................................................................. 40
3.1 RESET.............................................................................................................................................. 40
3.1.1 POWER-ON RESET (POR)...................................................................................................... 40
3.1.2 WATCHDOG RESET (WDT RESET)....................................................................................... 41
3.1.3 BROWN-OUT RESET............................................................................................................... 41

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 4 Version 2.0
3.1.3.1 BROWN OUT DESCRIPTION........................................................................................... 41
3.1.3.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION............................................... 42
3.1.3.3 BROWN-OUT RESET IMPROVEMENT.......................................................................... 42
3.1.4 EXTERNAL RESET .................................................................................................................. 43
3.1.4.1 SIMPLY RC RESET CIRCUIT........................................................................................... 44
3.1.4.2 DIODE & RC RESET CIRCUIT......................................................................................... 44
3.1.4.3 ZENER DIODE RESET CIRCUIT...................................................................................... 45
3.1.4.4 VOLTAGE BIAS RESET CIRCUIT................................................................................... 45
3.1.4.5 EXTERNAL RESET IC....................................................................................................... 46
3.1.5 SOFTWARE RESET ................................................................................................................. 46
3.2 SYSTEM CLOCK............................................................................................................................ 47
3.2.1 INTERNAL RC CLOCK SOURCE ........................................................................................... 47
3.2.1.1 Internal High-speed RC Oscillator (IHRC).......................................................................... 47
3.2.1.2 Internal Low-speed RC Oscillator (ILRC)........................................................................... 47
3.2.2 PLL ........................................................................................................................................... 48
3.2.2.1 PLL Frequency selection...................................................................................................... 48
3.2.3 EXTERNAL CLOCK SOURCE ................................................................................................ 49
3.2.3.1 External High-speed (EHS) Clock ....................................................................................... 49
3.2.3.2 CRYSTAL/CERAMIC......................................................................................................... 49
3.2.3.3 External Low-speed (ELS) Clock......................................................................................... 50
3.2.3.4 CRYSTAL............................................................................................................................ 50
3.2.3.5 Bypass Mode ........................................................................................................................ 50
3.2.4 SYSTEM CLOCK (SYSCLK) SELECTION............................................................................... 51
3.2.5 CLOCK-OUT CAPABITITY..................................................................................................... 51
3.3 SYSTEM CONTROL REGISTERS 0.............................................................................................. 52
3.3.1 Analog Block Control register (SYS0_ANBCTRL)................................................................... 52
3.3.2 PLL control register (SYS0_PLLCTRL)................................................................................... 52
3.3.2.1 RECOMMEND FREQUENCY SETTING.......................................................................... 53
3.3.3 Clock Source Status register (SYS0_CSST).............................................................................. 53
3.3.4 System Clock Configuration register (SYS0_CLKCFG).......................................................... 54
3.3.5 AHB Clock Prescale register (SYS0_AHBCP)......................................................................... 54
3.3.6 System Reset Status register (SYS0_RSTST) ............................................................................ 55
3.3.7 LVD Control register (SYS0_LVDCTRL)................................................................................. 55
3.3.8 External RESET Pin Control register (SYS0_EXRSTCTRL) ................................................... 56
3.3.9 SWD Pin Control register (SYS0_SWDCTRL)......................................................................... 56
3.4 SYSTEM CONTROL REGISTERS 1.............................................................................................. 57
3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN).................................................................... 57
3.4.2 APB Clock Prescale register 0 (SYS1_APBCP0)..................................................................... 58
3.4.3 APB Clock Prescale register 1 (SYS1_APBCP1)..................................................................... 59
3.4.4 APB Clock Prescale register 2 (SYS1_APBCP2)..................................................................... 61

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
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3.4.5 Peripheral Reset register (SYS1_PRST)................................................................................... 61
3.4.6 Divider Dividend register (SYS1_DIVIDEND)........................................................................ 63
3.4.7 Divider Divisor register (SYS1_DIVISOR) .............................................................................. 63
3.4.8 Divider Quotient register (SYS1_QUOTIENT)........................................................................ 63
3.4.9 Divider Remainder register (SYS1_REMAINDER).................................................................. 63
3.4.10 Divider Control register (SYS1_DIVCTRL)............................................................................. 64
4
4
4
SYSTEM OPERATION MODE........................................................................................................... 65
4.1 OVERVIEW..................................................................................................................................... 65
4.2 NORMAL MODE ............................................................................................................................ 65
4.3 LOW-POWER MODES................................................................................................................... 65
4.3.1 SLEEP MODE.......................................................................................................................... 65
4.3.2 DEEP-SLEEP MODE............................................................................................................... 66
4.3.3 DEEP POWER-DOWN (DPD) MODE.................................................................................... 66
4.3.3.1 Entering Deep power-down mode........................................................................................ 67
4.3.3.2 Exiting Deep power-down mode.......................................................................................... 67
4.4 WAKEUP......................................................................................................................................... 68
4.4.1 OVERVIEW .............................................................................................................................. 68
4.4.2 WAKEUP TIME........................................................................................................................ 68
4.5 STATE MACHINE OF PMU........................................................................................................... 69
4.6 OPERATION MODE COMPARSION TABLE .............................................................................. 70
4.7 PMU REGISTERS ........................................................................................................................... 71
4.7.1 Backup registers 0~15 (PMU_BKP0~15)................................................................................ 71
4.7.2 Power Control register (PMU_CTRL)..................................................................................... 71
4.7.3 I/O Latch Control register 1 (PMU_LATCHCTRL1)............................................................... 71
4.7.4 I/O Latch Control register 2 (PMU_LATCHCTRL2)............................................................... 72
4.7.5 I/O Latch Status register (PMU_LATCHST)............................................................................ 72
5
5
5
GENERAL PURPOSE I/O PORT (GPIO).......................................................................................... 73
5.1 OVERVIEW..................................................................................................................................... 73
5.2 GPIO MODE .................................................................................................................................... 73
5.3 GPIO REGISTERS........................................................................................................................... 74
5.3.1 GPIO Port n Data register (GPIOn_DATA) (n=0,1,2,3)......................................................... 74
5.3.2 GPIO Port n Mode register (GPIOn_MODE) (n=0,1,2,3)...................................................... 74
5.3.3 GPIO Port n Configuration register (GPIOn_CFG) (n=0,1,2,3)............................................ 74
5.3.4 GPIO Port n Interrupt Sense register (GPIOn_IS) (n=0,1,2,3)............................................... 76
5.3.5 GPIO Port n Interrupt Both-edge Sense register (GPIOn_IBS) (n=0,1,2,3)........................... 76
5.3.6 GPIO Port n Interrupt Event register (GPIOn_IEV) (n=0,1,2,3)............................................ 76
5.3.7 GPIO Port n Interrupt Enable register (GPIOn_IE) (n=0,1,2,3)............................................ 76
5.3.8 GPIO Port n Raw Interrupt Status register (GPIOn_RIS) (n=0,1,2,3) ................................... 77

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
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5.3.9 GPIO Port n Interrupt Clear register (GPIOn_IC) (n=0,1,2,3).............................................. 77
5.3.10 GPIO Port n Bits Set Operation register (GPIOn_BSET) (n=0,1,2,3).................................... 77
5.3.11 GPIO Port n Bits Clear Operation register (GPIOn_BCLR) (n=0,1,2,3)............................... 77
5.3.12 GPIO Port n Open-Drain Control register (GPIOn_ODCTRL) (n=0,1,2,3) .......................... 78
6
6
6
PERIPHERAL FUNCTION PIN ASSIGNMENT (PFPA)................................................................ 79
6.1 OVERVIEW..................................................................................................................................... 79
6.2 FEATURES...................................................................................................................................... 79
6.3 PIN ASSIGNMENT LIST................................................................................................................ 79
6.4 PFPA REGISTERS........................................................................................................................... 80
6.4.1 PFPA for UART register (PFPA_UART)................................................................................. 80
6.4.2 PFPA for I2C register (PFPA_I2C)......................................................................................... 81
6.4.3 PFPA for SSP register (PFPA_SSP)........................................................................................ 82
6.4.4 PFPA for I2S register (PFPA_I2S).......................................................................................... 83
6.4.5 PFPA for CT16B0 register (PFPA_CT16B0).......................................................................... 84
6.4.6 PFPA for CT16B1 register (PFPA_CT16B1).......................................................................... 85
6.4.7 PFPA for CT16B2 register (PFPA_CT16B2).......................................................................... 86
6.4.8 PFPA for CT32B0 register (PFPA_CT32B0).......................................................................... 86
6.4.9 PFPA for CT32B1 register (PFPA_CT32B1).......................................................................... 87
6.4.10 PFPA for CT32B2 register (PFPA_CT32B2).......................................................................... 88
7
7
7
14+1 CHANNEL ANALOG TO DIGITAL CONVERTOR (ADC).................................................. 90
7.1 OVERVIEW..................................................................................................................................... 90
7.2 ADC CONVERTING TIME ............................................................................................................ 91
7.3 ADC CONTROL NOTICE............................................................................................................... 92
7.3.1 ADC SIGNAL............................................................................................................................ 92
7.3.2 ADC PROGRAM ...................................................................................................................... 92
7.4 ADC CIRCUIT................................................................................................................................. 92
7.5 TEMPERATURE SENSOR (TS)..................................................................................................... 93
7.6 ADC REGISTERS............................................................................................................................ 94
7.6.1 ADC Management register (ADC_ADM)................................................................................. 94
7.6.2 ADC Data register (ADC_ADB) .............................................................................................. 95
7.6.3 Port 2 Control register (ADC_P2CON)................................................................................... 95
7.6.4 ADC Interrupt Enable register (ADC_IE)................................................................................ 96
7.6.5 ADC Raw Interrupt Status register (ADC_RIS)....................................................................... 96
8
8
8
16-BIT TIMER WITH CAPTURE FUNCTION ................................................................................ 97
8.1 OVERVIEW..................................................................................................................................... 97
8.2 FEATURES...................................................................................................................................... 97
8.3 PIN DESCRIPTION......................................................................................................................... 97
8.4 BLOCK DIAGRAM......................................................................................................................... 98

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 7 Version 2.0
8.5 TIMER OPERATION ...................................................................................................................... 99
8.5.1 Edge-aligned Up-counting Mode ............................................................................................. 99
8.5.2 Edge-aligned Down-counting Mode....................................................................................... 100
8.5.3 Center-aligned Counting Mode.............................................................................................. 100
8.6 PWM............................................................................................................................................... 101
8.6.1 PWM Mode 1.......................................................................................................................... 101
8.6.2 PWM Mode 2.......................................................................................................................... 102
8.7 CT16BN REGISTERS.................................................................................................................... 104
8.7.1 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=0,1,2) ........................................ 104
8.7.2 CT16Bn Timer Counter register (CT16Bn_TC) (n=0,1,2) .................................................... 104
8.7.3 CT16Bn Prescale register (CT16Bn_PRE) (n=0,1,2)............................................................ 105
8.7.4 CT16Bn Prescale Counter register (CT16Bn_PC) (n=0,1,2)................................................ 105
8.7.5 CT16Bn Count Control register (CT16Bn_CNTCTRL) (n=0,1,2)......................................... 105
8.7.6 CT16Bn Match Control register (CT16Bn_MCTRL) (n=0,1,2) ............................................ 106
8.7.7 CT16Bn Match register 0~3 (CT16Bn_MR0~3) (n=0,1,2).................................................... 107
8.7.8 CT16Bn Capture Control register (CT16Bn_CAPCTRL) (n=0,1,2) ..................................... 107
8.7.9 CT16Bn Capture 0 register (CT16Bn_CAP0) (n=0,1,2) ....................................................... 107
8.7.10 CT16Bn External Match register (CT16Bn_EM) (n=0,1,2) ............................................... 108
8.7.11 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=0,1,2)........................................ 108
8.7.12 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=0,1,2) ............................... 109
8.7.13 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=0,1,2).......................................... 110
9
9
9
32-BIT TIMER WITH CAPTURE FUNCTION .............................................................................. 111
9.1 OVERVIEW................................................................................................................................... 111
9.2 FEATURES.................................................................................................................................... 111
9.3 PIN DESCRIPTION....................................................................................................................... 111
9.4 BLOCK DIAGRAM....................................................................................................................... 112
9.5 TIMER OPERATION .................................................................................................................... 113
9.5.1 Edge-aligned Up-counting Mode ........................................................................................... 113
9.5.2 Edge-aligned Down-counting Mode....................................................................................... 114
9.5.3 Center-aligned Counting Mode.............................................................................................. 114
9.6 PWM............................................................................................................................................... 115
9.6.1 PWM Mode 1.......................................................................................................................... 115
9.6.2 PWM Mode 2.......................................................................................................................... 116
9.7 CT32BN REGISTERS.................................................................................................................... 118
9.7.1 CT32Bn Timer Control register (CT32Bn_TMRCTRL) (n=0,1,2) ........................................ 118
9.7.2 CT32Bn Timer Counter register (CT32Bn_TC) (n=0,1,2) .................................................... 118
9.7.3 CT32Bn Prescale register (CT32Bn_PRE) (n=0,1,2)............................................................ 119
9.7.4 CT32Bn Prescale Counter register (CT32Bn_PC) (n=0,1,2)................................................ 119
9.7.5 CT32Bn Count Control register (CT32Bn_CNTCTRL) (n=0,1,2)......................................... 119

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
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9.7.6 CT32Bn Match Control register (CT32Bn_MCTRL) (n=0,1,2) ............................................ 120
9.7.7 CT32Bn Match register 0~3 (CT32Bn_MR0~3) (n=0,1,2).................................................... 120
9.7.8 CT32Bn Capture Control register (CT32Bn_CAPCTRL) (n=0,1,2) ..................................... 121
9.7.9 CT32Bn Capture 0 register (CT32Bn_CAP0) (n=0,1,2) ....................................................... 121
9.7.10 CT32Bn External Match register (CT32Bn_EM) (n=0,1,2) .................................................. 121
9.7.11 CT32Bn PWM Control register (CT32Bn_PWMCTRL) (n=0,1,2)........................................ 122
9.7.12 CT32Bn Timer Raw Interrupt Status register (CT32Bn_RIS) (n=0,1,2) ............................... 123
9.7.13 CT32Bn Timer Interrupt Clear register (CT32Bn_IC) (n=0,1,2).......................................... 124
1
1
10
0
0
WATCHDOG TIMER (WDT)........................................................................................................ 125
10.1 OVERVIEW................................................................................................................................... 125
10.2 BLOCK DIAGRAM....................................................................................................................... 126
10.3 WDT REGISTERS......................................................................................................................... 127
10.3.1 Watchdog Configuration register (WDT_CFG)..................................................................... 127
10.3.2 Watchdog Clock Source register (WDT_CLKSOURCE)....................................................... 127
10.3.3 Watchdog Timer Constant register (WDT_TC)...................................................................... 127
10.3.4 Watchdog Feed register (WDT_FEED)................................................................................. 128
1
1
11
1
1
REAL-TIME CLOCK (RTC) ......................................................................................................... 129
11.1 OVERVIEW................................................................................................................................... 129
11.2 FEATURES.................................................................................................................................... 129
11.3 FUNCTIONAL DESCRIPTION.................................................................................................... 129
11.3.1 INTRODUCTION................................................................................................................... 129
11.3.2 RESET RTC REGISTERS....................................................................................................... 129
11.3.3 RTC FLAG ASSERTION ........................................................................................................ 129
11.3.4 RTC OPERATION.................................................................................................................. 130
11.4 BLOCK DIAGRAM....................................................................................................................... 131
11.5 RTC REGISTERS .......................................................................................................................... 132
11.5.1 RTC Control register (RTC_CTRL) ....................................................................................... 132
11.5.2 RTC Clock Source Select register (RTC_CLKS).................................................................... 132
11.5.3 RTC Interrupt Enable register (RTC_IE)............................................................................... 132
11.5.4 RTC Raw Interrupt Status register (RTC_RIS) ...................................................................... 132
11.5.5 RTC Interrupt Clear register (RTC_IC)................................................................................. 133
11.5.6 RTC Second Counter Reload Value register (RTC_SECCNTV)............................................ 133
11.5.7 RTC Second Count register (RTC_SECCNT) ........................................................................ 133
11.5.8 RTC Alarm Counter Reload Value register (RTC_ALMCNTV)............................................. 133
11.5.9 RTC Alarm Count register (RTC_ALMCNT)......................................................................... 134
1
1
12
2
2
SPI/SSP.............................................................................................................................................. 135
12.1 OVERVIEW................................................................................................................................... 135
12.2 FEATURES.................................................................................................................................... 135

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
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12.3 PIN DESCRIPTION....................................................................................................................... 135
12.4 INTERFACE DESCRIPTION ....................................................................................................... 136
12.4.1 SPI .......................................................................................................................................... 136
12.4.2 SSI........................................................................................................................................... 137
12.4.3 COMMUNICATION FLOW................................................................................................... 137
12.4.3.1 SINGLE-FRAME........................................................................................................... 137
12.4.3.2 MULTI-FRAME ............................................................................................................ 138
12.5 AUTO-SEL..................................................................................................................................... 138
12.6 SSP REGISTERS ........................................................................................................................... 139
12.6.1 SSP n Control register 0 (SSPn_CTRL0) (n=0,1).................................................................. 139
12.6.2 SSP n Control register 1 (SSPn_CTRL1) (n=0,1).................................................................. 140
12.6.3 SSP n Clock Divider register (SSPn_CLKDIV) (n=0,1)........................................................ 140
12.6.4 SSP n Status register (SSPn_STAT) (n=0,1).......................................................................... 140
12.6.5 SSP n Interrupt Enable register (SSPn_IE) (n=0,1) .............................................................. 141
12.6.6 SSP n Raw Interrupt Status register (SSPn_RIS) (n=0,1)...................................................... 141
12.6.7 SSP n Interrupt Clear register (SSPn_IC) (n=0,1) ................................................................ 142
12.6.8 SSP n Data register (SSPn_DATA) (n=0,1)........................................................................... 142
12.6.9 SSP n Data Fetch register (SSPn_DF) (n=0,1) ..................................................................... 142
1
1
13
3
3
I2C...................................................................................................................................................... 143
13.1 OVERVIEW................................................................................................................................... 143
13.2 FEATURES.................................................................................................................................... 143
13.3 PIN DESCRIPTION....................................................................................................................... 144
13.4 WAVE CHARACTERISTICS....................................................................................................... 144
13.5 I2C MASTER MODES .................................................................................................................. 145
13.5.1 MASTER TRANSMITTER MODE.......................................................................................... 145
13.5.2 MASTER RECEIVER MODE................................................................................................. 145
13.5.3 ARBITRATION ....................................................................................................................... 145
13.6 I2C SLAVE MODES...................................................................................................................... 146
13.6.1 SLAVE TRANSMITTER MODE ............................................................................................. 146
13.6.2 SLAVE RECEIVER MODE .................................................................................................... 146
13.7 MONITOR MODE......................................................................................................................... 147
13.7.1 INTERRUPT........................................................................................................................... 147
13.7.2 LOSS of ARBITRATION......................................................................................................... 147
13.8 I2C REGISTERS............................................................................................................................ 148
13.8.1 I2C n Control register (I2Cn_CTRL) (n=0,1)........................................................................ 148
13.8.2 I2C n Status register (I2Cn_STAT) (n=0,1)........................................................................... 149
13.8.3 I2C n TX Data register (I2Cn_TXDATA) (n=0,1) ................................................................. 150
13.8.4 I2C n RX Data register (I2Cn_RXDATA) (n=0,1)................................................................. 150
13.8.5 I2C n Slave Address 0 register (I2Cn_SLVADDR0) (n=0,1)................................................. 150

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32-Bit Cortex-M0 Micro-Controller
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13.8.6 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0,1) ........................................ 150
13.8.7 I2C n SCL High Time register (I2Cn_SCLHT) (n=0,1)......................................................... 151
13.8.8 I2C n SCL Low Time register (I2Cn_SCLLT) (n=0,1)........................................................... 151
13.8.9 I2C n Timeout Control register (I2Cn_TOCTRL) (n=0,1) .................................................... 151
13.8.10 I2C n Monitor Mode Control register (I2Cn_MMCTRL) (n=0,1)..................................... 151
1
1
14
4
4
UNIVERSAL SYNCHRONOUS AND ASYNCHRONOUS RECEIVER AND TRANSMITTER
(USART)........................................................................................................................................................ 153
14.1 OVERVIEW................................................................................................................................... 153
14.2 FEATURES.................................................................................................................................... 153
14.3 PIN DESCRIPTION....................................................................................................................... 153
14.4 BLOCK DIAGRAM....................................................................................................................... 154
14.5 EIA-485/RS-485 MODES.............................................................................................................. 155
14.5.1 RS-485/EIA-485 NORMAL MULTIDROP MODE (NMM).................................................... 155
14.5.2 RS-485/EIA-485 AUTO ADDRESS DETECTION (AAD) MODE ......................................... 155
14.5.3 RS-485/EIA-485 AUTO DIRECTION CONTROL (ADC)...................................................... 155
14.5.4 RS485/EIA-485 DRIVER DELAY TIME................................................................................. 156
14.5.5 RS485/EIA-485 OUTPUT INVERSION ................................................................................. 156
14.5.6 RS485/EIA-485 FRAME STRUCTURE.................................................................................. 156
14.6 BAUD RATE CALCULATION .................................................................................................... 156
14.7 MODEM CONTROL (MC)............................................................................................................ 158
14.7.1 AUTO-RTS.............................................................................................................................. 158
14.7.2 AUTO-CTS.............................................................................................................................. 159
14.8 AUTO-BAUD FLOW .................................................................................................................... 159
14.8.1 AUTO-BAUD.......................................................................................................................... 159
14.8.2 AUTO-BAUD MODES ........................................................................................................... 160
14.9 SMART CARD MODE.................................................................................................................. 161
14.9.1 SMART CARD SETUP PROCEDURE................................................................................... 161
14.10 SYNCHRONOUS MODE.......................................................................................................... 162
14.11 USART REGISTERS................................................................................................................. 164
14.11.1 USART n Receiver Buffer register (USARTn_RB) (n=0,1)................................................ 164
14.11.2 USART n Transmitter Holding register (USARTn_TH) (n=0,1)........................................ 164
14.11.3 USART n Divisor Latch LSB registers (USARTn_DLL) (n =0,1)...................................... 164
14.11.4 USART n Divisor Latch MSB register (USARTn_DLM) (n=0,1) ...................................... 164
14.11.5 USART n Interrupt Enable register (USARTn_IE) (n=0,1) ............................................... 165
14.11.6 USART n Interrupt Identification register (USARTn_II) (n=0,1)...................................... 165
14.11.7 USART n Line Status register (USARTn_LS) (n=0,1)........................................................ 167
14.11.8 USART n FIFO Control register (USARTn_FIFOCTRL) (n=0,1)..................................... 168
14.11.9 USART n Line Control register (USARTn_LC) (n=0,1) .................................................... 168
14.11.10 USART n Modem Control register (USARTn_MC) (n=0,1) .............................................. 169

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 11 Version 2.0
14.11.11 USART n Modem Status register (USARTn_MS) (n=0,1).................................................. 169
14.11.12 USART n Scratch Pad register (USARTn_SP) (n=0,1)...................................................... 170
14.11.13 USART n Auto-baud Control register (USARTn_ABCTRL) (n=0,1)................................. 170
14.11.14 USART n Fractional Divider register (USARTn_FD) (n=0,1).......................................... 170
14.11.15 USART n Control register (USARTn_CTRL) (n=0,1)........................................................ 171
14.11.16 USART n Half-duplex Enable register (USARTn_HDEN) (n=0,1) ................................... 172
14.11.17 USART n Smart card Interface Control register (USARTn_SCICTRL) (n=0,1) ............... 172
14.11.18 USART n RS485 Control register (USARTn_RS485CTRL) (n=0,1).................................. 173
14.11.19 USART n RS485 Address Match register (USARTn_RS485ADRMATCH) (n=0,1) .......... 173
14.11.20 USART n RS485 Delay Value register (USARTn_RS485DLYV) (n=0,1).......................... 173
14.11.21 USART n Synchronous Mode Control Register (USARTn_SYNCCTRL) (n=0,1) ............. 174
1
1
15
5
5
I2S ...................................................................................................................................................... 175
15.1 OVERVIEW................................................................................................................................... 175
15.2 FEATURES.................................................................................................................................... 175
15.3 PIN DESCRIPTION....................................................................................................................... 175
15.4 BLOCK DIAGRAM....................................................................................................................... 176
15.4.1 I2S CLCOK CONTROL.......................................................................................................... 176
15.4.2 I2S BLOCK DIAGRAM .......................................................................................................... 176
15.5 FUNCTIONAL DESCRIPTION.................................................................................................... 177
15.5.1 I2S OPERATION.................................................................................................................... 177
15.5.2 I2S FIFO OPERAION............................................................................................................ 179
15.5.2.1 MONO............................................................................................................................ 179
15.5.2.2 STEREO......................................................................................................................... 179
15.6 I2S REGISTERS............................................................................................................................. 180
15.6.1 I2S Control register (I2S_CTRL) ........................................................................................... 180
15.6.2 I2S Clock register (I2S_CLK)................................................................................................. 181
15.6.3 I2S Status register (I2S_STATUS).......................................................................................... 181
15.6.4 I2S Interrupt Enable register (I2S_IE)................................................................................... 182
15.6.5 I2S Raw Interrupt Status register (I2S_RIS) .......................................................................... 182
15.6.6 I2S Interrupt Clear register (I2S_IC)..................................................................................... 183
15.6.7 I2S RXFIFO register (I2S_RXFIFO) ..................................................................................... 183
15.6.8 I2S TXFIFO register (I2S_TXFIFO)...................................................................................... 183
1
1
16
6
6
4X32 LCD DRIVER......................................................................................................................... 184
16.1 OVERVIEW................................................................................................................................... 184
16.2 FEATURES.................................................................................................................................... 184
16.3 PIN DESCRIPTION....................................................................................................................... 184
16.4 BLOCK DIAGRAM....................................................................................................................... 185
16.4.1 LCD CLOCK CONTROL ....................................................................................................... 185

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 12 Version 2.0
16.4.2 LCD BLOCK DIAGRAM........................................................................................................ 185
16.5 LCD TIMING................................................................................................................................. 186
16.5.1 LCD Timing Table.................................................................................................................. 186
16.5.2 LCD Driver Waveform ........................................................................................................... 186
16.6 R-TYPE LCD APPLICATION CIRCUIT...................................................................................... 188
16.7 C-TYPE LCD APPLICATION CIRCUIT...................................................................................... 189
16.7.1 4C-TYPE................................................................................................................................. 190
16.7.2 1C-Type .................................................................................................................................. 192
16.8 LCD DISPLAY MEMORY MAP .................................................................................................. 193
16.9 LCD REGISTERS.......................................................................................................................... 194
16.9.1 LCD Control register (LCD_CTRL)....................................................................................... 194
16.9.2 LCD Control register 1(LCD_CTRL1)................................................................................... 195
16.9.3 LCD C-Type Control register 1 (LCD_CCTRL1).................................................................. 195
16.9.4 LCD C-Type Control register 2 (LCD_CCTRL2).................................................................. 196
16.9.5 LCD Frame Counter Control register (LCD_FCC)............................................................... 196
16.9.6 LCD Raw Interrupt Status register (LCD_RIS) ..................................................................... 197
16.9.7 LCD SEG Memory register 0 (LCD_SEGM0)....................................................................... 197
16.9.8 LCD SEG Memory register 1 (LCD_SEGM1)....................................................................... 198
16.9.9 LCD SEG Memory register 2 (LCD_SEGM2)....................................................................... 198
16.9.10 LCD SEG Memory register 3 (LCD_SEGM3)................................................................... 198
1
1
17
7
7
FLASH............................................................................................................................................... 200
17.1 OVERVIEW................................................................................................................................... 200
17.2 EMBEDDED FLASH MEMORY.................................................................................................. 200
17.3 FEATURES.................................................................................................................................... 200
17.4 ORGANIZATION.......................................................................................................................... 201
17.5 READ ............................................................................................................................................. 201
17.6 PROGRAM/ERASE....................................................................................................................... 201
17.7 EMBEDDED BOOT LOADER ..................................................................................................... 201
17.8 FLASH MEMORY CONTROLLER (FMC).................................................................................. 202
17.8.1 CODE SECURITY (CS).......................................................................................................... 202
17.8.2 PROGRAM FLASH MEMORY............................................................................................... 203
17.8.3 ERASE .................................................................................................................................... 203
17.8.3.1 PAGE ERASE................................................................................................................ 203
17.8.3.2 MASS ERASE................................................................................................................ 203
17.9 READ PROTECTION.................................................................................................................... 203
17.10 HW CHECKSUM....................................................................................................................... 203
17.11 FMC REGISTERS...................................................................................................................... 204
17.11.1 Flash Low Power Control register (FLASH_LPCTRL)..................................................... 204
17.11.2 Flash Status register (FLASH_STATUS) ........................................................................... 204

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 13 Version 2.0
17.11.3 Flash Control register (FLASH_CTRL)............................................................................. 204
17.11.4 Flash Data register (FLASH_DATA)................................................................................. 205
17.11.5 Flash Address register (FLASH_ADDR) ........................................................................... 205
17.11.6 Flash Checksum register (FLASH_CHKSUM).................................................................. 205
1
1
18
8
8
SERIAL-WIRE DEBUG (SWD)..................................................................................................... 206
18.1 OVERVIEW................................................................................................................................... 206
18.2 FEATURES.................................................................................................................................... 206
18.3 PIN DESCRIPTION....................................................................................................................... 206
18.4 DEBUG NOTE............................................................................................................................... 206
18.4.1 LIMITATIONS........................................................................................................................ 206
18.4.2 DEBUG RECOVERY.............................................................................................................. 206
18.4.3 INTERNAL PULL-UP/DOWN RESISTORS on SWD PINS................................................... 207
1
1
19
9
9
DEVELOPMENT TOOL ................................................................................................................ 208
19.1 SN-LINK-V3.................................................................................................................................. 209
19.2 SN32F760 STARTER-KIT ............................................................................................................ 210
2
2
20
0
0
ELECTRICAL CHARACTERISTIC............................................................................................ 212
20.1 ABSOLUTE MAXIMUM RATING.............................................................................................. 212
20.2 ELECTRICAL CHARACTERISTIC............................................................................................. 212
20.3 CHARACTERISTIC GRAPHS ..................................................................................................... 214
2
2
21
1
1
FLASH ROM PROGRAMMING PIN........................................................................................... 216
2
2
22
2
2
PACKAGE INFORMATION ......................................................................................................... 217
22.1 LQFP 80 PIN .................................................................................................................................. 217
22.2 LQFP 64 PIN .................................................................................................................................. 218
22.3 LQFP 48 PIN .................................................................................................................................. 219
22.4 QFN 46 PIN.................................................................................................................................... 220
22.5 QFN 33 PIN 5X5............................................................................................................................. 221
2
2
23
3
3
MARKING DEFINITION............................................................................................................... 222
23.1 INTRODUCTION.......................................................................................................................... 222
23.2 MARKING INDETIFICATION SYSTEM.................................................................................... 222
23.3 MARKING EXAMPLE ................................................................................................................. 223
23.4 DATECODE SYSTEM.................................................................................................................. 224

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 14 Version 2.0
1
1
1
PRODUCT OVERVIEW
1.1 FEATURES

Memory configuration

Timer
Up to 64KB on-chip Flash programming memory.
3 16-bit and 3 32-bit general purpose timers with
Up to 8KB SRAM.
a total of 6 capture inputs and 21 PWMs.
4KB Boot ROM

Working voltage 1.8V ~ 5.5V

Operation Frequency up to 50MHz

ADC

Interrupt sources
14-channel 12-bit SAR ADC
ARM Cortex-M0 built-in Nested Vectored Interrupt
Temperature sensor inside
Controller (NVIC).

I/O pin configuration

Interface
Up to 64 General Purpose I/O (GPIO) pins with
-Two I2C controllers supporting I2C-bus specification
configurable pull-up/pull-down resistors.
with multiple address recognition and monitor mode.
GPIO pins can be used as edge and level sensitive
- USART controller with fractional baud rate
interrupt sources.
generation, and EIA-485 support.
High-current source driver (20 mA)
- UART controller with fractional baud rate generation.
-Two SPI controllers with SSP features and multi-

Programmable Watchdog Timer (WDT)
protocol capabilities.
Programmable watchdog frequency with watchdog
-I2S Function with mono and stereo audio data
clock source and divider.
supported, MSB justified data format supported, and
can operate as either master or slave.

System tick timer
24-bit timer.

System clocks
The system tick timer clock is fixed to the frequency of
-External high clock: Crystal type 10MHz~25MHz
the system clock.
-External low clock: Crystal type 32.768 KHz
The SysTick timer is intended to generate a fixed
-Internal high clock: RC type 12 MHz
10-ms interrupt.
-Internal low clock: RC type 32 KHz
-PLL allows CPU operation up to the maximum CPU

Hardware divider
rate without the need for a high-frequency crystal.
-Clock output function which can reflect the internal

Real-Time Clock (RTC)
high/low RC oscillator, HCLK, PLL output, and
external high/low clock.

LVD with separate thresholds
Reset: 1.65V for VCORE

LCD driver
Reset: 1.8V/2.0V/2.4V/2.7V/3.0V/3.6V for VDD
Support both R-type and C-type
Interrupt: 1.8V/2.0V/2.4V/2.7V/3.0V/3.6V for VDD
4 common x 32 segment
1/3 or 1/2 bias voltage

Fcpu (Instruction cycle)
Multiple C-type LCD Voltage: 2.7 ~5.0V
FCPU = FHCLK = FSYSCLK/1, FSYSCLK /2, FSYSCLK /4, …,
R-type optional-bias resistor: 400K, 200K, 100K, 35K
FSYSCLK /512.
Support 1/2 duty, 1/3 duty, 1/4 duty

Operating modes

In-System Programming (ISP) supported
Normal, Sleep, Deep-sleep, Power-down, and Deep
power-down

Package (Chip form support)
LQFP 80/64/48 pin

Serial Wire Debug (SWD)
QFN 46/33 pin

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 15 Version 2.0
Features Selection Table
Chip
ROM
RAM
Boot
Loader
FCPU
(Max
MHz)
TIMER
USART
SPI
I2C
I2S
PWM
12-bit
ADC
LCD
GPIO
with
Wakeup
Package
SN32F769F
64KB
8KB
4KB
50 MHz
16-bitx3
32-bitx3
USARTx1
UARTx1
2
2
1
21
14CH
4x32
64
LQFP80
SN32F768F
64KB
8KB
4KB
50 MHz
16-bitx3
32-bitx3
USARTx1
UARTx1
2
2
1
21
11CH
4x28
57
LQFP64
SN32F767F
64KB
8KB
4KB
50 MHz
16-bitx3
32-bitx3
USARTx1
UARTx1
2
2
1
21
8CH
4x18
42
LQFP48
SN32F766J
64KB
8KB
4KB
50 MHz
16-bitx3
32-bitx3
USARTx1
UARTx1
2
2
1
21
7CH
4x17
40
QFN46
SN32F765J
64KB
8KB
4KB
50 MHz
16-bitx3
32-bitx3
UARTx2
2
2
-
21
4CH
-
26
QFN33
SN32F759F
32KB
4KB
4KB
50 MHz
16-bitx3
32-bitx3
USARTx1
UARTx1
2
2
1
21
14CH
4x32
64
LQFP80
SN32F758F
32KB
4KB
4KB
50 MHz
16-bitx3
32-bitx3
USARTx1
UARTx1
2
2
1
21
11CH
4x28
57
LQFP64
SN32F757F
32KB
4KB
4KB
50 MHz
16-bitx3
32-bitx3
USARTx1
UARTx1
2
2
1
21
8CH
4x18
42
LQFP48
SN32F756J
32KB
4KB
4KB
50 MHz
16-bitx3
32-bitx3
USARTx1
UARTx1
2
2
1
21
7CH
4x17
40
QFN46
SN32F755J
32KB
4KB
4KB
50 MHz
16-bitx3
32-bitx3
UARTx2
2
2
-
21
4CH
-
26
QFN33

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 16 Version 2.0
1.2 SYSTEM BLOCK DIAGRAM
TEST/DEBUG
INTERFACE
PIO0_0~15
PIO1_0~13
PIO2_0~15
PIO3_0~15
SWDIO
SWCLK
XTALOUT,
LXTALOUT
XTALIN,
LXTALIN
CLKOUT
CT16B2_PWM[2:0]
CT16B2_CAP0
URX0, UTX0
USCLK0
UCTS0
URTS0
SCK0
SEL0
SDI0
SDO0
SCL0
SDA0
SCK1
SEL1
SDI1
SDO1
/RESET
ARM
CORTEX-M0
CLOCK GENERATION
FLASH ROM
Up to 64KB SRAM Up to 8KB
SYS
POWER CONTROL/
SYSTEM FUNCTIONS
SPI1
I2C0
USART 0
SPI0
USART 1
POWER
REGULATOR 1
ILRC
32KHz IHRC 12MHz
LVD
Clocks
Controls
AHB-LITE BUS
AHB TO APB
BRIDGE
APB BUS
RTC
GPIO
VCORE
VDD 1.8V~5.5V
I2C1
SCL1
SDA1
URX1
UTX1
I2S
I2SBCLK
I2SWS
I2SDIN
I2SDOUT
I2SMCLK
BOOT LOADER
4KB
AIN0~AIN13
PMU
COM0~COM3
SEG0~SEG31
V3,V2,
CL+, CL- LCD
WDT
16-bit TIMER 2 with PWM
ADC
CT16B1_PWM[2:0]
CT16B1_CAP0
16-bit TIMER 1 with PWM
CT16B0_PWM[2:0]
CT16B0_CAP0
16-bit TIMER 0 with PWM
CT32B2_PWM[3:0]
CT32B2_CAP0
32-bit TIMER 2 with PWM
CT32B1_PWM[3:0]
CT32B1_CAP0
32-bit TIMER 1 with PWM
CT32B0_PWM[3:0]
CT32B0_CAP0
32-bit TIMER 0 with PWM

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 17 Version 2.0
1.3 CLOCK GENERATION BLOCK DIAGRAM
XTALOUT
XTALIN High speed
Crystal
oscillator
1MHz~25MHz
CLKOUT
PLL
1, 2, … , 32
IHRC
12MHz
ILRC
32KHz
PLLCLKSEL
IHRC
ILRC
PLLCLKout
SYSCLK
SYSCLKSEL
CLKOUTSEL
EHS Oscillator
SSPn
Clock Prescaler
/1,2,4,8,16
WDTCLKSEL
WDT
Clock Prescaler
/1, 2, 4, 8, 16, 32
WDT_PCLK
SSPn_PCLK
HCLK
AHB clock for SSPn
SSPnCLKEN
n=0, 1
WDT
register block
WDT
clock source
SSPn
register block
SSPn
clock source
AHB clock for WDT
AHB clock for AHB to APB bridge, to AHB
matrix, to Cortex-M0 FCLK, HCLK, and
System Timer, to SYS, and to PMU
AHB clock for GPIO
GPIOCLKEN
LXTALOUT
LXTALIN Low speed
Crystal
oscillator
32.768KHz
32.768KHz
GPIO block
AHB
Prescaler
/1,2,4,…,512
PLLCLKout
RTCCLKSEL
ILRC
32.768KHz
/128
ADC
Clock Prescaler
/1,2,4,8,16
ADC_PCLK
AHB clock for ADC
ADCCLKEN ADC
register block
ADC
clock source
I2S
Clock Prescaler
/1,2,3,4,8,16
I2S_PCLK
AHB clock for I2S
I2SCLKEN
I2S
register block
I2S
clock source
I2Cn
Clock Prescaler
/1,2,4,8,16
I2Cn_PCLK
AHB clock for I2Cn
I2CnCLKEN
n=0,1
I2Cn
register block
I2Cn
clock source
CT32Bn
Clock Prescaler
/1,2,4,8,16
CT32Bn_PCLK
AHB clock for CT32Bn
CT32BnCLKEN
n=0,1, 2
CT32Bn
register block
CT32Bn
clock source
CT16Bn
Clock Prescaler
/1,2,4,8,16
CT16Bn_PCLK
AHB clock for CT16Bn
CT16BnCLKEN
n=0,1, 2
CT16Bn
register block
CT16Bn
clock source
USARTn
Clock Prescaler
/1,2,4,8,16
USARTn_PCLK
AHB clock for USARTn
USARTnCLKEN
n=0,1
USARTn
register block
USARTn
clock source
AHB clock for SRAM SRAM block
AHB clock for FLASH FLASH block
Max 16MHz
CLKOUT
Prescaler
/1,2,4,…,512
WDTCLKEN
HCLK
HCLK
IHRC
ILRC
32.768KHz
EHS Oscillator
RTC_PCLK RTC
register block
RTC
clock source
AHB clock for RTC
RTCCLKEN
LCDCLK
ILRC
32.768KHz
LCD_PCLK LCD
register block
LCD
clock source
AHB clock for LCD
LCDCLKEN
PFPA blcok AHB clock for PFPA
I2SCLKSEL

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 18 Version 2.0
1.4 PIN ASSIGNMENT
SN32F769/759F (LQFP 80 pins)
P3.15/LXTALOUT
P3.14/LXTALIN
NC
NC
NC
P3.13/HXTALOUT
P3.12/HXTALIN
P3.11/CLKOUT
P3.10/RESET
P0.8/SWCLK
P0.9/SWDIO
VSS
NC
VDD
NC
NC
NC
P3.9/SEG11
P3.8/SEG10
P3.7/SEG9
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
AIN0/P2.0
1
●
60
P3.6/SEG8
AIN1/P2.1
2
59
P3.5/SEG7
BOOT/AIN2/P2.2
3
58
P3.4/SEG6
AIN3/P2.3
4
57
P3.3/SEG5
AIN4/P2.4
5
56
P3.2/SEG4
P2.14
6
55
P1.7/V2
P2.15
7
54
P1.6/V3
AIN5/P2.5
8
53
P1.8/CL-
AIN6/P2.6
9
52
P1.9/CL+
AIN7/P2.7
10
SN32F769F
SN32F759F
51
VSS
AIN8/P2.8
11
50
P3.1/SEG3
AIN9/P2.9
12
49
P3.0/SEG2
AIN10/P2.10
13
48
P1.15/SEG1
AIN11/P2.11
14
47
P1.14/SEG0
AIN12/P2.12
15
46
P1.13/COM3
AIN13/P2.13
16
45
P1.12/COM2
VSS
17
44
P1.11/COM1
AVSS
18
43
P1.10/COM0
AVDD
19
42
VDD1/VLCD1
VDD3/VLCD3
20
41
VDD2/VLCD2
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SEG31/P0.0
SEG30/P0.1
SEG29/P0.2
SEG28/P0.3
SEG27/P0.4
SEG26/P0.5
SEG25/P0.6
SEG24/P0.7
SEG23/P0.10
SEG22/P0.11
SEG21/P0.12
SEG20/P0.13
SEG19/P0.14
SEG18/P0.15
SEG17/P1.0
SEG16/P1.1
SEG15/P1.2
SEG14/P1.3
SEG13/P1.4
SEG12/P1.5

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 19 Version 2.0
SN32F768/758F (LQFP 64 pins)
P3.15/LXTALOUT
P3.14/LXTALIN
P3.13/HXTALOUT
P3.12/HXTALIN
P3.11/CLKOUT
P3.10/RESET
P0.8/SWCLK
P0.9/SWDIO
VSS
VDD
P3.9/SEG11
P3.8/SEG10
P3.7/SEG9
P3.6/SEG8
P3.5/SEG7
P3.4/SEG6
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AIN0/P2.0
1
●
48
P3.3/SEG5
AIN1/P2.1
2
47
P3.2/SEG4
BOOT/AIN2/P2.2
3
46
P1.7/V2
AIN3/P2.3
4
45
P1.6/V3
AIN4/P2.4
5
44
P1.8/CL-
P2.14
6
43
P1.9/CL+
P2.15
7
SN32F768F
SN32F758F
42
P3.1/SEG3
AIN5/P2.5
8
41
P3.0/SEG2
AIN6/P2.6
9
40
P1.15/SEG1
AIN10/P2.10
10
39
P1.14/SEG0
AIN11/P2.11
11
38
P1.13/COM3
AIN12/P2.12
12
37
P1.12/COM2
AIN13/P2.13
13
36
P1.11/COM1
AVSS
14
35
P1.10/COM0
AVDD
15
34
VDD1/VLCD1
VDD3/VLCD3
16
33
VDD2/VLCD2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SEG31/P0.0
SEG30/P0.1
SEG29/P0.2
SEG28/P0.3
SEG27/P0.4
SEG26/P0.5
SEG25/P0.6
SEG24/P0.7
SEG19/P0.14
SEG18/P0.15
SEG17/P1.0
SEG16/P1.1
SEG15/P1.2
SEG14/P1.3
SEG13/P1.4
SEG12/P1.5
Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes. Strongly recommended to set these pins as input pull-up.

SN32F760 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 20 Version 2.0
SN32F767/757 (LQFP 48 pins)
P3.15/LXTALOUT
P3.14/LXTALIN
P3.13/HXTALOUT
P3.12/HXTALIN
P3.11/CLKOUT
P3.10/RESET
P0.8/SWCLK
P0.9/SWDIO
VSS
VDD
P3.9/SEG11
P3.6/SEG8
48
47
46
45
44
43
42
41
40
39
38
37
AIN0/P2.0
1
●
36
P3.5/SEG7
AIN1/P2.1
2
35
P3.3/SEG5
BOOT/AIN2/P2.2
3
34
P3.2/SEG4
AIN3/P2.3
4
33
P1.7/V2
AIN4/P2.4
5
SN32F767F
SN32F757F
32
P1.6/V3
P2.14
6
31
P3.1/SEG3
P2.15
7
30
P3.0/SEG2
AIN5/P2.5
8
29
P1.13/COM3
AIN6/P2.6
9
28
P1.12/COM2
AIN7/P2.7
10
27
P1.11/COM1
AVSS
11
26
P1.10/COM0
AVDD
12
25
VDD12/VLCD12
13
14
15
16
17
18
19
20
21
22
23
24
VDD3/VLCD3
SEG31/P0.0
SEG30/P0.1
SEG29/P0.2
SEG28/P0.3
SEG27/P0.4
SEG26/P0.5
SEG17/P1.0
SEG16/P1.1
SEG15/P1.2
SEG14/P1.3
SEG13/P1.4
Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes. Strongly recommended to set these pins as input pull-up.