SONIX SN8P26L00 Series User manual

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 1 PreliminaryVersion0.2
SN8P26L00 Series
USER’S MANUAL
Preliminary Specification Version 0.2
SN8P26L34
SN8P26L32
SN8P26L321
S
SO ON Ni iX X 8 8- -B Bi it t M Mi ic cr ro o- -C Co on nt tr ro ol ll le er r
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 2 PreliminaryVersion0.2
AMENDMENT HISTORY
Version Date Description
VER 0.1 Dec. 2006 First Issue.
VER 0.2 Mar. 2007 1. Add SN8P26L321 pin assignment.
2. Add IR section.

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 PreliminaryVersion0.2
Table of Content
AMENDMENT HISTORY............................................................................................................................ 2
1 PRODUCT OVERVIEW.............................................................................................................................. 7
1.1 FEATURES.............................................................................................................................................. 7
1.2 SYSTEM BLOCK DIAGRAM ................................................................................................................ 8
1.3 PIN ASSIGNMENT ................................................................................................................................. 9
1.4 PIN DESCRIPTIONS............................................................................................................................. 10
1.5 PIN CIRCUIT DIAGRAMS................................................................................................................... 12
2 CENTRAL PROCESSOR UNIT (CPU) ................................................................................................... 14
2.1 MEMORY MAP..................................................................................................................................... 14
2.1.1 PROGRAM MEMORY (ROM) ........................................................................................................ 14
2.1.1.1 RESET VECTOR (0000H) ...................................................................................................... 15
2.1.1.2 INTERRUPT VECTOR (0008H)............................................................................................. 16
2.1.1.3 LOOK-UP TABLE DESCRIPTION........................................................................................ 18
2.1.1.4 JUMP TABLE DESCRIPTION............................................................................................... 20
2.1.1.5 CHECKSUM CALCULATION............................................................................................... 22
2.1.2 CODE OPTION TABLE.................................................................................................................. 23
2.1.3 DATA MEMORY (RAM).................................................................................................................. 24
2.1.4 SYSTEM REGISTER........................................................................................................................ 25
2.1.4.1 SYSTEM REGISTER TABLE ................................................................................................ 25
2.1.4.2 SYSTEM REGISTER DESCRIPTION ................................................................................... 25
2.1.4.3 BIT DEFINITION of SYSTEM REGISTER........................................................................... 26
2.1.4.4 ACCUMULATOR ................................................................................................................... 28
2.1.4.5 PROGRAM FLAG................................................................................................................... 29
2.1.4.6 PROGRAM COUNTER........................................................................................................... 30
2.1.4.7 H, L REGISTERS..................................................................................................................... 33
2.1.4.8 Y, Z REGISTERS..................................................................................................................... 34
2.1.4.9 R REGISTERS......................................................................................................................... 35
2.2 ADDRESSING MODE........................................................................................................................... 36
2.2.1 IMMEDIATE ADDRESSING MODE.............................................................................................. 36
2.2.2 DIRECTLY ADDRESSING MODE ................................................................................................. 36
2.2.3 INDIRECTLY ADDRESSING MODE ............................................................................................. 36
2.3 STACK OPERATION............................................................................................................................ 37
2.3.1 OVERVIEW ..................................................................................................................................... 37
2.3.2 STACK REGISTERS........................................................................................................................ 38
2.3.3 STACK OPERATION EXAMPLE.................................................................................................... 39
3 RESET.......................................................................................................................................................... 40

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 4 PreliminaryVersion0.2
3.1 OVERVIEW........................................................................................................................................... 40
3.2 POWER ON RESET............................................................................................................................... 41
3.3 WATCHDOG RESET............................................................................................................................ 41
3.4 BROWN OUT RESET ........................................................................................................................... 42
3.4.1 BROWN OUT DESCRIPTION........................................................................................................ 42
3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION............................................................... 43
3.4.3 BROWN OUT RESET IMPROVEMENT......................................................................................... 43
3.5 EXTERNAL RESET .............................................................................................................................. 46
3.6 EXTERNAL RESET CIRCUIT ............................................................................................................. 46
3.6.1 Simply RC Reset Circuit.................................................................................................................. 46
3.6.2 Diode & RC Reset Circuit............................................................................................................... 47
3.6.3 Zener Diode Reset Circuit............................................................................................................... 47
3.6.4 Voltage Bias Reset Circuit............................................................................................................... 48
3.6.5 External Reset IC............................................................................................................................. 49
4 SYSTEM CLOCK....................................................................................................................................... 50
4.1 OVERVIEW........................................................................................................................................... 50
4.2 CLOCK BLOCK DIAGRAM................................................................................................................. 50
4.3 OSCM REGISTER................................................................................................................................. 51
4.4 SYSTEM HIGH CLOCK ....................................................................................................................... 52
4.4.1 INTERNAL HIGH RC...................................................................................................................... 52
4.4.2 EXTERNAL HIGH CLOCK............................................................................................................. 52
4.4.2.1 CRYSTAL/CERAMIC............................................................................................................. 53
4.4.2.2 RC............................................................................................................................................. 53
4.4.2.3 EXTERNAL CLOCK SIGNAL............................................................................................... 54
4.5 SYSTEM LOW CLOCK ........................................................................................................................ 55
4.5.1 SYSTEM CLOCK MEASUREMENT............................................................................................... 56
5 SYSTEM OPERATION MODE................................................................................................................ 57
5.1 OVERVIEW........................................................................................................................................... 57
5.2 SYSTEM MODE SWITCHING EXAMPLE......................................................................................... 58
5.3 WAKEUP ............................................................................................................................................... 60
5.3.1 OVERVIEW ..................................................................................................................................... 60
5.3.2 WAKEUP TIME............................................................................................................................... 60
5.3.3 P1W WAKEUP CONTROL REGISTER.......................................................................................... 60
6 INTERRUPT................................................................................................................................................ 61
6.1 OVERVIEW........................................................................................................................................... 61
6.2 INTEN INTERRUPT ENABLE REGISTER......................................................................................... 62
6.3 INTRQ INTERRUPT REQUEST REGISTER....................................................................................... 63
6.4 GIE GLOBALINTERRUPT OPERATION .......................................................................................... 63

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 5 PreliminaryVersion0.2
6.5 PUSH, POP ROUTINE........................................................................................................................... 64
6.6 INT0 (P0.0) INTERRUPT OPERATION............................................................................................... 65
6.7 INT1 (P0.1) INTERRUPT OPERATION............................................................................................... 66
6.8 T0 INTERRUPT OPERATION.............................................................................................................. 67
6.9 TC1 INTERRUPT OPERATION........................................................................................................... 69
6.10 MULTI-INTERRUPT OPERATION................................................................................................... 70
7 I/O PORT ..................................................................................................................................................... 71
7.1 I/O PORT MODE ................................................................................................................................... 71
7.2 I/O PULL UP REGISTER ...................................................................................................................... 72
7.3 I/O OPEN-DRAIN REGISTER.............................................................................................................. 73
7.4 I/O PORT DATA REGISTER ................................................................................................................ 74
8 TIMERS ....................................................................................................................................................... 75
8.1 WATCHDOG TIMER............................................................................................................................ 75
8.2 TIMER 0(T0) ......................................................................................................................................... 77
8.2.1 OVERVIEW ..................................................................................................................................... 77
8.2.2 T0M MODE REGISTER.................................................................................................................. 78
8.2.3 T0C COUNTING REGISTER.......................................................................................................... 79
8.2.4 T0 TIMER OPERATION SEQUENCE............................................................................................ 80
8.3 TIMER/COUNTER 0(TC1)................................................................................................................... 81
8.3.1 OVERVIEW ..................................................................................................................................... 81
8.3.2 TC1M MODE REGISTER............................................................................................................... 82
8.3.3 TC1C COUNTING REGISTER....................................................................................................... 83
8.3.4 TC1R AUTO-LOAD REGISTER ..................................................................................................... 84
8.3.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER)......................................................................... 85
8.3.6 TC1 TIMER OPERATION SEQUENCE ......................................................................................... 86
8.4 PWM1 MODE ........................................................................................................................................ 87
8.4.1 OVERVIEW ..................................................................................................................................... 87
8.4.2 TC1IRQ AND PWM DUTY ............................................................................................................. 88
8.4.3 PWM PROGRAM EXAMPLE ......................................................................................................... 89
8.4.4 PWM1 DUTY CHANGING NOTICE.............................................................................................. 90
9 IR OUTPUT................................................................................................................................................. 92
9.1 OVERVIEW........................................................................................................................................... 92
9.2 IR CONTROL REGISTER..................................................................................................................... 93
9.2.1 TC0M MODE REGISTER............................................................................................................... 93
9.2.2 TC0C COUNTING REGISTER....................................................................................................... 93
9.2.3 TC0R AUTO-LOAD REGISTER ..................................................................................................... 94
9.2.4 TC0D IR DUTY CONTROL REGISTER......................................................................................... 95
9.2.5 IR OUTPUT OPERATION SEQUENCE......................................................................................... 96

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 6 PreliminaryVersion0.2
10 ANALOG COMPARAOTR..................................................................................................................... 97
10.1 OVERVIEW......................................................................................................................................... 97
10.2 CP0M REGISTER................................................................................................................................ 99
10.3 CP1M REGISTER.............................................................................................................................. 100
10.4 ANALOG COMPARATOR APPLICATION.................................................................................... 101
11 INSTRUCTION TABLE ........................................................................................................................ 103
12 ELECTRICAL CHARACTERISTIC................................................................................................... 104
12.1 ABSOLUTE MAXIMUM RATING .................................................................................................. 104
12.2 ELECTRICAL CHARACTERISTIC................................................................................................. 104
13 OTP PROGRAMMING PIN.................................................................................................................. 105
13.1.1 The pin assignment of Easy Writer transition board socket: ...................................................... 105
13.1.2 Programming Pin Mapping: ....................................................................................................... 106
14 MARKING DEFINITION...................................................................................................................... 107
14.1 INTRODUCTION.............................................................................................................................. 107
14.2 MARKING INDETIFICATION SYSTEM........................................................................................ 107
14.3 MARKING EXAMPLE...................................................................................................................... 108
14.4 DATECODE SYSTEM ...................................................................................................................... 108
15 PACKAGE INFORMATION ................................................................................................................ 109
15.1 SK-DIP 28 PIN ................................................................................................................................... 109
15.2 SOP 28 PIN......................................................................................................................................... 110
15.3 SSOP 28 PIN....................................................................................................................................... 111
15.4 P-DIP 18 PIN ...................................................................................................................................... 112
15.5 SOP 18 PIN......................................................................................................................................... 113
15.6 SSOP 20 PIN....................................................................................................................................... 116

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 7 PreliminaryVersion0.2
1 PRODUCT OVERVIEW
1.1 FEATURES
♦Memory configuration ♦Two 8-bit Timer/Counter
OTP ROM size: 8K * 16 bits. T0: Basic timer.
RAM size: 240 * 8 bits. TC1: Auto-reload timer/counter.
♦Eight levels stack buffer ♦One RTC timer (T0).
♦One channels PWM output.
♦I/O pin configuration ♦One channels buzzer output.
Bi-directional: P0, P1, P2, P5 ♦One channel IR output (duty/cycle programmable
Programmable open-drain: P1.0, P1.1 PWM, TC0).
Wakeup:P0, P1 level change trigger. ♦On chip watchdog timer and clock source is internal
P1 wake-up function controlled by P1W. low clock RC type (about 32KHz @5V).
Pull-up resisters: P0, P1, P2, P5
External interrupt input: P0.0 ♦Four system clocks
External Interrupt trigger edge: External high clock: RC type up to 4 MHz
P0.0 controlled by PEDGE register External high clock: Crystal type up to 4 MHz
Internal high clock: RC type 8MHz.
♦2-ch analog comparators with internal selectable Internal low clock: RC type 16KHz(3V), 32KHz(5V).
reference voltage 0.9V/1.0V/1.1V/1.2V and
external reference input. ♦Four operating modes
Normal mode: Both high and low clock active
♦Six interrupt sources Slow mode: Low clock only
Four internal interrupts: T0, TC1, CM0, CM1 Sleep mode: Both high and low clock stop
One external interrupts: INT0 INT1 Green mode: Periodical wakeup by timer
♦Powerful instructions ♦Package (Chip form support)
IT instruction structure. SK-DIP 28 pins
Instruction cycle controlled by code option. SOP 28 pins
Instruction’s length is one word. SSOP 28 pins
Most of instructions are one cycle only. P-DIP 18 pins
Maximum instruction cycle is two. SOP 18 pins
All ROM area JMP instruction. SSOP 20 pins
All ROM area lookup table function (MOVC)
)Features Selection Table
Timer PWM
CHIP ROM
(word) RAM (byte) Stack T0 TC1 RTC IR Out
Int.
High
Osc. I/O Comp
arator Buzzer Wakeup Pin No. Package
SN8P26L32 8K 240 8 V V V V8M 16 1-ch V 8 DIP18/
SOP18
SN8P26L321 8K 240 8 V V V V8M 18 2-ch V 8
DIP20/
SOP20/
SSOP20
SN8P26L34 8K 240 8 V V V V8M 26 2-ch V 13
SKDIP28/
SOP28/
SSOP28
*Note: SN8P26L321 doesn’t includes CM0O pin and comparator 0 output function.

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 8 PreliminaryVersion0.2
1.2 SYSTEM BLOCK DIAGRAM
INTERRUPT
CONTROL
EXTERNAL
HIGH OSC.
ACC
INTERNAL
LOW RC
TIMING GENERATOR
RAM
SYSTEM REGISTERS
LVD
(Low Voltage Detector)
WATCHDOG TIMER
TIMER & COUNTER
P0 P5P1
PWM 1
BUZZER 1
ALU
PC
FLAGS
IR
OTP
ROM
PWM1
BUZZER1
P2
INTERNAL HIGH
RC 8MHz
Comparator 0
Comparator 1
CM0P
CM0N
CM0O
CM1P
CM1N
CM1O
IR OUT IROUT

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 9 PreliminaryVersion0.2
1.3 PIN ASSIGNMENT
SN8P26L34K (SK-DIP 28 pins)
SN8P26L34S (SOP 28 pins)
SN8P26L34X (SSOP 28 pins)
SN8P26L32P (P-DIP 18 pins)
SN8P26L32S (SOP 18 pins)
SN8P26L321P (P-DIP 20 pins)
SN8P26L321S (SOP 20 pins)
SN8P26L321X (SSOP 20 pins)
P0.1/INT1 1 U 28 P2.7/CM1O
VDD 2 27 P2.6/CM1P
P5.4/IROUT 3 26 P2.5/CM1N
VSS 4 25 P2.4/CM0O
P0.0/INT0 5 24 P2.3/CM0P
P5.0 6 23 P2.2/CM0N
P5.1 7 22 XIN/P0.3
P5.2 8 21 XOUT/P0.4
P5.3/BZ1/PWM1 9 20 P2.1
P0.2/RST/VPP 10 19 P2.0
P1.0 11 18 P1.7
P1.1 12 17 P1.6
P1.2 13 16 P1.5
P1.3 14 15 P1.4
SN8P26L34K
SN8P26L34S
SN8P26L34X
P0.1/INT1 1 U 18 P2.7/CM1O
VDD 2 17 P2.6/CM1P
P5.4/IROUT 3 16 P2.5/CM1N
VSS 4 15 XIN/P0.3
P5.0 5 14 XOUT/P0.4
P5.1 6 13 P1.3
P5.2 7 12 P1.2
P5.3/BZ1/PWM1 8 11 P1.1
P0.2/RST/VPP 9 10 P1.0
SN8P26L32P
SN8P26L32S
P2.7/CM1O 1 U 20 P2.6/CM1P
P0.1/INT1 2 19 P2.5/CM1N
VDD 3 18 P2.3/CM0P
P5.4/IROUT 4 17 P2.2/CM0N
VSS 5 16 XIN/P0.3
P5.0 6 15 XOUT/P0.4
P5.1 7 14 P1.3
P5.2 8 13 P1.2
P5.3/BZ1/PWM1 9 12 P1.1
P0.2/RST/VPP 10 11 P1.0
SN8P26L321P
SN8P26L321S
SN8P26L321X

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 10 PreliminaryVersion0.2
1.4 PIN DESCRIPTIONS
PIN NAME TYPE DESCRIPTION
VDD, VSS P Power supply input pins for digital circuit.
P0.0/INT0 I/O
P0.0: Port 0.0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
INT0: External interrupt 0 input pin.
P0.1/INT1 I/O
P0.1: Port 0.1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
INT1: External interrupt 1 input pin.
P0.2/RST/VPP I, P
RST is system external reset input pin under Ext_RST mode.
P0.2 is input only pin without pull-up resistor under P0.2 mode.
Schmitt trigger structure, active “low”, normal stay to “high”.
Built wakeup function.
OTP 12.3V power input pin in programming mode.
P0.3/XIN I/O
XIN: Oscillator input pin while external oscillator enable (crystal and RC).
P0.3: Port 0.3 bi-direction pin under internal 16M RC.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
P0.4/XOUT I/O
XOUT: Oscillator output pin while external crystal enable.
P0.4: Port 0.4 bi-direction pin under internal 16M RC and external RC.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
P1.0 I/O
P1.0: Port 1.0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Open-Drain function controlled by “P1OC” register.
Built wakeup function.
P1.1 I/O
P1.1: Port 1.1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Open-Drain function controlled by “P1OC” register.
Built wakeup function.
P1[7:2] I/O
P1: Port 1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
P2[1:0] I/O
P2: Port 2 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
P2.2/CM0N I/O
P2.2: Port 2.2 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
CM0N: Analog comparator 0 negative input pin.
P2.3/CM0P I/O
P2.3: Port 2.3 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
CM0P: Analog comparator 0 positive input pin.
P2.4/CM0O I/O
P2.4: Port 2.4 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
CM0O: Analog comparator 0 output pin.
When the CM0N input level is less than the level of CM0P, the CM0O output Vdd. When
the CM0N input level is higher than the level of CM0P, the CM0O output Vss.
P2.5/CM1N I/O
P2.5: Port 2.5 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
CM1N: Analog comparator 1 negative input pin.
P2.6/CM1P I/O
P2.6: Port 2.6 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
CM1P: Analog comparator 1 positive input pin.
P2.7/CM1O I/O
P2.7: Port 2.7 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
CM1O: Analog comparator 1 output pin.

SN8P26L00 Series
8-Bit Micro-Controller
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When the CM1N input level is less than the level of CM1P, the CM1O output Vdd. When
the CM1N input level is higher than the level of CM1P, the CM1O output Vss.
P5[2:0] I/O
P5: Port 5 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
P5.3/BZ1/PWM1 I/O
P5.3: Port 5.3 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
BZ1: 1/2 TC1 counter output pin.
PWM1: PWM1 output.
P5.4/IROUT I/O
P5.4: Port 5.4 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
IROUT: IR output pin.

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 12 PreliminaryVersion0.2
1.5 PIN CIRCUIT DIAGRAMS
Port 0, 1, 2, 5 structure:
Pull-Up
Pin
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
Port 1.0, P1.1 structure:
Pull-Up
Pin
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
P1OC
Open-Drain
Port 0.3, 0.4 structure:
Oscillator
Code Option
Int. Osc.
Pull-Up
Pin
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
Port 2 structure:
Comparator
CMnEN
Pull-Up
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
Pin

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 13 PreliminaryVersion0.2
Port 0.2 structure:
Pin
Ext. Reset
Code Option
Int. Bus
Int. Rst

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 14 PreliminaryVersion0.2
2 CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
2.1.1 PROGRAM MEMORY (ROM)
)8K words ROM
ROM
0000H Reset vector User reset vector
Jump to user start address
0001H
.
.
0007H
General purpose area
0008H Interrupt vector User interrupt vector
0009H User program
.
.
000FH
0010H
0011H
.
.
.
.
.
1FFCH
General purpose area
End of user program
1FFDH
1FFEH
1FFFH
Reserved

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 15 PreliminaryVersion0.2
2.1.1.1RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
)Power On Reset (NT0=1, NPD=0).
)Watchdog Reset (NT0=0, NPD=0).
)External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
¾Example: Defining Reset Vector
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
ORG 10H
START: ; 0010H, The head of user program.
… ; User program
…
ENDP ; End of program

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 16 PreliminaryVersion0.2
2.1.1.2INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
¾Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.CODE
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
ORG 8 ; Interrupt vector.
PUSH ; Save ACC and PFLAG register to buffers.
…
…
POP ; Load ACC and PFLAG register from buffers.
RETI ; End of interrupt service routine
…
START: ; The head of user program.
… ; User program
…
JMP START ; End of user program
…
ENDP ; End of program

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 17 PreliminaryVersion0.2
¾Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
ORG 8 ; Interrupt vector.
JMP MY_IRQ ; 0008H, Jump to interrupt service routine address.
ORG 10H
START: ; 0010H, The head of user program.
… ; User program.
…
…
JMP START ; End of user program.
…
MY_IRQ: ;The head of interrupt service routine.
PUSH ; Save ACC and PFLAG register to buffers.
…
…
POP ; Load ACC and PFLAG register from buffers.
RETI ; End of interrupt service routine.
…
ENDP ; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. User’s program is a loop routine for main purpose application.

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 18 PreliminaryVersion0.2
2.1.1.3LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
¾Example: To look up the ROM data located “TABLE1”.
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
INCMS Z ; Z+1
JMP @F ; Z is not overflow.
INCMS Y ; Z overflow (FFH Æ00), ÆY=Y+1
NOP ;
;
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
… ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must take care such situation to avoid look-up table errors. If Z register
overflows, Y register must be added one. The following INC_YZ macro shows a simple method
to process Y and Z registers automatically.
¾Example: INC_YZ macro.
INC_YZ MACRO
INCMS Z ; Z+1
JMP @F ; Not overflow
INCMS Y ; Y+1
NOP ; Not overflow
@@:
ENDM

SN8P26L00 Series
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 19 PreliminaryVersion0.2
¾Example: Modify above example by “INC_YZ” macro.
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
INC_YZ ; Increment the index address for next address.
;
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
… ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
¾Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV Y, #TABLE1$M ; To set lookup table’s middle address.
B0MOV Z, #TABLE1$L ; To set lookup table’s low address.
B0MOV A, BUF ; Z = Z + BUF.
B0ADD Z, A
B0BTS1 FC ; Check the carry flag.
JMP GETDATA ; FC = 0
INCMS Y ; FC = 1. Y+1.
NOP
GETDATA: ;
MOVC ; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
…
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…

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SONiX TECHNOLOGY CO., LTD Page 20 PreliminaryVersion0.2
2.1.1.4JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
¾Example: Jump table.
ORG 0X0100 ; The jump table is from the head of the ROM boundary
B0ADD PCL, A ; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
JMP A0POINT ; ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
¾Example: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A MACRO VAL
IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
JMP ($ | 0XFF)
ORG ($ | 0XFF)
ENDIF
ADD PCL, A
ENDM
Note: “VAL” is the number of the jump table listing number.