Telit Wireless Solutions SE868SY-D Guide

SE868SY-D
HW Design Guide
1VV0301705 Rev.5 –2021-12-15
Telit Technical Documentation

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APPLICABILITY TABLE
PRODUCTS
SE868SY-D

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CONTENTS
APPLICABILITY TABLE 2
CONTENTS 3
1. INTRODUCTION 6
Scope 6
Audience 6
Contact Information, Support 6
Symbol Conventions 7
2. GENERAL PRODUCT DESCRIPTION 8
Overview 8
Product Variants and Supported Satellite Systems 8
Target Market 8
Block Diagram 9
Main Features 9
Mechanical Specifications 10
2.6.1. Dimensions 10
2.6.2. Weight 10
Temperature Range 10
Magnetic Field Immunity 10
3. PINS ALLOCATION 11
Pin-Out 11
LGA Pads Layout 13
Absolute Maximum Ratings 14
4. POWER SUPPLY 15
Power Supply Requirements 15
Power Consumption 15
General Design Rules 16
4.3.1. Electrical Design Guidelines 16
4.3.2. Power Supply PCB Layout Guidelines 17
5. DIGITAL SECTION 19

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Logic Levels 19
Communication Ports 19
5.2.1. Communication Interfaces to the Host MCU (HIF) 19
5.2.2. Host Interface Selection 20
Digital I/O 21
5.3.1. nRESET 21
5.3.2. LNA Enable 21
5.3.3. 1PPS 21
5.3.4. System ON 21
6. PRODUCT PERFORMANCE 22
Horizontal Position Accuracy 22
Time to First Fix 22
Sensitivity 22
7. RF SECTION 24
GNSS RF Signal Pin-Out 24
RF Front End Design 24
7.2.1. Reference Design for Passive Antenna 24
7.2.2. Reference Design for Active Antenna 25
7.2.3. Guidelines of PCB Line for GNSS Antenna 25
GNSS Antenna Requirements 26
7.3.1. GNSS Antenna Specification 26
7.3.2. GNSS Antenna –Installation Guidelines 26
7.3.3. Powering the External LNA (Active Antenna) 27
8. MECHANICAL DESIGN 28
Drawing 28
9. APPLICATION PCB DESIGN 29
Recommended Footprint for the Application 29
PCB Pad Design 30
Stencil 32
Solder Paste 32
Solder Reflow 32

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10. PACKAGING 34
Reel 34
Tray 35
11. CONFORMITY ASSESSMENT ISSUES 37
EU RED Declaration of Conformity 37
UKCA Declaration of Conformity 37
12. PRODUCT AND SAFETY INFORMATION 38
Copyrights and Other Notices 38
12.1.1. Copyrights 38
12.1.2. Computer Software Copyrights 38
Usage and Disclosure Restrictions 39
12.2.1. License Agreements 39
12.2.2. Copyrighted Materials 39
12.2.3. High Risk Materials 39
12.2.4. Trademarks 40
12.2.5. Third Party Rights 40
12.2.6. Waiver of Liability 40
Safety Recommendations 41
13. GLOSSARY 42
14. DOCUMENT HISTORY 43

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1. INTRODUCTION
Scope
This document introduces the SE868SY-D module and presents possible and
recommended hardware solutions for the development of a product based on this
module. All the features and solutions described in this document are applicable to all
the variants listed in the applicability table.
This document cannot include every possible hardware solution or product. Where the
suggested hardware configurations are not required, the information provided should be
used as a guide and starting point for the proper product development with the Telit
module.
Audience
This document is intended for Telit customers, especially system integrators, about to
implement their applications using our SE868SY-D modules.
Contact Information, Support
For general contact, technical support services, technical questions and report
documentation errors contact Telit Technical Support at:
• TS[email protected]
• TS[email protected]
• TS[email protected]
• TS[email protected]
Alternatively, use:
https://www.telit.com/contact-us
For detailed information about where you can buy the Telit modules or for
recommendations on accessories and components visit:
https://www.telit.com
Our aim is to make this guide as helpful as possible. Keep us informed of your comments
and suggestions for improvements.
Telit appreciates the user feedback on our information.

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Symbol Conventions
Danger: This information MUST be followed, or catastrophic
equipment failure or personal injury may occur.
Warning: Alerts the user on important steps about the module
integration.
Note/Tip: Provides advice and suggestions that may be useful when
integrating the module.
Electro-static Discharge: Notifies the user to take proper grounding
precautions before handling the product.
Table 1: Symbol Conventions
All dates are in ISO 8601 format, i.e. YYYY-MM-DD.

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2. GENERAL PRODUCT DESCRIPTION
Overview
The SE868SY-D module, the latest addition to the xE868 family, is a multi-frequency and
multi-constellation GNSS receiver.
The SE868SY-D product uses the two GNSS bands L1 and L5 to achieve sub-meter
accuracy and reduce the multipath effects that are common in urban canyons.
The SE868SY-D operates at 1.8 V, minimizing power consumption even below L1-only
products and making it ideal for battery powered and wearable device applications.
Product Variants and Supported Satellite Systems
The SE868SY-D is available in two different ordering part numbers:
•Standard
•Low-power (requiring an external 0.8 V voltage supply on pin27)
Table 2, below lists the supported satellite systems, for both variants.
Product
Constellations
SE868SY-D
GPS (L1C/A; L5)
GLONASS (L1OF)
Galileo (E1B/C; E5a)
BeiDou (B1I; B1C; B2A)
QZSS (L1C/A, L1S1, L1C/B)
QZSS (L5)
NavIC (L5)
Note 1: Planning
Table 2: Product Variants and Supported Satellite Systems
Target Market
SE868SY-D, with its improved accuracy and ultra-low power consumption, can ideally be
applied to all positioning verticals such as:
•Telemetry
•Fleet managements
•Insurance telematics / Dashcams
•Asset/personal tracking
•Sport equipment

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•E-mobility
•Drones
Block Diagram
Figure 1: SE868SY-D Block Diagram
Main Features
Function
Features
GNSS
Multi-constellation and Multi-bands
Low power consumption
Geofence (in progress)
Real Time Clock
Interfaces
Main UART
SPI 1 / I2C
1PPS signal
LNA_EN
SYS_ON (only in low power P/N)
Single Antenna pin
External Sensors support1
External Flash support 1
Note 1: Planning
Table 3: Functional Features

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Mechanical Specifications
2.6.1. Dimensions
The overall dimensions of SE868SY-D are:
•Length: 11 mm
•Width: 11 mm
•Thickness: 2.8 mm
2.6.2. Weight
The nominal weight of the module is 1gram.
Temperature Range
Mode
Temperature
Notes
Operating Temperature Range
–40°C - +85°C
Storage and non-operating
Temperature Range
–40°C - +85°C
Table 4: Temperature Range
Magnetic Field Immunity
Since the SE868SY-D uses an embedded MRAM as an NVM (Non-Volatile Memory) for its
program code and data storage, the customer should consider the environment magnetic
field strength for good retention performance as shown in Table 5.
Item
Min.
Typ.
Max.
Unit
Notes
10-year data
retention
-
-
100
mT
In Deep Sleep or
Shutdown at 25° C
-
-
90
mT
In Deep Sleep or
Shutdown at 55° C
-
-
55
mT
In Deep Sleep or
Shutdown at 105° C
Active Read/Write
-
-
25
mT
In Exec or Idle
Table 5: Magnetic Field Immunity

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3. PINS ALLOCATION
Pin-Out
Pin
Signal
I/O
Function
Type
Notes
Host Interface (HIF) UART
10
UART_TX
I/O
1st function: UART-TX (HIF)
DIGITAL 1.8V
2nd function: I2C-SDA (HIF)
3rd function: SPI-MOSI (HIF)
11
UART_RX
I/O
1st function: UART-RX (HIF)
DIGITAL 1.8V
2nd function: I2C-SCL (HIF)
3rd function: SPI-SCLK (HIF)
23
UART_CTS
I/O
1st function: UART-CTS (HIF)
DIGITAL 1.8V
2nd function: SPI-CS (HIF)
3rd function: GPIO
24
UART_RTS
I/O
1st function: UART-RTS (HIF)
DIGITAL 1.8V
2nd function: SPI-MISO (HIF)
3rd function: GPIO
DIGITAL IO
5
SYS_ON1
O
System On –active HIGH
DIGITAL 1.8V
12
nRESET
I
Reset –active LOW
DIGITAL 1.8V
PU 10 kΩ
19
HOST_SEL_02
I/O
Host Interface Protocol
Selector
DIGITAL 1.8V
PD 47 kΩ
20
HOST_SEL_12
I/O
Host Interface Protocol
Selector
DIGITAL 1.8V
PD 47 kΩ
26
LNA_EN
I/O
1st function: external LNA
enabler (active HIGH)
DIGITAL 1.8V
2nd function: GPIO
28
PPS
I/O
1st function: PPS
DIGITAL 1.8V
2nd function: DRI (HIF)
3rd function: GPIO
RF Section
8
RF_IN
I
L1-L5 band RF signal input
ANALOG RF

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Pin
Signal
I/O
Function
Type
Notes
Power Supply
25
VDD18
-
Power supply
Power 1.8V
27
VDD18
-
Power supply
Power 1.8V (Standard P/N)
Power 0.8 V (Low-Power P/N)
32
VDD18
-
Power supply
Power 1.8V
1
GND
-
Ground
4
GND
-
Ground
7
GND
-
Ground
9
GND
-
Ground
21
GND
-
Ground
31
GND
-
Ground
RESERVED FOR FUTURE USE (RFU)
2
RFU
-
RFU
3
RFU
-
RFU
5
RFU3
RFU
See SYS_ON
6
RFU
-
RFU
14
RFU
-
RFU
15
RFU
-
RFU
16
RFU
-
RFU
17
RFU
-
RFU
18
RFU
-
RFU
22
RFU
-
RFU
29
RFU
-
RFU
30
RFU
-
RFU
NOT CONNECTED
13
NC
-
NOT CONNECTED
Note 1: PIN 5 is SYS_ON only In Low power P/N. In Standard P/N PIN 5 is RESERVED FOR FUTURE USE (RFU).
Note 2: UART is set as default Host Interface due to internal 47 kΩPull Down resistors on PIN 19 and PIN 20.
Table 6: Pin-out Information

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Warning: Reserved pins must not be connected.
LGA Pads Layout
TOP VIEW
Figure 2: LGA Pads Layout

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Absolute Maximum Ratings
Parameter
Pins
Absolute Maximum Rating
Units
RF Input Voltage
Pin 8
0.9
V
RF Input Power
Pin 8
-20
dBm
ESD Voltage CDM JESD22-
C101F
All Pins
±150
V
ESD Voltage HDM JEDEC JS-
001-2017
All pins
±1500 V
V
ESD Voltage on Antenna PIN
IEC-61000-4-2
Pin 8
8 kV
kV
Supply Voltage (1V8)
Pin 25, Pin 32
Pin 27 (in standard part
numbers)
2.5
V
Supply Voltage (0V8)
Pin 27 (in Low power part
numbers)
1.1
V
I/O Pins
Digital inputs
-0.3/+2.2
V
Table 7: Absolute Maximum Ratings

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4. POWER SUPPLY
The power supply circuitry and board layout are critical components of the overall
product design, and they strongly reflect the product's overall performance. For a proper
design, please read the requirements and guidelines carefully.
Power Supply Requirements
The external power supply must be connected to VDD18 pins, and it must fulfill the
following requirements:
Power Supply
Value
Notes
Nominal Supply Voltage
1.8 V
On Pin 25, 27 and 32 in Standard P/N
On Pin 25 and 32 in Low Power P/N
0.8 V
On Pin 27, ONLY in Low Power P/N
Operating Voltage Range
1.71 ÷ 1.89 V
On Pin 25, 27 and 32 in Standard P/N
On Pin 25 and 32 in Low Power P/N
0.75 ÷ 0.85 V
On Pin 27, ONLY in Low Power P/N
Table 8: Power Supply Requirements
Note: The Operating Voltage Range MUST never be exceeded at any
time. This also applies to overshoots above the maximum allowed
voltage and drops below the minimum.
Power Consumption
Standard
P/N
GPS
L1
only
GPS
L1+L5
GPS, GLO, GAL, QZSS, L1+L5
Acquisition
(avg)
53
mW
61
mW
60 mW
Acquisition
(max)
57
mW
65
mW
71 mW
Tracking
(avg)
25
mW
36
mW
47 mW
Idle (avg)
10 mW
Deep
Sleep
70 µW
Table 9: Power Consumption in Standard P/N

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Low Power P/N
GPS L1 only
GPS L1+L5
GPS, GLO, GAL, QZSS,
L1+L5
Acquisition (avg)
38 mW
43 mW
40 mW
Acquisition (max)
41 mW
45 mW
49 mW
Tracking (avg)
20 mW
28 mW
34 mW
Idle (avg)
8 mW
Deep Sleep
50 µW
Table 10: Power Consumption in Low Power P/N
Note: It is recommended to reach the Sleep state only from Idle. Setting the
device in Sleep mode directly from Exec state may result in higher-than-
normal power consumption.
General Design Rules
The principal guidelines for the Power Supply Design embrace three different design
steps:
•Electrical design
•Thermal design
•PCB layout
4.3.1. Electrical Design Guidelines
The electrical design of the power supply strongly depends on the chosen power source.
The following diagram depicts an example of a suitable linear voltage regulator:
Figure 3: Example of a suitable Linear Voltage Regulator
To further reduce the power consumption, DC-DC converters can be used instead of LDO.
Figure 4 and Figure 5 show a reference design for generating the 1.8 V voltage and the
0.8V (to be provided on PIN 27 only in case of low power P/N). As depicted in Figure 5, in

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low power P/N, the DC-DC enable PIN (CE) must be connected to the SYS_ON signal,
exported on pin 5 of SE868SY-D, to ensure the module enters a deep sleep state.
Figure 4: Example of a Suitable 1.8 V DC-DC Converter
Figure 5: Example of a Suitable 0.8 V DC-DC Converter
Aluminum electrolytic capacitors are not recommended at the module input due to their
high ESR. When Tantalum capacitors are chosen, a minimum value of 10µF is
recommended, in parallel with a 0.1µF ceramic capacitor. Ceramic capacitors can be
used alone for both input and output, but ensure that the LDO is stable with such
capacitors tied to the output.
4.3.2. Power Supply PCB Layout Guidelines
As seen on the electrical design guidelines, the power supply must have a low ESR
capacitor on the output to cut current peaks on the input and protect the module supply
from spikes.

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The placement of this component is crucial for the correct working of the circuitry. A
misplaced component can be ineffective or even degrade the performance of the power
supply.
•The low ESR bypass capacitor must be placed close to the Telit SE868SY-D power
input pads; in case the power supply is a switching type, it can be placed close to
the switching inductor to reduce ripple.
•In case a switching power regulator is used, it is important to keep the involved
current loop formed by the input capacitor, the output diode (if not embodied in the
IC) and the regulator as small as possible to reduce the radiated EMI at the
switching frequency (100-500 kHz usually).
•A dedicated ground for the Switching regulator, separated from the common
ground plane, is recommended.

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5. DIGITAL SECTION
Logic Levels
Table 11: Logic Levels Minimum and Maximum
Table 12: I/O Driving Capability
Communication Ports
5.2.1. Communication Interfaces to the Host MCU (HIF)
The SE868SY-D features three different Host Interfaces (HIF) for communicating with the
host MCU, which can be selected using the Host Interface Selection pin (See section 5.2.2
Host Interface Selection):
•HIF_UART: serial interface, supporting speeds up to 10Mbps.
Function
Pin on SE868SY-D
HIF_UART_TX
10
HIF_UART_RX
11
HIF_UART_CTS
23
HIF_UART_RTScon
24
Parameter
Min
Max
Absolute Maximum Ratings –Not Functional
Input level on any digital pin (CMOS
1.8) with respect to ground
-0.3V
2.2 V
Operating Range - Interface levels (1.8V CMOS)
Input high level
0.7*VDD
VDD
Input low level
0 V
0.3*VDD
Output high level
VDD-0.45 V
VDD
Output low level
0 V
0.45 V
Parameter
AVG
Current characteristics for digital pins
Output Current
3 mA
Input Current
3 mA

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Table 13: UART Pins
•HIF_SPI: slave SPI interface, speed up to 10Mbps.
Function
Pin on SE868SY-D
HIF_SPI_SCLK
11
HIF_SPI_CS
23
HIF_SPI_MISO
24
HIF_SPI_MOSI
10
Table 14: SPI Pins
•HIF_I2C: slave I2C interface, speed up to 400kbps in Fast mode and up to 3.4 Mbps
in High-Speed Mode.
Function
Pin on SE868SY-D
HIF_I2C_SCL
11
HIF_I2C_SDA
10
Table 15: I2C Pins
5.2.2. Host Interface Selection
The different Host Interface (HIF) options described in the previous section can be
selected in the SE868SY-D via two pins, HIF_SEL_0 and HIF_SEL_1, whose values are
checked when the power is turned ON. HIF_SEL_0 and HIF_SEL_1 are internally pulled
down with a 47 kΩresistor: this implies that the HIF is set to UART by default. SPI and
I2C can be selected by externally pulling up HIF_SEL_1 or HIF_SEL_0 to VDD, as shown
in Table 16. The recommended Pull Up values to select SPI or I2C is 4.7 kΩ.
HIF_SEL_1
HIF_SEL_0
Selected host interface
NC
NC
HIF_UART
NC
PULL UP
HIF_I2C
PULL UP
NC
HIF_SPI
Table 16: Settings for Host Interface Selection
Note: The configuration with both HIF_SEL_x pins pulled up is
reserved, and shall not be used.