Texas Instruments TMS320 Series User manual

Preliminary
TMS320F2803x
Piccolo Local Interconnect Network (LIN)Module
User's Guide
Literature Number: SPRUGE2AMay 2009 – Revised June 2009

Preliminary
2 SPRUGE2A – May 2009 – Revised June 2009Submit Documentation Feedback

Contents
Preface ........................................................................................................................................ 71 Introduction and Features ..................................................................................................... 91.1 Purpose .................................................................................................................... 91.2 Features .................................................................................................................... 91.3 Block Diagram ........................................................................................................... 101.4 Standards ................................................................................................................. 112 Operation .......................................................................................................................... 122.1 Message Frame.......................................................................................................... 122.2 Synchronizer ............................................................................................................. 132.3 Baud Rate ................................................................................................................ 142.4 Header Generation ...................................................................................................... 142.5 Extended Frames Handling ............................................................................................ 182.6 Timeout Control .......................................................................................................... 192.7 TXRX Error Detector (TED) ............................................................................................ 202.8 Message Filtering and Validation ...................................................................................... 232.9 Receive Buffers .......................................................................................................... 242.10 Transmit Buffers ......................................................................................................... 253 Interrupts .......................................................................................................................... 264 Low-Power Mode ................................................................................................................ 284.1 Entering Sleep Mode .................................................................................................... 294.2 Wakeup ................................................................................................................... 294.3 Wakeup Timeouts ....................................................................................................... 305 Emulation Mode ................................................................................................................. 306 SCI/BLIN Control Registers ................................................................................................. 316.1 SCI Global Control Register 0 (SCIGCR0) ........................................................................... 396.2 SCI Global Control Register (SCIGCR1) ............................................................................. 396.3 SCI Global Control Register (SCIGCR2) ............................................................................. 446.4 SCI Set Interrupt Register (SCISETINT) ............................................................................. 456.5 SCI Clear Interrupt Register (SCICLEARINT) ....................................................................... 496.6 SCI Set Interrupt Level Register (SCISETINTLVL) ................................................................. 536.7 SCI Clear Interrupt Level Register (SCICLEARINTLVL) ........................................................... 576.8 SCI Flags Register (SCIFLR) .......................................................................................... 606.9 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ....................................................................... 676.10 SCI Interrupt Vector Offset 1 (SCIINTVECT1) ....................................................................... 676.11 SCI Format Control Register (SCIFORMAT) ........................................................................ 686.12 Baud Rate Selection Register (BRSR) ............................................................................... 696.13 SCI Data Buffers (SCIED, SCIRD, SCITD) .......................................................................... 706.14 SCI Pin I/O Control Register 2 (SCIPIO2) ............................................................................ 726.15 LIN Compare Register (LINCOMPARE) .............................................................................. 736.16 LIN Receive Buffer 0 Register (LINRD0) ............................................................................. 746.17 LIN Receive Buffer 1 Register (LINRD1) ............................................................................. 75
SPRUGE2A – May 2009 – Revised June 2009 Table of Contents 3Submit Documentation Feedback

Preliminary
www.ti.com
6.18 LIN Mask Register (LINMASK) ........................................................................................ 756.19 LIN Identification Register (LINID) ..................................................................................... 766.20 LIN Transmit Buffer 0 Register (LINTD0) ............................................................................ 766.21 LIN Transmit Buffer 1 Register (LINTD1) ............................................................................ 776.22 Maximum Baud Rate Selection Register (MBRS) ................................................................... 786.23 I/O Design For Test Control (IODFTCTRL) Register ............................................................... 787 BLIN SCI vs. Standard SCI ................................................................................................... 81Appendix A Revision History ...................................................................................................... 84
4Contents SPRUGE2A – May 2009 – Revised June 2009Submit Documentation Feedback

Preliminary
www.ti.com
List of Figures
1 SCI/BLIN Block Diagram .................................................................................................. 112 LIN Protocol Message Frame Format: Master Header and Slave Response ...................................... 123 Header Fields: Synch Break, Synch, and ID ........................................................................... 124 Response Format of LIN Message Frame .............................................................................. 135 Message Header in Terms of T
bit
........................................................................................ 156 ID Field ...................................................................................................................... 157 Measurements for Synchronization ...................................................................................... 168 Synchronization Validation Process and Baud Rate Adjustment .................................................... 179 Optional Embedded Checksum in Response for Extended Frames ................................................ 1810 Checksum Compare and Send for Extended Frames ................................................................. 1911 TXRX Error Detector ....................................................................................................... 2112 Classic Checkbyte Generation at Transmitting Node ................................................................. 2213 LIN 2.0-Compliant Checkbyte Generation at Transmitting Node .................................................... 2214 ID Reception, Filtering and Validation ................................................................................... 2315 Receive Buffers ............................................................................................................. 2516 Transmit Buffers ............................................................................................................ 2617 General Interrupt Scheme ................................................................................................. 2718 Interrupt Generation for Given Flags .................................................................................... 2819 LIN Message Frame Showing LIN Interrupt Timing and Sequence” ................................................ 2820 Wakeup Signal Generation ............................................................................................... 3021 SCI Global Control Register 0 (SCIGCR0) ............................................................................. 3922 SCI Global Control Register (SCIGCR1) ................................................................................ 3923 SCI Global Control Register (SCIGCR2) ................................................................................ 4424 SCI Set Interrupt Register (SCISETINT) ................................................................................ 4625 SCI Clear Interrupt Register (SCICLEARINT) .......................................................................... 5026 SCI Set Interrupt Level Register (SCISETINTLVL) .................................................................... 5427 SCI Clear Interrupt Level Register (SCICLEARINTLVL) .............................................................. 5728 SCI Flags Register (SCIFLR) ............................................................................................. 6129 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ......................................................................... 6730 SCI Interrupt Vector Offset 1 (SCIINTVECT1) ......................................................................... 6831 SCI Format Control Register (SCIFORMAT) ........................................................................... 6832 Baud Rate Selection Register (BRSR) .................................................................................. 6933 Receiver Emulation Data Buffer (SCIED) ............................................................................... 7034 Receiver Data Buffer (SCIRD) ............................................................................................ 7135 Transmit Data Buffer Register (SCITD) ................................................................................. 7236 SCI Pin I/O Control Register 2 (SCIPIO2) .............................................................................. 7237 LIN Compare Register (LINCOMPARE) ................................................................................ 7338 LIN Receive Buffer 0 Register (LINRD0) ................................................................................ 7439 LIN Receive Buffer 1 Register (LINRD1) ................................................................................ 7540 LIN Mask Register (LINMASK) ........................................................................................... 7541 LIN Identification Register (LINID) ....................................................................................... 7642 LIN Transmit Buffer 0 Register (LINTD0) ............................................................................... 7743 LIN Transmit Buffer 1 Register (LINTD1) ............................................................................... 7744 Maximum Baud Rate Selection Register (MBRS) ..................................................................... 7845 I/O Design For Test Control (IODFTCTRL) Register .................................................................. 79
SPRUGE2A – May 2009 – Revised June 2009 List of Figures 5Submit Documentation Feedback

Preliminary
www.ti.com
List of Tables
1 Response Length with SCIFORMAT(18–16) Programming .......................................................... 132 Timeout Values in T
bit
Units ............................................................................................... 193 SCI/BLIN Interrupts ........................................................................................................ 274 LIN Registers ............................................................................................................... 315 SCI Global Control Register 0 (SCIGCR0) Field Descriptions ....................................................... 396 SCI Global Control Register (SCIGCR1) Field Descriptions ......................................................... 407 SCI Receiver Status Flags ................................................................................................ 448 SCI Transmitter Status Flags ............................................................................................. 449 SCI Global Control Register (SCIGCR2) Field Descriptions ......................................................... 4410 SCI Set Interrupt Register (SCISETINT) Field Descriptions .......................................................... 4611 SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions .................................................... 5012 SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions .............................................. 5413 SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions ....................................... 5714 SCI Flags Register (SCIFLR) Field Descriptions....................................................................... 6115 SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions ................................................... 6716 SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions ................................................... 6817 SCI Format Control Register (SCIFORMAT) Field Descriptions ..................................................... 6818 Baud Rate Selection Register (BRSR) Field Descriptions ............................................................ 7019 P and M values for standard bit-rates ................................................................................... 7020 Receiver Emulation Data Buffer (SCIED) Field Descriptions ......................................................... 7121 Receiver Data Buffer (SCIRD) Field Descriptions ..................................................................... 7122 Transmit Data Buffer Register (SCITD) Field Descriptions ........................................................... 7223 SCI Pin I/O Control Register 2 (SCIPIO2) Field Descriptions ........................................................ 7224 LIN Compare Register (LINCOMPARE) Field Descriptions .......................................................... 7325 LIN Receive Buffer 0 Register (LINRD0) Field Descriptions ......................................................... 7426 LIN Receive Buffer 1 Register (LINRD1) Field Descriptions ......................................................... 7527 LIN Mask Register (LINMASK) Field Descriptions ..................................................................... 7528 LIN Identification Register (LINID) Field Descriptions ................................................................. 7629 LIN Transmit Buffer 0 Register (LINTD0) Field Descriptions ......................................................... 7730 LIN Transmit Buffer 1 Register (LINTD1) Field Descriptions ......................................................... 7731 Maximum Baud Rate Selection Register (MBRS) Field Descriptions ............................................... 7832 I/O Design For Test Control (IODFTCTRL) Register Field Descriptions ............................................ 7933 SCI vs. LIN-SCI Programming ............................................................................................ 81A-1 Revision A Changes ....................................................................................................... 84
6List of Tables SPRUGE2A – May 2009 – Revised June 2009Submit Documentation Feedback

Preliminary
PrefaceSPRUGE2A – May 2009 – Revised June 2009
Read This First
This document describes the Local Interconnect Network (LIN) Module.
About This Manual
The TMS320C2000™ is part of the TMS320™ family.
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h or with a leading 0x. For example, the followingnumber is 40 hexadecimal (decimal 64): 40h or 0x40.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation
The following books describe the TMS320x28x and related support tools that are available on the TIwebsite:
SPRS584 — TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 PiccoloMicrocontrollers Data Manual contains the pinout, signal descriptions, as well as electrical andtiming specifications for the 2803x devices.
SPRZ295 — TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 Piccolo MCU SiliconErrata describes known advisories on silicon and provides workarounds.
CPU User's Guides—SPRU430 — TMS320C28x CPU and Instruction Set Reference Guide describes the central processingunit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signalprocessors (DSPs). It also describes emulation features available on these DSPs.
Peripheral Guides—
SPRUGL8 — TMS320x2803x Piccolo System Control and Interrupts Reference Guide describes thevarious interrupts and system control features of the 2803x microcontrollers (MCUs).
SPRU566 — TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral referenceguides of the 28x digital signal processors (DSPs).
SPRUGO0 — TMS320x2803x Piccolo Boot ROM Reference Guide describes the purpose and featuresof the boot loader (factory-programmed boot-loading software) and provides examples of code. Italso describes other contents of the device on-chip boot ROM and identifies where all of theinformation is located within that memory.
SPRUGE6 — TMS320x2803x Piccolo Control Law Accelerator (CLA) Reference Guide describes theoperation of the Control Law Accelerator (CLA).
SPRUGE2A – May 2009 – Revised June 2009 Preface 7Submit Documentation Feedback

Preliminary
Related Documentation www.ti.com
SPRUGE2 — TMS320x2803x Piccolo Local Interconnect Network (LIN) Module Reference Guidedescribes the operation of the Local Interconnect Network (LIN) Module.
SPRUFK8 — TMS320x2803x Piccolo Enhanced Quadrature Encoder Pulse (eQEP) Reference Guidedescribes the operation of the Enhanced Quadrature Encoder Pulse (eQEP) .
SPRUGL7 — TMS320x2803x Piccolo Enhanced Controller Area Network (eCAN) Reference Guidedescribes the operation of the Enhanced Controller Area Network (eCAN).
SPRUGE5 — TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and ComparatorReference Guide describes how to configure and use the on-chip ADC module, which is a 12-bitpipelined ADC.
SPRUGE9 — TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) ModuleReference Guide describes the main areas of the enhanced pulse width modulator that includedigital motor control, switch mode power supply control, UPS (uninterruptible power supplies), andother forms of power conversion.
SPRUGE8 — TMS320x2802x, 2803x Piccolo High-Resolution Pulse Width Modulator (HRPWM)describes the operation of the high-resolution extension to the pulse width modulator (HRPWM).
SPRUGH1 — TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) Reference Guidedescribes how to use the SCI.
SPRUFZ8 — TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module Reference Guidedescribes the enhanced capture module. It includes the module description and registers.
SPRUG71 — TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) Reference Guidedescribes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bitstream of programmed length (one to sixteen bits) to be shifted into and out of the device at aprogrammed bit-transfer rate.
SPRUFZ9 — TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) Reference Guide describesthe features and operation of the inter-integrated circuit (I2C) module.
Tools Guides—
SPRU513 — TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assemblylanguage tools (assembler and other tools used to develop assembly language code), assemblerdirectives, macros, common object file format, and symbolic debugging directives for theTMS320C28x device.
SPRU514 — TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes theTMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code andproduces TMS320 DSP assembly language source code for the TMS320C28x device.
SPRU608 — TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instructionset of the C28x™ core.
8Read This First SPRUGE2A – May 2009 – Revised June 2009Submit Documentation Feedback

1 Introduction and Features
1.1 Purpose
1.2 Features
Preliminary
User's GuideSPRUGE2A – May 2009 – Revised June 2009
Local Interconnect Network (LIN) Module
This document describes the buffered local interconnect network (BLIN) module. Since this module canalso operate like a conventional serial communications interface (SCI) port, it is referred to as theSCI/BLIN module in this document. In the SCI (UART) mode, it is functionally compatible to thestandalone SCI module in the TMS320x2803x device. However, since the SCI/BLIN module uses adifferent register/bit structure, code written for this module cannot be directly ported to the standalone SCImodule and vice versa.
The SCI/BLIN is compliant to the LIN 2.0 protocol specified in the LIN Specification Package. This moduleuses the SCI as its core and augments the SCI’s hardware features for LIN compatibility. This module canbe configured to operate in either LIN mode or the SCI (UART) mode. The SCI mode is also referred to ascompatibility mode in this document.
The SCI/BLIN provides a communications structure at the hardware and software level. It provides alow-cost solution where the bandwidth and fault tolerance of a controller area network (CAN) are notrequired.
The following are the features of the SCI/BLIN module:•Compatibility with LIN 1.3 or 2.0 protocols (LIN Specification Package 2002)•Two external pins: LINRX and LINTX•Functionally compatible with the standalone SCI of C2000 devices•Multi-buffered receive and transmit units•Identification masks for message filtering•Automatic master header generation– Programmable synchronization break field– Synchronization field– Identifier field•Slave automatic synchronization– Synchronization break detection– Optional baud rate update– Synchronization validation•2
28
programmable transmission rates•Wakeup on LINRX dominant level from transceiver•Automatic wakeup support– Wakeup signal generation– Expiration times on wakeup signals•Automatic bus idle detection•Error detection
SPRUGE2A – May 2009 – Revised June 2009 Local Interconnect Network (LIN) Module 9Submit Documentation Feedback

1.3 Block Diagram
Preliminary
Introduction and Features www.ti.com
– Bit error– Bus error– No-response error– Checksum error– Synchronization field error– Parity error•2 Interrupt lines with priority encoding for:– Receive
– Transmit
– ID, error, and status•Support for LIN 2.0 checksum•Enhanced synchronizer finite state machine (FSM) support for frame processing•Enhanced handling of extended frames•Enhanced baud rate generator
The SCI/BLIN module is based on the SCI with the addition of an error detector (parity calculator,checksum calculator, and bit monitor), a mask filter, a synchronizer, and a multibuffered receiver andtransmitter. The SCI interface and the baud generator are modified as part of the hardware enhancementsfor LIN compatibility. Figure 1 shows the SCI/BLIN block diagram.
10 Local Interconnect Network (LIN) Module SPRUGE2A – May 2009 – Revised June 2009Submit Documentation Feedback