Texas Instruments TMS320 Series User manual

Preliminary
TMS320F2803x
Piccolo Local Interconnect Network (LIN)Module
User's Guide
Literature Number: SPRUGE2AMay 2009 – Revised June 2009

Preliminary
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Contents
Preface ........................................................................................................................................ 71 Introduction and Features ..................................................................................................... 91.1 Purpose .................................................................................................................... 91.2 Features .................................................................................................................... 91.3 Block Diagram ........................................................................................................... 101.4 Standards ................................................................................................................. 112 Operation .......................................................................................................................... 122.1 Message Frame.......................................................................................................... 122.2 Synchronizer ............................................................................................................. 132.3 Baud Rate ................................................................................................................ 142.4 Header Generation ...................................................................................................... 142.5 Extended Frames Handling ............................................................................................ 182.6 Timeout Control .......................................................................................................... 192.7 TXRX Error Detector (TED) ............................................................................................ 202.8 Message Filtering and Validation ...................................................................................... 232.9 Receive Buffers .......................................................................................................... 242.10 Transmit Buffers ......................................................................................................... 253 Interrupts .......................................................................................................................... 264 Low-Power Mode ................................................................................................................ 284.1 Entering Sleep Mode .................................................................................................... 294.2 Wakeup ................................................................................................................... 294.3 Wakeup Timeouts ....................................................................................................... 305 Emulation Mode ................................................................................................................. 306 SCI/BLIN Control Registers ................................................................................................. 316.1 SCI Global Control Register 0 (SCIGCR0) ........................................................................... 396.2 SCI Global Control Register (SCIGCR1) ............................................................................. 396.3 SCI Global Control Register (SCIGCR2) ............................................................................. 446.4 SCI Set Interrupt Register (SCISETINT) ............................................................................. 456.5 SCI Clear Interrupt Register (SCICLEARINT) ....................................................................... 496.6 SCI Set Interrupt Level Register (SCISETINTLVL) ................................................................. 536.7 SCI Clear Interrupt Level Register (SCICLEARINTLVL) ........................................................... 576.8 SCI Flags Register (SCIFLR) .......................................................................................... 606.9 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ....................................................................... 676.10 SCI Interrupt Vector Offset 1 (SCIINTVECT1) ....................................................................... 676.11 SCI Format Control Register (SCIFORMAT) ........................................................................ 686.12 Baud Rate Selection Register (BRSR) ............................................................................... 696.13 SCI Data Buffers (SCIED, SCIRD, SCITD) .......................................................................... 706.14 SCI Pin I/O Control Register 2 (SCIPIO2) ............................................................................ 726.15 LIN Compare Register (LINCOMPARE) .............................................................................. 736.16 LIN Receive Buffer 0 Register (LINRD0) ............................................................................. 746.17 LIN Receive Buffer 1 Register (LINRD1) ............................................................................. 75
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6.18 LIN Mask Register (LINMASK) ........................................................................................ 756.19 LIN Identification Register (LINID) ..................................................................................... 766.20 LIN Transmit Buffer 0 Register (LINTD0) ............................................................................ 766.21 LIN Transmit Buffer 1 Register (LINTD1) ............................................................................ 776.22 Maximum Baud Rate Selection Register (MBRS) ................................................................... 786.23 I/O Design For Test Control (IODFTCTRL) Register ............................................................... 787 BLIN SCI vs. Standard SCI ................................................................................................... 81Appendix A Revision History ...................................................................................................... 84
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List of Figures
1 SCI/BLIN Block Diagram .................................................................................................. 112 LIN Protocol Message Frame Format: Master Header and Slave Response ...................................... 123 Header Fields: Synch Break, Synch, and ID ........................................................................... 124 Response Format of LIN Message Frame .............................................................................. 135 Message Header in Terms of T
bit
........................................................................................ 156 ID Field ...................................................................................................................... 157 Measurements for Synchronization ...................................................................................... 168 Synchronization Validation Process and Baud Rate Adjustment .................................................... 179 Optional Embedded Checksum in Response for Extended Frames ................................................ 1810 Checksum Compare and Send for Extended Frames ................................................................. 1911 TXRX Error Detector ....................................................................................................... 2112 Classic Checkbyte Generation at Transmitting Node ................................................................. 2213 LIN 2.0-Compliant Checkbyte Generation at Transmitting Node .................................................... 2214 ID Reception, Filtering and Validation ................................................................................... 2315 Receive Buffers ............................................................................................................. 2516 Transmit Buffers ............................................................................................................ 2617 General Interrupt Scheme ................................................................................................. 2718 Interrupt Generation for Given Flags .................................................................................... 2819 LIN Message Frame Showing LIN Interrupt Timing and Sequence” ................................................ 2820 Wakeup Signal Generation ............................................................................................... 3021 SCI Global Control Register 0 (SCIGCR0) ............................................................................. 3922 SCI Global Control Register (SCIGCR1) ................................................................................ 3923 SCI Global Control Register (SCIGCR2) ................................................................................ 4424 SCI Set Interrupt Register (SCISETINT) ................................................................................ 4625 SCI Clear Interrupt Register (SCICLEARINT) .......................................................................... 5026 SCI Set Interrupt Level Register (SCISETINTLVL) .................................................................... 5427 SCI Clear Interrupt Level Register (SCICLEARINTLVL) .............................................................. 5728 SCI Flags Register (SCIFLR) ............................................................................................. 6129 SCI Interrupt Vector Offset 0 (SCIINTVECT0) ......................................................................... 6730 SCI Interrupt Vector Offset 1 (SCIINTVECT1) ......................................................................... 6831 SCI Format Control Register (SCIFORMAT) ........................................................................... 6832 Baud Rate Selection Register (BRSR) .................................................................................. 6933 Receiver Emulation Data Buffer (SCIED) ............................................................................... 7034 Receiver Data Buffer (SCIRD) ............................................................................................ 7135 Transmit Data Buffer Register (SCITD) ................................................................................. 7236 SCI Pin I/O Control Register 2 (SCIPIO2) .............................................................................. 7237 LIN Compare Register (LINCOMPARE) ................................................................................ 7338 LIN Receive Buffer 0 Register (LINRD0) ................................................................................ 7439 LIN Receive Buffer 1 Register (LINRD1) ................................................................................ 7540 LIN Mask Register (LINMASK) ........................................................................................... 7541 LIN Identification Register (LINID) ....................................................................................... 7642 LIN Transmit Buffer 0 Register (LINTD0) ............................................................................... 7743 LIN Transmit Buffer 1 Register (LINTD1) ............................................................................... 7744 Maximum Baud Rate Selection Register (MBRS) ..................................................................... 7845 I/O Design For Test Control (IODFTCTRL) Register .................................................................. 79
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List of Tables
1 Response Length with SCIFORMAT(18–16) Programming .......................................................... 132 Timeout Values in T
bit
Units ............................................................................................... 193 SCI/BLIN Interrupts ........................................................................................................ 274 LIN Registers ............................................................................................................... 315 SCI Global Control Register 0 (SCIGCR0) Field Descriptions ....................................................... 396 SCI Global Control Register (SCIGCR1) Field Descriptions ......................................................... 407 SCI Receiver Status Flags ................................................................................................ 448 SCI Transmitter Status Flags ............................................................................................. 449 SCI Global Control Register (SCIGCR2) Field Descriptions ......................................................... 4410 SCI Set Interrupt Register (SCISETINT) Field Descriptions .......................................................... 4611 SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions .................................................... 5012 SCI Set Interrupt Level Register (SCISETINTLVL) Field Descriptions .............................................. 5413 SCI Clear Interrupt Level Register (SCICLEARINTLVL) Field Descriptions ....................................... 5714 SCI Flags Register (SCIFLR) Field Descriptions....................................................................... 6115 SCI Interrupt Vector Offset 0 (SCIINTVECT0) Field Descriptions ................................................... 6716 SCI Interrupt Vector Offset 1 (SCIINTVECT1) Field Descriptions ................................................... 6817 SCI Format Control Register (SCIFORMAT) Field Descriptions ..................................................... 6818 Baud Rate Selection Register (BRSR) Field Descriptions ............................................................ 7019 P and M values for standard bit-rates ................................................................................... 7020 Receiver Emulation Data Buffer (SCIED) Field Descriptions ......................................................... 7121 Receiver Data Buffer (SCIRD) Field Descriptions ..................................................................... 7122 Transmit Data Buffer Register (SCITD) Field Descriptions ........................................................... 7223 SCI Pin I/O Control Register 2 (SCIPIO2) Field Descriptions ........................................................ 7224 LIN Compare Register (LINCOMPARE) Field Descriptions .......................................................... 7325 LIN Receive Buffer 0 Register (LINRD0) Field Descriptions ......................................................... 7426 LIN Receive Buffer 1 Register (LINRD1) Field Descriptions ......................................................... 7527 LIN Mask Register (LINMASK) Field Descriptions ..................................................................... 7528 LIN Identification Register (LINID) Field Descriptions ................................................................. 7629 LIN Transmit Buffer 0 Register (LINTD0) Field Descriptions ......................................................... 7730 LIN Transmit Buffer 1 Register (LINTD1) Field Descriptions ......................................................... 7731 Maximum Baud Rate Selection Register (MBRS) Field Descriptions ............................................... 7832 I/O Design For Test Control (IODFTCTRL) Register Field Descriptions ............................................ 7933 SCI vs. LIN-SCI Programming ............................................................................................ 81A-1 Revision A Changes ....................................................................................................... 84
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Preliminary
PrefaceSPRUGE2A – May 2009 – Revised June 2009
Read This First
This document describes the Local Interconnect Network (LIN) Module.
About This Manual
The TMS320C2000™ is part of the TMS320™ family.
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h or with a leading 0x. For example, the followingnumber is 40 hexadecimal (decimal 64): 40h or 0x40.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation
The following books describe the TMS320x28x and related support tools that are available on the TIwebsite:
SPRS584 — TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 PiccoloMicrocontrollers Data Manual contains the pinout, signal descriptions, as well as electrical andtiming specifications for the 2803x devices.
SPRZ295 — TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 Piccolo MCU SiliconErrata describes known advisories on silicon and provides workarounds.
CPU User's Guides—SPRU430 — TMS320C28x CPU and Instruction Set Reference Guide describes the central processingunit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signalprocessors (DSPs). It also describes emulation features available on these DSPs.
Peripheral Guides—
SPRUGL8 — TMS320x2803x Piccolo System Control and Interrupts Reference Guide describes thevarious interrupts and system control features of the 2803x microcontrollers (MCUs).
SPRU566 — TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral referenceguides of the 28x digital signal processors (DSPs).
SPRUGO0 — TMS320x2803x Piccolo Boot ROM Reference Guide describes the purpose and featuresof the boot loader (factory-programmed boot-loading software) and provides examples of code. Italso describes other contents of the device on-chip boot ROM and identifies where all of theinformation is located within that memory.
SPRUGE6 — TMS320x2803x Piccolo Control Law Accelerator (CLA) Reference Guide describes theoperation of the Control Law Accelerator (CLA).
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Preliminary
Related Documentation www.ti.com
SPRUGE2 — TMS320x2803x Piccolo Local Interconnect Network (LIN) Module Reference Guidedescribes the operation of the Local Interconnect Network (LIN) Module.
SPRUFK8 — TMS320x2803x Piccolo Enhanced Quadrature Encoder Pulse (eQEP) Reference Guidedescribes the operation of the Enhanced Quadrature Encoder Pulse (eQEP) .
SPRUGL7 — TMS320x2803x Piccolo Enhanced Controller Area Network (eCAN) Reference Guidedescribes the operation of the Enhanced Controller Area Network (eCAN).
SPRUGE5 — TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and ComparatorReference Guide describes how to configure and use the on-chip ADC module, which is a 12-bitpipelined ADC.
SPRUGE9 — TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) ModuleReference Guide describes the main areas of the enhanced pulse width modulator that includedigital motor control, switch mode power supply control, UPS (uninterruptible power supplies), andother forms of power conversion.
SPRUGE8 — TMS320x2802x, 2803x Piccolo High-Resolution Pulse Width Modulator (HRPWM)describes the operation of the high-resolution extension to the pulse width modulator (HRPWM).
SPRUGH1 — TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) Reference Guidedescribes how to use the SCI.
SPRUFZ8 — TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module Reference Guidedescribes the enhanced capture module. It includes the module description and registers.
SPRUG71 — TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) Reference Guidedescribes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bitstream of programmed length (one to sixteen bits) to be shifted into and out of the device at aprogrammed bit-transfer rate.
SPRUFZ9 — TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) Reference Guide describesthe features and operation of the inter-integrated circuit (I2C) module.
Tools Guides—
SPRU513 — TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assemblylanguage tools (assembler and other tools used to develop assembly language code), assemblerdirectives, macros, common object file format, and symbolic debugging directives for theTMS320C28x device.
SPRU514 — TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes theTMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code andproduces TMS320 DSP assembly language source code for the TMS320C28x device.
SPRU608 — TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instructionset of the C28x™ core.
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1 Introduction and Features
1.1 Purpose
1.2 Features
Preliminary
User's GuideSPRUGE2A – May 2009 – Revised June 2009
Local Interconnect Network (LIN) Module
This document describes the buffered local interconnect network (BLIN) module. Since this module canalso operate like a conventional serial communications interface (SCI) port, it is referred to as theSCI/BLIN module in this document. In the SCI (UART) mode, it is functionally compatible to thestandalone SCI module in the TMS320x2803x device. However, since the SCI/BLIN module uses adifferent register/bit structure, code written for this module cannot be directly ported to the standalone SCImodule and vice versa.
The SCI/BLIN is compliant to the LIN 2.0 protocol specified in the LIN Specification Package. This moduleuses the SCI as its core and augments the SCI’s hardware features for LIN compatibility. This module canbe configured to operate in either LIN mode or the SCI (UART) mode. The SCI mode is also referred to ascompatibility mode in this document.
The SCI/BLIN provides a communications structure at the hardware and software level. It provides alow-cost solution where the bandwidth and fault tolerance of a controller area network (CAN) are notrequired.
The following are the features of the SCI/BLIN module:•Compatibility with LIN 1.3 or 2.0 protocols (LIN Specification Package 2002)•Two external pins: LINRX and LINTX•Functionally compatible with the standalone SCI of C2000 devices•Multi-buffered receive and transmit units•Identification masks for message filtering•Automatic master header generation– Programmable synchronization break field– Synchronization field– Identifier field•Slave automatic synchronization– Synchronization break detection– Optional baud rate update– Synchronization validation•2
28
programmable transmission rates•Wakeup on LINRX dominant level from transceiver•Automatic wakeup support– Wakeup signal generation– Expiration times on wakeup signals•Automatic bus idle detection•Error detection
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1.3 Block Diagram
Preliminary
Introduction and Features www.ti.com
– Bit error– Bus error– No-response error– Checksum error– Synchronization field error– Parity error•2 Interrupt lines with priority encoding for:– Receive
– Transmit
– ID, error, and status•Support for LIN 2.0 checksum•Enhanced synchronizer finite state machine (FSM) support for frame processing•Enhanced handling of extended frames•Enhanced baud rate generator
The SCI/BLIN module is based on the SCI with the addition of an error detector (parity calculator,checksum calculator, and bit monitor), a mask filter, a synchronizer, and a multibuffered receiver andtransmitter. The SCI interface and the baud generator are modified as part of the hardware enhancementsfor LIN compatibility. Figure 1 shows the SCI/BLIN block diagram.
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LINRX/
SCIRX
LINTX/
SCITX
READ DATA BUS
WRITE DATA BUS
ADDRESS BUS
INTERFACE
SCI
BLIN
CHECKSUM
CALCULATOR
ID PARITY
CHECKER
BIT MONITOR
TXRX ERROR
DETECTOR (TED)
TIMEOUT CONTROL
COUNTER
COMPARE
FSM
SYNCHRONIZER
MASK
FILTER
8 RECEIVE
BUFFERS
8 TRANSMIT
BUFFERS
1.4 Standards
Preliminary
www.ti.com Introduction and Features
Figure 1. SCI/BLIN Block Diagram
The LIN standard is based on the SCI (UART) serial data link format. The communication concept issingle-master/multiple-slave with a message identification for multi-cast transmission between any networknodes.
For compatibility with LIN2.0 standard, the following additional features are implemented over LIN1.3:i. Support for LIN 2.0 checksumii. Enhanced synchronizer FSM support for frame processingiii. Enhanced handling of extended framesiv. Enhanced baudrate generatorv. Update wakeup/go to sleep
The SCI/BLIN module covers the CPU performance-consuming features, defined in the LIN SpecificationPackage Revision 1.3 and 2.0 by hardware.
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2 Operation
2.1 Message Frame
Message Frame
Master Header Slave Response
Sync Break Sync Field 1, 2, 3, ...8 Data Fields Checksum
In-Frame Space
2.1.1 Message Header
SYNCH BREAK FIELD SYNCH FIELD ID FIELD
Preliminary
Operation www.ti.com
The SCI/BLIN module can be used in LIN mode or SCI (UART) mode. The enhancements for baudgeneration and additional receive/transmit buffers necessary for LIN mode operation are part of theenhanced buffered SCI/BLIN module.
Note: To make a determination of the bit value, 16 samples for each bit are taken with majorityvote on samples 8, 9, and 10.
For a detailed description of SCI/BLIN registers, see Section 6 .
The LIN protocol defines a message frame format, illustrated in Figure 2 . Each frame includes one masterheader, one response, one in-frame response space, and inter-byte spaces. In-frame-response andinterbyte spaces may be 0.
Figure 2. LIN Protocol Message Frame Format: Master Header and Slave Response
There is no arbitration in the definition of the LIN protocol; therefore, multiple slave nodes responding to aheader might be detected as an error.
The LIN bus is a single channel wired-AND. The bus has a binary level: either dominant for a value of 0,or recessive for a value of 1.
The header of a message is initiated by a master (see Figure 3 ) and consists of a three field-sequence:•The synch break field signaling the beginning of a message•The synch field conveying bit rate information of the LIN bus•The ID field denoting the content of a message
Figure 3. Header Fields: Synch Break, Synch, and ID
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2.1.2 Response
Response
1 to 8 Data Fields Checksum
Field
Interbyte Spaces
2.2 Synchronizer
Preliminary
www.ti.com Operation
The format of the response is as illustrated in Figure 4 . There are two types of fields in a response: dataand checksum. The data field consists of exactly one data byte, one start bit, and one stop bit, for a totalof 10 bits. The LSB is transmitted first. The checksum field consists of one checksum byte, one start bitand one stop bit. The checksum byte is the inverted modulo-256 sum over all data bytes in the data fieldsof the response.
Figure 4. Response Format of LIN Message Frame
The format of the response is a stream of "N" data fields and one checksum field. Typically N is from 1 to8, with the exception of the extended command frames. The length N of the response is indicated with theoptional length control bits of the identifier, or by the SCIFORMAT(18–16) register ( Section 6.11 ); seeTable 1 . The SCI/BLIN module supports response lengths from 1 to 8 bytes in compliance with LIN 2.0.
Table 1. Response Length with SCIFORMAT(18–16) Programming
SCIFORMAT (18–16) No. of Bytes
000 1001 2010 3011 4100 5101 6110 7111 8
The synchronizer has three major functions in the messaging between master and slave nodes. Itgenerates the master header data stream, it synchronizes to the LIN bus for responding, and it locallydetects timeouts. A bit rate is programmed using the prescalers in the BRS register as indicated by theLIN_speed value in the LIN description file (LDF).
The SCI/BLIN synchronizer will perform the following functions: master header signal generation, slavedetection and synchronization to message header with optional baud rate adjusting, responsetransmission timing and timeout control.
The SCI/BLIN synchronizer should be capable of detecting an incoming break and initializecommunication at all times.
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2.3 Baud Rate
2.3.1 Fractional Divider
CLKLM
T_bit 16
M
1P16TM ,alland0,other thanPallFor ú
û
ù
ê
ë
é++=
L M _ C L Kb it 32TT:0PFor ==
z e r oo th e r th a nPa llf o r,
1 6
11 6
_
FL I N C L K
ú
û
ù
ê
ë
é++
=M
P
C L KL M
0Pfor,
32
_
FL IN C L K == C L KL M
2.4 Header Generation
Preliminary
Operation www.ti.com
The LIN module is clocked at a frequency of one-half the CPU clock (SYSCLKOUT). i.e. LIN Module inputclock (LM_CLK) = SYSCLKOUT/2. For a 60 MHz device, LM_CLK = 30 MHz.
The transmission baud rate of any node is configured by the CPU in the beginning; this defines the bittime T
bit
. The bit time is derived from the fields P and M in the baud rate selection register (BRSR;Section 6.12 ).
The ranges for the prescaler values in the BRSR are:
P = 0, 1, 2, 3, . . . , 2
24
- 1
M = 0, 1, 2, . . . , 15
The BRSR with P and M values are user programmable. These divider values are automatically obtainedin LIN mode (during header reception) when the synchronization field is measured, if the ADAPT bit is set.Otherwise, the P and M dividers could be used for both SCI mode and LIN mode to select a baud rate.
The LIN protocol defines baud rate boundaries as follows:
1kHz ≤F
LINCLK
≤20kHZ
All transmitted bits are shifted in and out at T
bit
periods.
The M field of the BRSR register (Section 6.12 ) modifies the integer prescaler P for finer tuning of thebaud rate. The M value adds in increments of 1/16 of the P value.
Therefore, the LINCLK frequency is given by
Therefore, the LINCLK frequency is given by:
Note: LM_CLK = 30 MHz, T
LM_CLK
= 33.3 ns for a 60 MHz device.
Automatic generation of the LIN protocol header data stream is supported without CPU interaction. TheCPU will trigger a message header generation and the SCI/BLIN state machine will handle the generationitself. The header is always sent by the master to initiate a LIN communication and consists of three fields:synchronization break field, synchronization field, and identification field, as seen in Figure 5 .•The synchronization break field consists of two components.– The synchronization break (SYNCH BREAK) consists of a minimum of 13 (dominant) low bits to amaximum of 20 dominant bits. The synch break length may be extended from the minimum with the3- bit SBREAK value in the LINCOMP register.
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10101
SYNCH BREAK
13+(0...7) Tbit SDEL
1..4 Tbit
SYNCH FIELD
10 Tbit
ID FIELD
10 Tbit
010
Start Bit
Stop Bit
Optional
Length
Control
Bits
Optional
Parity
Bits
ID Field
Start
Bit
Stop
Bit
ID0 ID1 ID2 ID3 ID4 ID5 P0 P1
Preliminary
www.ti.com Operation
– The synchronization break delimiter (SDEL) consists of a minimum of 1 (recessive) high bit to amaximum of 4 recessive bits. The delimiter marks the end of the synchronization break field. Thesynch break delimiter length depends on the 2-bit SDEL value in the LINCOMP register.•The synchronization field (SYNCH FIELD) consists of one start bit, byte 0x55, and a stop bit. It is usedto convey T
bit
information and resynchronize LIN bus nodes.•The identifier field’s ID byte may use six bits as an identifier (optional length control within it), and twooptional bits as parity of the identifier. The identifier parity is used and checked if the (SCIGCR1.2)PARITY enable bit is set. If length control bits are not used, then there can be a total of 64 identifiersplus parity. If neither length control or parity are used there can be up to 256 identifiers. See Figure 6for an illustration of the ID field.
Note: The LIN protocol uses the parity bits in the identifier. The control length bits are optional tothe LIN protocol.
Figure 5. Message Header in Terms of T
bit
A master node initiates header generation on CPU writes to the IDBYTE in the LINID register(Section 6.19 ).
Note: IDBYTE [LINID(5–4); Section 6.19 ] conveys response length information if compliant tostandards earlier than LIN 1.3.
ID5 ID4 Number of Data bytes
002012104118
The SCIFORMAT register (Section 6.11 ) stores the length of the response for later versions of the LINprotocol.
Figure 6. ID Field
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2.4.1 Event Triggered Frame Handling
2.4.2 Header Reception and Adaptive Baud Rate
SYNCH Break SDEL SYNCH Field
10 Tbit
ID Field
10 Tbit
BRK-count BAUD-count
1 2 34
10101010
Start Bit
Stop Bit
Preliminary
Operation www.ti.com
The LIN 2.0 protocol uses event-triggered frames that may occasionally cause collisions. Event-triggeredframes have to be handled in software.
If no slave answers to an event triggered frame header, the master node will set the NRE flag and a NREinterrupt will occur if enabled. If a collision occurs, a frame error and checksum error may arise before theNRE error. Those errors are flagged and the appropriate interrupts will occur, if enabled.
Frame errors and checksum errors depend on the behavior and synchronization of the responding slaves.If the slaves are totally synchronized and stop transmission once the collision occurred, it is possible thatonly the NRE error is flagged despite the occurrence of a collision. To detect if there has been a receptionof one byte before the NRE error is flagged use the bus busy flag (SCIFLR.3) as an indicator.
The bus busy flag is set on the reception of the first bit of the header and remains set until the headerreception is complete, and again is set on the reception of the first bit of the response. In the case of acollision, the flag is cleared in the same cycle as the NRE flag is set.
Software could implement the following sequence:•Once the reception of the header is done (poll for RXID flag), wait for the bus busy flag to get set orNRE flag to get set.•If bus busy flag is not set before NRE flag, then it is a true no response case (no data has beentransmitted onto the bus).•If bus busy flag gets set, then wait for NRE flag to get set or for successful reception. If NRE flag is set,then in this case a collision has occurred on the bus.
Even in the case of a collision, the received (corrupted) data is accessible in the RX buffers; registersLINRD0 and LINRD1.
A slave node baud rate might be adjusted to the detected bit rate as an option in the SCI/BLIN module.The adaptive baud rate option is enabled by setting the ADAPT bit in SCIGCR1 (Section 6.2 ). Duringheader reception, a slave measures the baud rate during detection of the synch field. If SCIGCR1[10] (theADAPT bit) is set, then the measured baud rate is compared to the slave node’s programmed baud rateand adjusted to the LIN bus baud rate if necessary.
The SCI/BLIN synchronizer determines two measurements: BRK_count and BAUD_count (Figure 7 ).These values are always calculated during the Header reception for synch field validation (Figure 8 ).
Note: When an inconsistent synch field (ISF) error occurs, suggested action for the application is•Reset the SWnRST bit.•Set the SWnRST bit to make sure that the internal FSMs are back to their normal states
Figure 7. Measurements for Synchronization
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Wait for falling edge
LINRX = 1
while LINRX = 0
Increment Counter
Counter
>= 11Tbit?
No
Yes
Reset Counter
LINRX = 0
Increment Counter
2On LINRX
Save counter
(SBRK_count)
and reset it
3On 1st LINRX falling edge
1
Increment counter
4On 5th LINRX falling edge
Save counter (BAUD_count)
Verify valid Synch Field
If ADAPT = 1, compare baud rate
and Baud Update flag is set
if baudrates differ
Receive ID Field
Wait for Response
On LINRX
BRK_count3»BAUD_count2»BAUD_countBAUD_count £++
Preliminary
www.ti.com Operation
Figure 8. Synchronization Validation Process and Baud Rate Adjustment
By measuring the values BRK_count and BAUD_count, a valid synch break sequence can be detected asdescribed in Figure 8 . The four numbered events in Figure 7 signal the start/stop of the synchronizercounter. The synchronizer counter uses LM_CLK as the time base.
The synchronizer counter is used to measure the synch break relative to the detecting node T
bit
. For aslave node receiving the synch break, a threshold of 11 T
bit
is used as required by the LIN protocol. Fordetection of the dominant data stream of the synch break, the synchronizer counter is started on a fallingedge and stopped on a rising edge of the LINRX. On detection of the synch break delimiter, thesynchronizer counter value is saved and then reset.
On detection of five consecutive falling edges, the BAUD_count is measured. Bit timing calculation andconsistency to required accuracy is implemented following the recommendations of LIN revision 2.0. Aslave node can calculate a single T
bit
time by division of BAUD_count by 8. In addition, for consistencybetween the detected edges the following is evaluated:
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2.5 Extended Frames Handling
Extended Frame With Embedded Checksum Bytes
Master Header N Data Fields Response
In-Frame Space
Sync Break Sync Field ID Field Checksum Checksum Checksum
Preliminary
Operation www.ti.com
The BAUD_count value is shifted 3 times to the right and rounded using the first insignificant bit to obtaina T
bit
unit. If the ADPAT bit is set then, the detected baud rate is compared to the programmed baud rate.
During the header reception processing as illustrated in Figure 8 , if the measured BRK_count value is lessthan 11 T
bit
the synch break is not valid according to the protocol for a fixed rate. If the ADAPT bit is set,then the MBRS (Section 6.22 ) is used for measuring BRK_count and BAUD_count values andautomatically adjusts to any allowed LIN bus rate (refer to LIN Specification Package 2.0).
Note: The MBRS divider should be set so that the rate is 20 kHz.
Note: The synch-break-threshold relative to the slave node is 11 T
bit
. The synch break is 13 T
bit
asspecified in LIN version 1.3.
If the synch field is not detected within the given tolerances, the inconsistent-synch-field-error (ISFE) flagwill be set. An ISFE interrupt will be generated, if enabled by its respective bit in the SCISETINT register(Section 6.6 ). The ID byte should be received after the synch field validation was successful. Any time avalid synch break (larger than 11 T
bit)
is detected, the receiver’s state machine should reset to reception ofthis new frame. This reset condition is only valid during response state, it should not occur if an additionalsynch break occurs during header reception.
The LIN protocol includes two extended frames with identifiers 62 (user defined) and 63 (reservedextended). The length for these identifiers will be set during network configuration and are to be sharedwith the LIN bus nodes.
Note: Only identifier 62 (0x3E) applies to this special extended frame handling of unlimitedresponse length.
Extended frame communication is triggered on reception of a header with identifier 0x3E; see Figure 9 .Once the extended frame communication is triggered, unlike normal frames, this communication needs tobe stopped before issuing another header. To stop the current extended frame communication, theSCIGCR1.13 bit must be set.
Figure 9. Optional Embedded Checksum in Response for Extended Frames
For the LIN 2.0 specification, the length of the user-defined frame is unlimited. Therefore, an ID interruptwill be generated (if enabled and there is a match) on reception of this identifier. This interrupt allows theCPU using a software counter to keep track of the bytes that are being sent out and decides when tocalculate and insert a checksum byte (recommended at periodic rates). To handle this procedure, bitSCIGCR2[16] (Section 6.3 ) is used. A write to the SCIGCR2[16] bit will initiate an automatic send of thecheckbyte. The last data field should be a checksum in compliance with the LIN protocol.
The periodicity of the checksum insertion, defined during network configuration, is used by the receivingnode to evaluate the checksum of the ongoing message and has the benefit of enhanced reliability.
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SCIRXSHF
Checksum Calculator
SCITXSHF
7
7
0
0
RX
TX
Send
Checksum
Compare
Checksum
2.6 Timeout Control
2.6.1 No-Response Error
Preliminary
www.ti.com OperationFor the sending node, the automatic embedding of checksum should be possible when the SCIGCR2[16]bit is set. For the receiving node, a checksum comparison should be forced when the SCIGCR2[17] bit isset; see Figure 10 .
Note: The LIN 2.0 enhanced checksum does not apply to the reserved identifiers. They will alwaysuse the classic checksum.
Figure 10. Checksum Compare and Send for Extended Frames
Any SCI/BLIN node listening to the bus and expecting a response initiated from a master node could flaga no-response error timeout event. The LIN protocol defines four types of timeout events, which are allhandled by the hardware of the SCI/BLIN module. The four LIN protocol events are:•No-response timeout error•Bus idle detection•Timeout after wakeup signal•Timeout after three wakeup signals
The no-response error will occur when any node expecting a response waits for T
FRAME_MAX
time and themessage frame is not fully completed within the maximum length allowed, T
FRAME_MAX
. After this time ano-response error (NRE) is flagged in the NRE bit of the SCIFLR register. An interrupt is triggered ifenabled.
As specified in the LIN 1.3 standard, the minimum time to transmit a frame is:
T
FRAME_MIN
= T
HEADER_MIN
+ T
DATA_FIELD
+ TC
HECKSUM_FIELD
= 44 + 10N
where N = number of data fields.
And the maximum time frame is given by:
T
FRAME_MAX
= (T
FRAME_MIN
+ 1) ×1.4
The timeout value T
FRAME_MAX
is derived from the N number of data fields value. The N value is eitherembedded in the header’s ID field for messages or is part of the description file. In the latter case, the3-bit CHAR value, SCIFORMAT(18–16) in Section 6.11 , will indicate the value for N.
Table 2. Timeout Values in T
bit
Units
N T
DATA_FIELD
T
FRAME_MIN
T
FRAME_MAX
1 10 54 772 20 64 91
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2.6.2 Bus Idle Detection
2.6.3 Timeout after Wakeup Signal and Timeout after Three Wakeup Signals
2.7 TXRX Error Detector (TED)
2.7.1 Bit Errors
Preliminary
Operation www.ti.com
Table 2. Timeout Values in T
bit
Units (continued)
N T
DATA_FIELD
T
FRAME_MIN
T
FRAME_MAX
3 30 74 1054 40 84 1195 50 94 1336 60 104 1477 70 114 1618 80 124 175
Note: The length coding of the ID field does not apply to two extended frame identifiers, with IDfields 0x3E (62) and 0x3F (63). In these cases, the ID field can be followed by an arbitrarynumber of data byte fields. The LIN 2.0 protocol specification mentions that ID field 0x3F (63)cannot be used. For these two cases, the NRE will not be handled by the SCI/BLIN controllerhardware.
The second type of timeout can occur when a node detects an inactive LIN bus: no transitions betweenrecessive and dominant values are detected on the bus. This should happen after a minimum of 4 s (thisis 80,000 F
LINCLK
cycles with the fastest bus rate of 20 kbps). If a node detects no activity in the bus as theTIMEOUT bit is set (Section 6.8 ), then it can be assumed that the LIN bus is in sleep mode.
The third and fourth types of timeout are related to the wakeup signal. A node initiating a wakeup shouldexpect a header from the master within a defined amount of time: timeout after wakeup signal. SeeSection 4.3 for more details.
The following sources of error are detected by the TXRX error detector logic (TED). The TED logicconsists of a bit monitor, an ID parity checker, and a checksum error. The following errors are detected:•Bit errors (BE)•Physical bus errors (PBE)•Identifier parity errors (PE)•Checksum errors (CE)
All of these errors (BE, PBE, PE, CE) are flagged. An interrupt for the flagged errors will be generated ifenabled. A message is valid for both the transmitter and the receiver if there is no error detected until theend of the frame.
A BE has to be detected at that bit time when the bit value that is monitored is different from the bit valuethat is sent. A BE is indicated by the BE flag in SCIFLR (Section 6.8 ). After signaling a BE, thetransmission has to be aborted no later than the next byte. The bit monitor ensures that the transmitted bitin LINTX is the correct value on the LIN bus by reading back on the LINRX pin as shown in Figure 11 .
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