Texas Instruments TPS54325 User manual

User’s Guide
TPS54325 Step-Down Converter Evaluation Module User's
Guide
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Background........................................................................................................................................................................ 3
1.2 Performance Specification Summary.................................................................................................................................3
1.3 Modifications...................................................................................................................................................................... 3
2 Test Setup and Results.......................................................................................................................................................... 4
2.1 Test Setup.......................................................................................................................................................................... 4
2.2 Test Procedure................................................................................................................................................................... 4
2.3 Efficiency............................................................................................................................................................................5
2.4 Load Regualtion................................................................................................................................................................. 5
2.5 Line Regulation.................................................................................................................................................................. 6
2.6 Load Transient Response.................................................................................................................................................. 6
2.7 Output Voltage Ripple........................................................................................................................................................ 7
2.8 Input Voltage Ripple........................................................................................................................................................... 7
2.9 Start Up.............................................................................................................................................................................. 8
2.10 Switching Frequency........................................................................................................................................................8
3 Board Layout...........................................................................................................................................................................9
3.1 Layout................................................................................................................................................................................ 9
4 Schematic and Bill of Materials...........................................................................................................................................13
4.1 Schematic........................................................................................................................................................................ 13
4.2 Bill of Materials.................................................................................................................................................................14
5 References............................................................................................................................................................................ 15
6 Revision History................................................................................................................................................................... 15
List of Figures
Figure 2-1. Equipment Setup for TPS54325EVM Board............................................................................................................. 4
Figure 2-2. TPS54325EVM Efficiency......................................................................................................................................... 5
Figure 2-3. TPS54325EVM Load Regulation.............................................................................................................................. 5
Figure 2-4. TPS54325EVM Line Regulation................................................................................................................................6
Figure 2-5. TPS54325EVM Load Transient Response................................................................................................................6
Figure 2-6. TPS54325EVM Output Voltage Ripple......................................................................................................................7
Figure 2-7. TPS54325EVM Input Voltage Ripple........................................................................................................................ 7
Figure 2-8. TPS54325EVM Start Up........................................................................................................................................... 8
Figure 2-9. TPS54325EVM Switching Frequency....................................................................................................................... 8
Figure 3-1. Top Assembly............................................................................................................................................................ 9
Figure 3-2. Top Layer.................................................................................................................................................................10
Figure 3-3. Internal Layer 1....................................................................................................................................................... 10
Figure 3-4. Internal Layer 2........................................................................................................................................................11
Figure 3-5. Bottom Layer........................................................................................................................................................... 11
Figure 3-6. Bottom Assembly (as Viewed from Back Side)....................................................................................................... 12
Figure 4-1. TPS54325EVM Schematic Diagram....................................................................................................................... 13
List of Tables
Table 1-1. EVM Input Voltage and Output Current Summary...................................................................................................... 3
Table 1-2. TPS54325EVM Performance Specifications Summary.............................................................................................. 3
Table 1-3. Output Voltages.......................................................................................................................................................... 4
Table 4-1. Bill of Materials..........................................................................................................................................................14
Trademarks
SWIFT™, D-CAP2™ and are trademarks of Texas Instruments.
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All trademarks are the property of their respective owners.
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1 Introduction
This user’s guide contains background information for the TPS54325 as well as support documentation for the
TPS54325EVM evaluation module. Also included are the performance specifications, schematic and the bill of
materials for the TPS54325EVM.
1.1 Background
The TPS54325 is a single, adaptive on-time D-CAP2™ mode synchronous buck converter. System designers
may use the TPS54325 to complete various end equipment dc/dc converters with a low cost, low component
count, low standly current solution. The main control loop for the TPS54325 uses the D-CAP2™ mode that
optimized for low ESR output capacitors such as POSCAP, SP-CAP, High Polymer Chemistry or ceramic types.
This control loop implementation provides fast transient response with no external compensation components.
The TPS54325 dc/dc synchronous converter is designed to provide up to a 3-A output from an input control
voltage source (VCC) of 4.5 V to 18 V, input power voltage source (VIN) of 2.0 V to 18 V and output voltage from
0.76 V to 5.5 V. Rated input voltage and output current range for the evaluation module are given in Table 1-1.
Table 1-1. EVM Input Voltage and Output Current Summary
EVM INPUT VOLTAGE RANGE OUTPUT CURRENT RANGE
TPS54325EVM VIN = 5 V to 17 V 0 A to 3 A
1.2 Performance Specification Summary
A summary of the EVM performance specifications is provided in Table 1-2. Specifications are given for an input
voltage of VIN = 12 V and an output voltage of 1.05 V, unless otherwise noted. The VIN and VCC input voltage
pins are cnnected on the EVM using a 0-Ω resistor (R9). The ambient temperature is 25°C for all measurement,
unless otherwise noted.
Table 1-2. TPS54325EVM Performance Specifications Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range (VIN) 5 12 17 V
Output voltage 1.05 V
Operating frequency VIN = 12 V, Iout1 = 1 A 700 kHz
Output current range 0 3 A
Over current limit VIN = 12 V 4.1 A
Output ripple voltage VIN = 12 V, Iout1 = 3 A 9 mVp-p
Efficiency VIN = 12 V, VOUT = 3.3 V, IOUT = 1.2 A 91 %
1.3 Modifications
These evaluation modules are designed to provide access to the feature set of the TPS54325. Some
modification can be made to these modules.
1.3.1 Output Voltage Set Point
The output voltage of the EVM is set using the voltage divider of R1 + R4 and R2. To change the output voltage
of the EVMs, it is necessary to change the value of resistors R1 and R4 while leaving R2 fixed. Changing the
value of R1 and R4 can change the output voltage above 0.765 V.The value of R1 and R4 for a specific output
voltage basically can be calculated using Equation 1.
1
0.765 (1 )
2
RR
VOR = · +
+4
(1)
Table 1-3 lists the each R1 and R4 value for some common output voltages. C9 is used for faster load transient
response and is not normally used. Note that the values given in Table 1-3 are standard values, and not the
exact value calculated using Table 1-3.
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Table 1-3. Output Voltages
Output Voltage (V) R1(Ω) R4(Ω) R2(Ω) C9(pF) L1(H)
1.0 6.8 k 100 22 k 1..5 μ
1.05 8.2 k 220 22 k 1.5 μ
1.2 12 k 820 22 k 1.5 μ
1.8 27 k 3.0 k 22 k 10 - 22 2.2 μ
2.5 47 k 3.0 k 22 k 10 - 22 2.2 μ
3.3 68 k 4.7 k 22 k 10 - 22 2.2 μ
5 120 k 1.2 k 22 k 10 - 22 3.3 μ
2 Test Setup and Results
This section describes how to properly connect, set up, and use the TPS54325 EVM. The section also includes
test results typical for the evaluation modules and efficiency, output load regulation, output line regulation, load
transient response, output voltage ripple, input voltage ripple, start up and switching frequency.
2.1 Test Setup
Connect test equipment and TPS54325EVM board as shown in Figure 2-1.
TPS54325EVM-001
Electronic
Load1
+
–
Oscilloscope
Ch1
VO
VO_GND
12V/ 4A
Power Supply
VIN_GND
VIN
+
–
DMM2
+
–
DMM1
+
–
TP6
TP9
TP 8
TP4
FAN
Figure 2-1. Equipment Setup for TPS54325EVM Board
2.2 Test Procedure
1. Make sure the switch SW1 (EN) is in the “OFF” position.
2. Apply the appropriate VIN voltage to VIN and VIN_GND terminals.
3. Turn on SW1 (EN) to enable the EVM output voltage.
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2.3 Efficiency
Figure 2-2 shows the efficiency for the TPS54325EVM at an ambient temperature of 25°C. The EVM was
modified for operation at 3.3-, 2.5- and 1.8-V output using the R1 and R4 values inTable 1-3.
EFFICIENCY
VS
OUTPUT CURRENT V = 3.3 V, 2.5 V and 1.8 V
O
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0 2.5 3.0
I - Output Current - A
OUT
Efficiency - %
V = 3.3 V
O
V = 2.5 V
O
V = 1.8 V
O
Figure 2-2. TPS54325EVM Efficiency
2.4 Load Regualtion
The load regulation for the TPS54325EVM is shown Figure 2-3.
1.05 V OUTPUT VOLTAGE
VS
OUTPUT CURRENT
1.000
1.025
1.050
1.075
1.100
0.0 0.5 1.0 1.5 2.0 2.5 3.0
I - Output Current - A
OU T
V - Output Voltage - V
OUT
V = 12 V
IN
V = 18 V
IN
V = 5 V
IN
Figure 2-3. TPS54325EVM Load Regulation
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2.5 Line Regulation
The line regulation for the TPS54325EVM is shown Figure 2-4.
1.05 V OUTPUT VOLTAGE
VS
INPUT VOLTAGE
1.000
1.025
1.050
1.075
1.100
0 5 10 15 20
V (V)
IN
V - Output Voltage - V
OUT
I = 0 A
O
I = 3 A
OI = 1.5 A
O
Figure 2-4. TPS54325EVM Line Regulation
2.6 Load Transient Response
The TPS54325EVM response to load transient is shown in Figure 2-5. The current step is from 0 A to
3 A of maximum rated load. Total peak to peak voltage variation is as shown.
V (50 mV/div)
O
I (2 A/div)
O
100 s/divµ
Figure 2-5. TPS54325EVM Load Transient Response
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2.7 Output Voltage Ripple
The TPS54325EVM output voltage ripple is shown in Figure 2-6. The output current is the rated full load of 3 A.
V (10 mV/div)
O
SW (5 V/div)
400 ns/div
Figure 2-6. TPS54325EVM Output Voltage Ripple
2.8 Input Voltage Ripple
The TPS54325EVM input voltage ripple is shown in Figure 2-7. The output current is the rated full load of 3 A.
V (50 mV/div)
IN
SW (5 V/div)
400 ns/div
Figure 2-7. TPS54325EVM Input Voltage Ripple
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2.9 Start Up
The TPS54325EVM start up waveform is shown in Figure 2-8.
EN(10 V/div)
VO(0.5 V/div)
PG(5 V/div)
400 µs/div
Figure 2-8. TPS54325EVM Start Up
2.10 Switching Frequency
The TPS54325EVM switching frequency is shown in Figure 2-9.
V = 1.8 V
O
V = 3.3 V
O
f - Switching Frequency - kHz
SW
V - Input Voltage - V
IN
900
800
700
600
500
0510 15 20
SWITCHING FREQUENCY
VS
INPUT VOLTAGE
Figure 2-9. TPS54325EVM Switching Frequency
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3 Board Layout
This section provides description of the TPS54325EVM, board layout, and layer illustrations.
3.1 Layout
The board layout for the TPS54325EVM and is shown in Figure 3-1 through Figure 3-6. The top layer contains
the main power traces for VIN , VOUT and the SW1 and SW2 nodes. Also on the top layer are connections
for the pins of the TPS54325 and a large area filled with power ground (PGND) connected to pins 8 and 9 of
the TPS54325. The first internal layer is a split ground plane containing a large power ground (PGND) area
and a smaller signal ground (GND) area. The second internal layer contains an additional VIN trace and a
connection from switch SW1 to VCC. The remainder of the second internal layer is power ground (PGND) area.
The bottom layer contans the remainder of the circuit interconnect traces and the signal ground plane (GND)
that is connected to pin 5 of the TPS54325 through a via near the pin. The signal ground and power ground are
electrically common. They are connected together on the pcb at the pin 5 and the powerpad of the TPS54325.
The bottom assembly layer is shown as looking from the back side of the printed circuit board.
The input decoupling capacitor and all parts are located as close to the IC as possible.
T
I
EXAS
NSTRUMENTS
Figure 3-1. Top Assembly
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Figure 3-2. Top Layer
Figure 3-3. Internal Layer 1
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