Texas Instruments TSW12QJ1600 User manual

TSW12QJ1600 Evaluation Module
User's Guide
Literature Number: SLAU796
July 2020

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Contents
Contents
Preface ........................................................................................................................................ 4
1 Introduction......................................................................................................................... 5
2 Equipment........................................................................................................................... 7
2.1 Evaluation Board Feature Identification Summary ...................................................................... 7
2.2 Required Equipment......................................................................................................... 8
3 Setup Procedure.................................................................................................................. 9
3.1 Install the High Speed Data Converter (HSDC) Pro Software......................................................... 9
3.2 Install the Configuration GUI Software.................................................................................... 9
3.3 Connect the EVM and TSW14J58EVM ................................................................................. 10
3.4 Connect the Power Supplies to the Boards (Power Off).............................................................. 10
3.5 Connect the Signal Generators to the EVM (RF Outputs Disabled Until Directed) ............................... 10
3.6 Turn On the TSW14J58EVM Power and Connect to the PC ........................................................ 10
3.7 Turn On the TSW12QJ1600EVM Power Supplies and Connect to the PC ........................................ 10
3.8 Turn On the Signal Generator RF Outputs ............................................................................. 10
3.9 Open the TSW12QJ1600EVM GUI and Program the ADC and Clocks ............................................ 11
3.10 Calibrate the ADC Device on the EVM.................................................................................. 12
3.11 Open the HSDCpro Software and Load the FPGA Image to the TSW14J58EVM................................ 13
3.12 Capture Data Using the HSDC Pro Software .......................................................................... 13
4 Device Configuration .......................................................................................................... 15
4.1 Supported JESD204C Device Features................................................................................. 15
4.2 Tab Organization........................................................................................................... 15
4.3 Low-Level Control.......................................................................................................... 16
5 Troubleshooting the TSW12QJ1600EVM ............................................................................... 17
A References ........................................................................................................................ 18
A.1 Technical Reference Documents......................................................................................... 18
A.2 TSW14J58EVM Operation................................................................................................ 18
B HSDC Pro Settings for Optional ADC Device Configuration..................................................... 19
B.1 Changing the Number of Frames per Multi-Frame (K)................................................................ 19
B.2 Customizing the EVM for Optional Clocking Support ................................................................. 19
B.2.1 Onboard 50M Ref to ADC PLL (Default)....................................................................... 19
B.2.2 "Ext Ref to ADC PLL" ............................................................................................ 20

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List of Figures
List of Figures
1-1. EVM Orientation ............................................................................................................. 5
2-1. EVM Feature Locations..................................................................................................... 7
3-1. EVM Test Setup.............................................................................................................. 9
3-2. Configuration GUI EVM Tab.............................................................................................. 11
3-3. Configuration GUI ADC Control .......................................................................................... 12
3-4. High Speed Data Converter Pro (HSDC) GUI.......................................................................... 14
4-1. Low-Level Register Control Tab ......................................................................................... 16
B-1. Onboard 50M Ref to ADC PLL System Block Diagram............................................................... 20
B-2. Ext Ref to ADC PLL System Block Diagram ........................................................................... 20
List of Tables
4-1. Supported and Non-Supported Features of the JESD204C Device................................................. 15
4-2. Low-Level Controls......................................................................................................... 16
5-1. Troubleshooting ............................................................................................................ 17

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Preface
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This user’s guide describes the characteristics, operation, and use of the TSW12QJ1600 evaluation
module (EVM). This user's guide discusses how to set up and configure the software and hardware, and
reviews various aspects of the program operation. Throughout this document, the terms evaluation board,
evaluation module, and EVM are synonymous with the TSW12QJ1600EVM. In the following sections of
this document, the TSW12QJ1600 evaluation board is referred to as the EVM and the TSW12QJ1600
device is referred to as the ADC device. This document also includes an electrical schematic, printed
circuit board (PCB) layout drawings, and a parts list for the EVM.
Trademarks
K&L Microwave is a trademark of K&L Microwave.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
Rohde & Schwarz is a registered trademark of Rohde & Schwarz GmbH & Co.
Trilithic is a trademark of Trilithic, Inc.
All other trademarks are the property of their respective owners.

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Introduction
Chapter 1
SLAU796–July 2020
Introduction
The TSW12QJ1600EVM is an evaluation board used to evaluate ADC12QJ1600 analog-to-digital
converters (ADC) from Texas Instruments with different front end options. The ADC12QJ1600 is a quad
channel, 12-bit ADC, capable of operating at sampling rates up to 1.6 Giga- samples per second (GSPS)
with four analog input channels. This design has two ADC12QJ1600 devices on the same PCB, this
design can be used to demonstrate multiple ADC synchronization, deterministic latency and test the
performance of the ADC with various front end options (AC coupled transformer, DC coupled option with
LMH32401) The design also demonstrate how clocking scheme can be simplified by daisy-chaining PLL
refout from one ADC to other ADC. Eliminating the need to clock distribution chip usually needed by JESD
devices. The TSW12QJ1600EVM output data is transmitted over a standard JESD204C high-speed serial
interface. This evaluation board also includes the following important features
• Transformer-coupled signal input network allowing a single-ended signal source from 10 MHz to
4 GHz. Option to bypass the transformer and use DC coupled differential inputs
• LM95233 temperature sensor
• High-speed serial data output over a High Pin Count FMC interface connector
NOTE: To improve signal routing quality, serial lanes are mapped differently with respect to the
standard FMC VITA-57 signal mapping.
• Device register programming through USB connector and FTDI USB-to-SPI bus translator with an
option to program through the FMC+ connector
Figure 1-1. EVM Orientation
The digital data from the TSW12QJ1600EVM board is quickly and easily captured with the
TSW14J58EVM data capture boards.

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Introduction
NOTE: The TSW14J58EVM can only be used be used for JMODES 8 at a maximum sampling rate
of 1GSPS.
The TSW14J58EVM captures the high-speed serial data, decodes the data, stores the data in memory,
and then uploads it to a connected PC through a USB interface for analysis. The High-Speed Data
Converter Pro (HSDC Pro) software on the PC communicates with the hardware and processes the data.

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Equipment
Chapter 2
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Equipment
This section describes how to setup the EVM on the bench with the proper equipment to evaluate the full
performance of the ADC device.
2.1 Evaluation Board Feature Identification Summary
Figure 2-1. EVM Feature Locations

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Equipment
2.2 Required Equipment
The following equipment and documents are included in the EVM evaluation kit:
• Evaluation board (EVM)
• Mini-USB cable
• Power cable
The following equipment is not included in the EVM evaluation kit, but is required for evaluation of this
product:
• TSW14J58EVM data capture board and related items
• PC computer running Microsoft®Windows®7, or 10
• One low-noise signal generator for providing a reference signal for the ADC PLL. ONLY need with
external reference clocking option is desired. TI recommends the following generators:
– Rohde & Schwarz®SMA100B
– Rohde & Schwarz®SMA100A
• One low-noise signal generator for analog input. TI recommends the following generators:
– Rohde & Schwarz®SMA100B
– Rohde & Schwarz®SMA100A
• Bandpass filter for analog input signal (97 MHz or desired frequency). The following filters are
recommended:
– Bandpass filter, greater than or equal to 60-dB harmonic attenuation, less than or equal to 5%
bandwidth, greater than 18-dBm power, less than 5-dB insertion loss
– Trilithic™ 5VH-series tunable BPF
– K&L Microwave™ BT-series tunable BPF
– TTE KC6 or KC7-series fixed BPF
• Signal-path cables, SMA to SMP or BNC (or both SMA and BNC)
By default, the TSW12QJ1600EVM is configured to use a 50-MHz onboard crystal oscillator to provide
reference input to the ADC PLL which is used to generate the sampling clock to the ADC (In the GUI this
option is labeled as " OnBoard 50M Ref to ADC PLL"). A few small board modifications allow the direct
external sampling clock option (In the GUI this option is labeled as "Ext Ref to ADC PLL").

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Setup Procedure
Chapter 3
SLAU796–July 2020
Setup Procedure
Figure 3-1. EVM Test Setup
NOTE: The HSDC Pro software must be installed before connecting the TSW14J58EVM to the PC
for the first time.
3.1 Install the High Speed Data Converter (HSDC) Pro Software
1. Download the most recent version of the HSDC Pro software from www.ti.com/tool/dataconverterpro-
sw. Follow the installation instructions to install the software.
2. Download and copy all the INI files required to the HSDCpro directory from the TSW12QJ1600EVM
web page on ti.com. The INI files should be copied to following location C:\Program Files (x86)\Texas
Instruments\High Speed Data Converter Pro\14J58 Details\ADC files
3.2 Install the Configuration GUI Software
1. Download the Configuration GUI software from the TI.com software page .
2. Extract files from the .zip file.
3. Run the executable file (setup.exe), and follow the instructions.

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Setup Procedure
3.3 Connect the EVM and TSW14J58EVM
With the power off, connect the TSW12QJ1600EVM (with the daughter card already mounted on base
board) to the TSW14J58EVM through the FMC+ connector as shown in Figure 3-1. Ensure that the
standoffs provide the proper height for robust connector connections.
3.4 Connect the Power Supplies to the Boards (Power Off)
1. Confirm that the power switch on the TSW14J58EVM is in the off position. Connect the power cable to
a 6-V DC (minimum 4 A) power supply. Ensure the proper supply polarity by confirming that the outer
surface of the barrel connector is GND and the inner portion of the connector is 6 V. Connect the
power cable to the EVM power connector.
2. Confirm that the power switch for the power supply of the TSW12QJ1600EVM is in the off position.
Connect the power cable to a 5-V DC (minimum 2.5 A) power supply. Ensure the proper supply
polarity by confirming that the outer surface of the barrel connector is GND and the inner portion of the
connector is 5 V. Connect the power cable to the EVM power connector.
CAUTION
Ensure the power connections to the EVMs are the correct polarity.
Failure to do so may result in immediate damage.
Leave the power switches in the off position until directed later.
3.5 Connect the Signal Generators to the EVM (RF Outputs Disabled Until Directed)
Connect a signal generator to any of the input labeled J2–J9 on the daughter card connected to the
TSW12QJ1600EVM through a bandpass filter and at the SMP connector. This must be a low-noise signal
generator. TI recommends a Trilithic-tunable bandpass filter to filter the signal from the generator.
Configure the signal generator for 97 MHz, 0 dBm.
When onboard 50-MHz crystal oscillator is used as a reference for the ADC PLL (Default):
a. By default, the EVM is set to use the onboard 50-MHz crystal oscillator to supply the 50-MHz reference
to the ADC PLL.
b. Skip this step for default ("OnBoard 50M Ref to ADC PLL ") EVM setup. This step should only be
followed when "Ext Ref to ADC PLL mode is desired. The reference clock signal for the ADC PLL of
desired frequency (50 MHz to 500 MHz) is applied at the SMP connector EXT CLK (J2). Set the output
power to approximately 6–9 dBm.
NOTE: Do not turn on the RF output of any signal generator at this time.
3.6 Turn On the TSW14J58EVM Power and Connect to the PC
1. Turn on the power switch of the TSW14J58EVM.
2. Connect a mini-USB cable and USB 3 cable from the PC to the TSW14J58EVM.
3. If this is the first time connecting the TSW14J58EVM to the PC, follow the on-screen instructions to
automatically install the device drivers. TSW14J58EVM user's guide for specific instructions.
3.7 Turn On the TSW12QJ1600EVM Power Supplies and Connect to the PC
1. Turn on the 5-V power supply to power up the EVM.
2. Connect the EVM to the PC with the mini-USB cable.
3.8 Turn On the Signal Generator RF Outputs
Turn on the RF signal output of the signal generator connected to INAP. If Ext Ref to ADC PLL clocking
option is used, turn on the RF signal outputs connected to EXT CLK

www.ti.com Open the TSW12QJ1600EVM GUI and Program the ADC and Clocks
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Setup Procedure
3.9 Open the TSW12QJ1600EVM GUI and Program the ADC and Clocks
The Device Configuration GUI is installed separately from the HSDC Pro installation and is a stand-alone
GUI.
Figure 3-2. Configuration GUI EVM Tab

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Setup Procedure
Figure 3-2 and Figure 3-3 show the GUI open to the EVM tab and Control tab respectively. Tabs at the
top of the panel organize the configuration into device and EVM features with user-friendly controls and a
low-level tab for directly configuring the registers. The EVM has two configurable devices, namely the
TSW12QJ1600. The register map for each device is provided in the device data sheet.
1. Open the TSW12QJ1600EVM GUI.
2. Select the "OnBoard 50M Ref to ADC PLL" as the clock source.
3. Select Fs = 1000 MHz MSPS as the onboard Fs selection option from the drop-down menu.
4. Select JMODE8 for the sampling and Calibration mode.
5. Click Program Clocks and ADC (Note: This action overwrites any previous device register settings.)
3.10 Calibrate the ADC Device on the EVM
Figure 3-3. Configuration GUI ADC Control

www.ti.com Open the HSDCpro Software and Load the FPGA Image to the TSW14J58EVM
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Setup Procedure
1. With the EVM GUI open on the PC, navigate to the Control tab.
2. To calibrate the ADC, click Cal Triggered/Running once, then click it again. This stops and re-starts the
Calibration engine.
NOTE: This calibrate button executes a calibration sequence that is required for full performance.
This calibration is performed automatically during the Section 3.9 step but must be
performed again, any time the sampling rate changes, after significant temperature change
of the ADC, or after exiting the power-down mode. See the TSW12QJ1600 device data
sheet, (SBAS960) for details regarding the necessary calibration sequence.
3. To enable background calibration, use the following steps:
• Navigate to the JESD204C tab and click on JESD Block Enable to stop the JESD204C block.
• Navigate back to the Control tab and click on Enable Calibration Block to disable calibration and
allow setting changes.
• Click on Enable Background Cal.
• If background offset calibration is desired also, click on Enable Background Offset Cal.
• Click on Enable Calibration Block to re-enable the calibration subsystem
• Navigate to the JESD204C tab and click on JESD Block Enable to re-start the JESD204C block.
• Navigate back to the Control tab and click the Cal Triggered/Running button once, then click it
again. This restarts the Calibration engine.
4. To disable background calibration, use the following steps:
• Navigate to the JESD204C tab and click on JESD Block Enable to stop the JESD204C block.
• Navigate back to the Control tab and click on Enable Calibration Block to disable calibration and
allow setting changes.
• If background offset calibration was enabled, click on Enable Background Offset Cal to disable the
feature.
• Click on Enable Background Cal to disable the feature.
• Click on Enable Calibration Block to re-enable the calibration subsystem.
• Navigate to the JESD204C tab and click on JESD Block Enable to re-start the JESD204C block.
• Navigate back to the Control tab and click the Cal Triggered/Running button once, then click it
again. This restarts the Calibration engine.
3.11 Open the HSDCpro Software and Load the FPGA Image to the TSW14J58EVM
1. Open the HSDC Pro software.
2. Click OK to confirm the serial number of the TSW14J58EVM device. If multiple TSWxxxxx boards are
connected, select the model and serial number for the one connected to the TSW12QJ1600EVM.
3. Select the ADC12QJ1600RD_JMODE8_12G_16G_divby64 device from the ADC select drop-down
menu in the top left corner.
4. When prompted, click Yes to update the firmware.
NOTE: If the user configures the EVM with options other than the default register values, different
instructions may be required for selecting the device in HSDC Pro. See Appendix B for more
details.
5. Enter the ADC Output Data Rate (ƒ(SAMPLE)) as "1000M" or the desired output sample rate. This number
must be equal to the actual sampling rate of the device and must be updated if the sampling rate
changes.
3.12 Capture Data Using the HSDC Pro Software
The following steps show how to capture data using the HSDC Pro software (see Figure 3-4):
1. Select the test to perform.

Windowing
Select
Channel
Choose Data
Window
CaptureSelect Device
Choose
Test
Check for Coherent
Freq. Auto-Calculate
Select Size of
Analysis Window
Enter Device Output
Data Rate
Enter Target Input
Frequency
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Setup Procedure
2. Select the data view.
3. Select the channel to view.
4. Click the capture button to capture new data.
Additional tips:
• Use the Notch Frequency Bins from the Test Options file menu to remove bins around DC (eliminate
DC noise and offset) or the fundamental (eliminate phase noise from signal generators).
• Open the Capture Option dialog from the Data Capture Options file menu to change the capture depth
or to enable Continuous Capture or FFT averaging.
• For analyzing only a portion of the spectrum, use the Single Tone test with the Bandwidth Integration
Markers from the Test Options file menu. The Channel Power test is also useful.
• For analyzing only a subset of the captured data, set the Analysis Window (samples) setting to a value
less than the number of total samples captured and move the green or red markers in the small
transient data window at the top of the screen to select the data subset of interest.
Figure 3-4. High Speed Data Converter Pro (HSDC) GUI

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Device Configuration
Chapter 4
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Device Configuration
The ADC device is programmable through the serial programming interface (SPI) bus accessible through
the FTDI USB-to-SPI converter located on the EVM. A GUI is provided to write instructions on the bus and
program the registers of the ADC device.
4.1 Supported JESD204C Device Features
The ADC device supports some configuration of the JESD204C interface. Due to limitations in the
TSW14J58EVM firmware, all JESD204C link features of the ADC device are not supported. Table 4-1 lists
the supported and non-supported features.
(1) Dependent on bypass or decimation mode and output rate selection. Always disable the JESD204 block before changing any of
the JESD204C settings. Once the settings are changed, re-enable the JESD204 block.
Table 4-1. Supported and Non-Supported Features of the JESD204C Device
JESD204C Feature Supported by ADC Device Supported by TSW14J58EVM
Number of lanes per link (L) L = 2, 3, 4, 6, 8(1) L = 1, 2, 3, 4, 6, 8 supported
Total number of lanes active 2,,3 4, 6, 8 2, 4, 6, 8, 12, 16
Number of frames per multiframe (K) Kmin = 4–256,(1)
Kmax = 256, Kstep = 4, 16 or 32
Most values of K supported, constrained by
requirement that
K × F = 4n
Scrambling Supported Supported
Encoding 8B/10B and 64B/66B 8B/10B
Test patterns
PRBS7, PRBS9, PRBS15, PBRS23, PRBS31, Ramp,
Transport Layer test, D21.5, K28.5, Repeat ILA,
Modified RPAT, Serial Out 0, Serial Out 1, Clock test,
ADC Test Pattern(1) ILA, Ramp, Long/Short Transport
Speed Lane rates from 0.8 to 17.16 Gbps(1) Lane rates from 12 to 16 Gbps ƒ(SAMPLE) parameter must be properly set in HSDC
Pro GUI.
4.2 Tab Organization
Control of the ADC1 and ADC2 device features are available in the EVM, ADC PLL, Control and
JESD204C tabs for respective ADCs.

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Device Configuration
4.3 Low-Level Control
The Low Level View tab, illustrated in Figure 4-1, allows configuration of the devices at the bit-field level.
At any time, the controls in Table 4-2 can be used to configure or read from the device.
Table 4-2. Low-Level Controls
Control Description
Register map summary Displays the devices on the EVM, registers for those devices, and the states of the registers
• Clicking on a register field allows individual bit manipulation in the register data cluster
• The value column shows the value of the register at the time the GUI was last updated
• The 0-7 column shows the value of the register at the time the register was last read
Write register button Write to the register highlighted in the register map summary with the value in the Write Data field
Write all button Update all registers shown in the register map summary with the values shown in the Register Map
summary
Read register button Read from the register highlighted in the Register Map summary and display the results in the
Read Data field
Can be used to re-synchronize the GUI with the state of the hardware
Read-all button Read from all registers in the Register Map summary and display the current state of the hardware
Load Configuration button Load a configuration file from disk and register address/data values in the file
Save Configuration button Save a configuration file to disk that contains the current state of the configuration registers
Register Data cluster Manipulate individual accessible bits of the register highlighted in the register map summary
Individual register cluster with
read or write register buttons Perform a generic read or write command to the device shown in the Block drop-down box using the address and write data information
Figure 4-1. Low-Level Register Control Tab

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Troubleshooting the TSW12QJ1600EVM
Chapter 5
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Troubleshooting the TSW12QJ1600EVM
Table 5-1 lists some troubleshooting procedures.
Table 5-1. Troubleshooting
Issue Troubleshoot
General problems
• Verify the test setup shown in Figure 3-1, and repeat the setup procedure as described in this
document.
• Check power supply to EVM and TSW14J58EVM. Verify that the power switch is in the on
position.
• Check signal and clock connections to EVM.
• Visually check the top and bottom sides of the board to verify that nothing looks discolored or
damaged.
• Ensure the board-to-board FMC connection is secure.
• Try pressing the CPU_RESET button on the TSW14J58EVM. Also try clicking Instrument
Options →Reset Board after changing the ADC configuration.
• Try power-cycling the external power supply to the EVM, and reprogram the LMK and ADC
devices.
Configuration GUI is not
working properly
• Verify that the USB cable is plugged into the EVM and the PC.
• Check the computer device manager and verify that a USB serial device is recognized when
the EVM is connected to the PC.
• Verify that the green USB Status LED light in the top right corner of the GUI is lit. If it is not lit,
click the Reconnect FTDI button.
• Try restarting the configuration GUI.
Configuration GUI is not
able to connect to the EVM • Use the free FT_PROG software from FTDI chip and verify that the onboard FTDI chip is
programmed with the product description ADC12QJxx00 RD.
HSDC Pro software is not
capturing good data or
analysis results are
incorrect.
• Verify that the TSW14J58EVM is properly connected to the PC with a mini-USB cable and that
the board serial number is properly identified by the HSDC software.
• Check that the proper ADC device mode is selected. The mode should match in HSDC Pro and
the ADC GUI.
• Check that the analysis parameters are properly configured.
HSDC Pro software gives a
time-out error when
capturing data
• Try to reprogram the LMK device and reset the JESD204 link.
• Verify that the ADC sampling rate is correctly set in the HSDC software.
• Try pressing the CPU_RESET button on the TSW14J58EVM. Also try clicking Instrument
Options →Reset Board after changing the ADC configuration. Try to recapture again.
• Select Instrument Options →Download Firmware and download
'TSW14J58_64B66B_12G_16G_REFCLKBY64_IID_28.rbf'. Try to capture again.
Sub-optimal measured
performance
• Try clicking Cal Triggered/Running button 2× to re-calibrate the ADC in the current operating
conditions. It is located on the Control tab of the configuration GUI.
• Check that the spectral analysis parameters are properly configured.
• Verify that bandpass filters are used in the clock and input signal paths and that low-noise
signal sources are used.

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References
Appendix A
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References
This section provides references to technical documents and user's guides.
A.1 Technical Reference Documents
•TSW14J58EVM user’s guide
•High-Speed Data Converter Pro GUI User's Guide, also available in the help menu of the software
• FTDI USB to Serial Driver Installation Manual
(www.ftdichip.com/Support/Documents/InstallGuides.htm)
A.2 TSW14J58EVM Operation
See the TSW14J58EVM user guide for configuration and status information.

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HSDC Pro Settings for Optional ADC Device Configuration
Appendix B
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HSDC Pro Settings for Optional ADC Device Configuration
This appendix provides settings for optional ADC device configuration in HSDC Pro.
B.1 Changing the Number of Frames per Multi-Frame (K)
Changing the number of frames per multi-frame output by the JESD204 transmitter (ADC device) is
configured using the K parameter( when using modes with 8B/10B encoding) on the JESD204C tab in the
Configuration GUI. This parameter must be matched by the receiving device, and the SYSREF frequency
must also be programmed to a compatible frequency. Ensure that the K value complies with the K Min
and Step values for the selected JMODE. Refer to the TSW12QJ1600 operating modes table in the device
datasheet..
B.2 Customizing the EVM for Optional Clocking Support
The TSW12QJ1600EVM can be clocked using two different methods:
1. Onboard 50M ref to ADC PLL clocking option
2. Ext Ref to ADC PLL clocking
B.2.1 Onboard 50M Ref to ADC PLL (Default)
The 50-MHz onboard crystal oscillator is use provide reference signal to ADC's single-ended clock input.
The ADC PLL generate a sampling clock for the ADC from this 50 MHz. In this clocking mode, the ADC
also generates the reference clock signal for FPGA. FPGA takes this reference clock and generates the
SYSREF signal for the ADC and feeds it back to the ADC. Figure B-1 shows the block diagram of the
Onboard 50M Ref to ADC PLL clocking option:
No hardware change is need to use this mode.

DA[15:0]
SYNC
FPGA_GBT_CLK
ADC_SYSREF
TSW12QJ1600
CLK
SYSREF
DA[15:0]
FMC+
SYNC
TRIGOUT
FPGA_CLKPLLREFO
50MHz
VCXO SE_CLK
J2
EXT CLK
(50-500MHz)
DA[15:0]
SYNC
FPGA_GBT_CLK
ADC_SYSREF
TSW12QJ1600
CLK
SYSREF
DA[15:0]
FMC+
SYNC
TRIGOUT
FPGA_CLKPLLREFO
50MHz
VCXO SE_CLK
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HSDC Pro Settings for Optional ADC Device Configuration
Figure B-1. Onboard 50M Ref to ADC PLL System Block Diagram
B.2.2 "Ext Ref to ADC PLL"
The reference signal for the ADC PLL is provided externally from External signal generator on SMP
labeled EXT CLK(J2) . The sampling clock is generate by ADC PLL, from this external provided PLL
reference signal. In this clocking mode ADC also generate the reference clock signal for FPGA. FPGA
takes this reference clock and generates the SYSREF signal for the ADC and feed it back to the ADC.
Figure B-2 shows the block diagram of Ext Ref to ADC PLL clocking option:
• Remove R231, and populate C27.
Figure B-2. Ext Ref to ADC PLL System Block Diagram