Texas Instruments DM648 DSP User manual

TMS320DM647/DM648 DSPDDR2 Memory Controller
User's Guide
Literature Number: SPRUEK5A
October 2007

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Contents
Preface ............................................................................................................................... 61 Introduction ................................................................................................................ 91.1 Purpose of the Peripheral ....................................................................................... 91.2 Features ........................................................................................................... 91.3 Functional Block Diagram ....................................................................................... 91.4 Industry Standard(s) Compliance Statement ............................................................... 102 Peripheral Architecture .............................................................................................. 112.1 Clock Control .................................................................................................... 112.2 Memory Map .................................................................................................... 112.3 Signal Descriptions ............................................................................................. 112.4 Protocol Description(s) ......................................................................................... 132.5 Memory Width and Byte Alignment .......................................................................... 182.6 Address Mapping ............................................................................................... 192.7 DDR2 Memory Controller Interface .......................................................................... 222.8 Refresh Scheduling ............................................................................................ 252.9 Self-Refresh Mode.............................................................................................. 262.10 Reset Considerations .......................................................................................... 262.11 DDR2 SDRAM Memory Initialization ......................................................................... 272.12 Interrupt Support ................................................................................................ 282.13 EDMA Event Support .......................................................................................... 282.14 Emulation Considerations ..................................................................................... 283 Using the DDR2 Memory Controller ............................................................................. 293.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM ............................................. 293.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications ............. 334 DDR2 Memory Controller Registers ............................................................................. 364.1 Module ID and Revision Register (MIDR) ................................................................... 374.2 DDR2 Memory Controller Status Register (DMCSTAT) ................................................... 374.3 SDRAM Configuration Register (SDCFG) ................................................................... 384.4 SDRAM Refresh Control Register (SDRFC) ................................................................ 404.5 SDRAM Timing 1 Register (SDTIM1) ........................................................................ 414.6 SDRAM Timing 2 Register (SDTIM2) ........................................................................ 434.7 Burst Priority Register (BPRIO) ............................................................................... 444.8 DDR2 Memory Controller Control Register (DMCCTL) ................................................... 45Appendix A Revision History ............................................................................................. 46
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List of Figures
1 DDR2 Memory Controller Block Diagram ............................................................................... 102 DDR2 Memory Controller Signals ........................................................................................ 123 DDR2 MRS and EMRS Command ...................................................................................... 144 Refresh Command ......................................................................................................... 155 ACTV Command ........................................................................................................... 156 DCAB Command ........................................................................................................... 167 DEAC Command ........................................................................................................... 168 DDR2 READ Command ................................................................................................... 179 DDR2 WRT Command .................................................................................................... 1810 Byte Alignment .............................................................................................................. 1911 Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM ............................................... 1912 Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM ................................................ 2013 Logical Address-to-DDR2 SDRAM Address Map ...................................................................... 2114 DDR2 SDRAM Column, Row, and Bank Access ...................................................................... 2215 DDR2 Memory Controller FIFO Block Diagram ........................................................................ 2316 DDR2 Memory Controller Reset Block Diagram ....................................................................... 2617 Connecting to Two 16-Bit DDR2 SDRAM Devices .................................................................... 3018 Connecting to a Single 16-Bit DDR2 SDRAM Device ................................................................. 3119 Connecting to Two 8-Bit DDR2 SDRAM Devices ...................................................................... 3220 Module ID and Revision Register (MIDR) ............................................................................... 3721 DDR2 Memory Controller Status Register (DMCSTAT) .............................................................. 3722 SDRAM Configuration Register (SDCFG) .............................................................................. 3823 SDRAM Refresh Control Register (SDRFC)............................................................................ 4024 SDRAM Timing 1 Register (SDTIM1) ................................................................................... 4125 SDRAM Timing 2 Register (SDTIM2) ................................................................................... 4326 Burst Priority Register (BPRIO) .......................................................................................... 4427 DDR2 Memory Controller Control Register (DMCCTL) ............................................................... 45
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List of Tables
1 DDR2 Memory Controller Signal Descriptions ......................................................................... 122 DDR2 SDRAM Commands ............................................................................................... 133 Truth Table for DDR2 SDRAM Commands ............................................................................ 134 Addressable Memory Ranges ............................................................................................ 185 Bank Configuration Register Fields for Address Mapping ............................................................ 196 DDR2 Memory Controller FIFO Description ............................................................................ 227 Refresh Urgency Levels ................................................................................................... 258 Reset Sources .............................................................................................................. 269 DDR2 SDRAM Mode Register Configuration ........................................................................... 2710 DDR2 SDRAM Extended Mode Register 1 Configuration ............................................................ 2711 SDCFG Configuration ..................................................................................................... 3312 DDR2 Memory Refresh Specification ................................................................................... 3413 SDRFC Configuration ...................................................................................................... 3414 SDTIM1 Configuration ..................................................................................................... 3415 SDTIM2 Configuration ..................................................................................................... 3516 DMCCTL Configuration .................................................................................................... 3517 DDR2 Memory Controller Registers ..................................................................................... 3618 Module ID and Revision Register (MIDR) Field Descriptions ........................................................ 3719 DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions ........................................ 3720 SDRAM Configuration Register (SDCFG) Field Descriptions ........................................................ 3821 SDRAM Refresh Control Register (SDRFC) Field Descriptions ..................................................... 4022 SDRAM Timing 1 Register (SDTIM1) Field Descriptions ............................................................. 4123 SDRAM Timing 2 Register (SDTIM2) Field Descriptions ............................................................. 4324 Burst Priority Register (BPRIO) Field Descriptions .................................................................... 4425 DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions ......................................... 45A-1 Document Revision History ............................................................................................... 46
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PrefaceSPRUEK5A – October 2007
Read This First
About This Manual
This document describes the DDR2 memory controller in the TMS320DM647/DM648 Digital SignalProcessor (DSP).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Note: Acronyms 3PSW, CPSW, CPSW_3G, and 3pGSw are interchangeable and all refer to the 3port gigabit switch.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM647/DM648 Digital Signal Processor (DSP). Copies ofthese documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com .
SPRS372 —TMS320DM647/DM648 Digital Media Processor Data Manual describes the signals,specifications and electrical characteristics of the device.
SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.
SPRUEK5 —TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide describes the DDR2memory controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The DDR2/mDDRmemory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAMdevices and standard Mobile DDR SDRAM devices.
SPRUEK6 —TMS320DM647/DM648 DSP External Memory Interface (EMIF) User's Guide describesthe operation of the asynchronous external memory interface (EMIF) in the TMS320DM647/DM648Digital Signal Processor (DSP). The EMIF supports a glueless interface to a variety of externaldevices.
SPRUEK7 —TMS320DM647/DM648 DSP General-Purpose Input/Output (GPIO) User's Guidedescribes the general-purpose input/output (GPIO) peripheral in the TMS320DM647/DM648 DigitalSignal Processor (DSP). The GPIO peripheral provides dedicated general-purpose pins that can beconfigured as either inputs or outputs. When configured as an input, you can detect the state of theinput by reading the state of an internal register. When configured as an output, you can write to aninternal register to control the state driven on the output pin.
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Related Documentation From Texas Instruments
SPRUEK8 —TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guidedescribes the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital SignalProcessor (DSP). The I2C peripheral provides an interface between the DSP and other devicescompliant with the I2C-bus specification and connected by way of an I2C-bus. External componentsattached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and from theDSP through the I2C peripheral. This document assumes the reader is familiar with the I2C-busspecification.
SPRUEL0 —TMS320DM647/DM648 DSP 64-Bit Timer User's Guide describes the operation of the64-bit timer in the TMS320DM647/DM648 Digital Signal Processor (DSP). The timer can beconfigured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdogtimer.
SPRUEL1 —TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guidedescribes the multichannel audio serial port (McASP) in the TMS320DM647/DM648 Digital SignalProcessor (DSP). The McASP functions as a general-purpose audio serial port optimized for theneeds of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interfacetransmission (DIT).
SPRUEL2 —TMS320DM647/DM648 DSP Enhanced DMA (EDMA) Controller User's Guide describesthe operation of the enhanced direct memory access (EDMA3) controller in theTMS320DM647/DM648 Digital Signal Processor (DSP). The EDMA3 controller’s primary purpose isto service user-programmed data transfers between two memory-mapped slave endpoints on theDSP.
SPRUEL4 —TMS320DM647/DM648 DSP Peripheral Component Interconnect (PCI) User's Guidedescribes the peripheral component interconnect (PCI) port in the TMS320DM647/DM648 DigitalSignal Processor (DSP). The PCI port supports connection of the C642x DSP to a PCI host via theintegrated PCI master/slave bus interface. The PCI port interfaces to the DSP via the enhancedDMA (EDMA) controller. This architecture allows for both PCI master and slave transactions, whilekeeping the EDMA channel resources available for other applications.
SPRUEL5 —TMS320DM647/DM648 DSP Host Port Interface (UHPI) User's Guide describes the hostport interface (HPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The HPI is aparallel port through which a host processor can directly access the CPU memory space. The hostdevice functions as a master to the interface, which increases ease of access. The host and CPUcan exchange information via internal or external memory. The host also has direct access tomemory-mapped peripherals. Connectivity to the CPU memory space is provided through theenhanced direct memory access (EDMA) controller.
SPRUEL8 —TMS320DM647/DM648 DSP Universal Asynchronous Receiver/Transmitter (UART)User's Guide describes the universal asynchronous receiver/transmitter (UART) peripheral in theTMS320DM647/DM648 Digital Signal Processor (DSP). The UART peripheral performsserial-to-parallel conversion on data received from a peripheral device, and parallel-to-serialconversion on data received from the CPU.
SPRUEL9 —TMS320DM647/DM648 DSP VLYNQ Port User's Guide describes the VLYNQ port in theTMS320DM647/DM648 Digital Signal Processor (DSP). The VLYNQ port is a high-speedpoint-to-point serial interface for connecting to host processors and other VLYNQ compatibledevices. It is a full-duplex serial bus where transmit and receive operations occur separately andsimultaneously without interference.
SPRUEM1 —TMS320DM647/DM648 DSP Video Port/VCXO Interpolated Control (VIC) Port User'sGuide discusses the video port and VCXO interpolated control (VIC) port in theTMS320DM647/DM648 Digital Signal Processor (DSP). The video port can operate as a videocapture port, video display port, or transport channel interface (TCI) capture port. The VIC portprovides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. When thevideo port is used in TCI mode, the VIC port is used to control the system clock, VCXO, for MPEGtransport channel.
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Related Documentation From Texas Instruments
SPRUEM2 —TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the SerialPort Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This referenceguide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface.The SPI is a programmable-length shift register, used for high speed communication betweenexternal peripherals or other DSPs.
SPRUEU6 — TMS320DM647/DM648 DSP Subsystem User's Guide describes the subsystem in theTMS320DM647/DM648 Digital Signal Processor (DSP). The subsystem is responsible forperforming digital signal processing for digital media applications. The subsystem acts as theoverall system controller, responsible for handling many system functions such as system-levelinitialization, configuration, user interface, user command execution, connectivity functions, andoverall system control.
SPRUF57 — TMS320DM647/DM648 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guidedescribes the operation of the 3 port switch (3PSW) ethernet subsystem in theTMS320DM647/DM648 Digital Signal Processor (DSP). The 3 port switch gigabit ethernetsubsystem provides ethernet packet communication and can be configured as an ethernet switch(DM648 only). It provides the serial gigabit media independent interface (SGMII), the managementdata input output (MDIO) for physical layer device (PHY) management.Trademarks
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1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
1.3 Functional Block Diagram
User's GuideSPRUEK5A – October 2007
DSP DDR2 Memory Controller
This document describes the DDR2 memory controller in the device.
The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAMdevices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memoriesare not supported. The DDR2 memory controller SDRAM can be used for program and data storage.
The DDR2 memory controller supports the following features:•JESD79D-2A standard compliant DDR2 SDRAM•256 Mbyte memory space•Data bus width of 32 or 16 bits•CAS latencies: 2, 3, 4, and 5•Internal banks: 1, 2, 4, and 8•Burst length: 8•Burst type: sequential•1 CE signal•Page sizes: 256, 512, 1024, and 2048•SDRAM auto-initialization
•Self-refresh mode•Prioritized refresh•Programmable refresh rate and backlog counter•Programmable timing parameters
The DDR2 memory controller is the main interface to external DDR2 memory (see Figure 1 ). Masterperipherals, such as the EDMA controller and the CPU can access the DDR2 memory controller throughthe switched central resource (SCR). The DDR2 memory controller performs all memory-relatedbackground tasks such as opening and closing banks, refreshes, and command arbitration.
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L1 S1 M1 D1
Data path A
Register file A Register file B
D2
Data path B
S2M2 L2
L1 data memory controller
Cache control
Memory protection
Interrupt
and exception
controller
Power control
Instruction decode
16/32−bit instruction dispatch
Instruction fetch
SPLOOP buffer
C64x+ CPU
IDMA
Bandwidth management
Cache control
L1 program memory controller Advanced
event
triggering
(AET)
L2 memory
controller
Bandwidth
management
Memory
protection
registers
Configuration
L1P
cache/SRAM
L1D
cache/SRAM
PLL2
DDR2 memory
EMIFA
Other
peripherals
EDMA
Boot
configuration
Switched central resource
PLL2
L2 memory
controller
controller
memory
External
controller
DMA
Master
DMA
Slave
Cache
control
Bandwidth management
Memory protection
1.4 Industry Standard(s) Compliance Statement
Introduction
Figure 1. DDR2 Memory Controller Block Diagram
The DDR2 memory controller is compliant with the JESD79D-2A DDR2 SDRAM standard with theexception of the On Die Termination (ODT) feature. The DSP does not include any on-die terminatingresistors. Furthermore, the on-die terminating resistors of the DDR2 SDRAM device must be disabled bytying the ODT input pin of the DDR2 SDRAM memory to ground.
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