Texas Instruments DM648 DSP User manual

TMS320DM647/DM648 DSPDDR2 Memory Controller
User's Guide
Literature Number: SPRUEK5A
October 2007

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Contents
Preface ............................................................................................................................... 61 Introduction ................................................................................................................ 91.1 Purpose of the Peripheral ....................................................................................... 91.2 Features ........................................................................................................... 91.3 Functional Block Diagram ....................................................................................... 91.4 Industry Standard(s) Compliance Statement ............................................................... 102 Peripheral Architecture .............................................................................................. 112.1 Clock Control .................................................................................................... 112.2 Memory Map .................................................................................................... 112.3 Signal Descriptions ............................................................................................. 112.4 Protocol Description(s) ......................................................................................... 132.5 Memory Width and Byte Alignment .......................................................................... 182.6 Address Mapping ............................................................................................... 192.7 DDR2 Memory Controller Interface .......................................................................... 222.8 Refresh Scheduling ............................................................................................ 252.9 Self-Refresh Mode.............................................................................................. 262.10 Reset Considerations .......................................................................................... 262.11 DDR2 SDRAM Memory Initialization ......................................................................... 272.12 Interrupt Support ................................................................................................ 282.13 EDMA Event Support .......................................................................................... 282.14 Emulation Considerations ..................................................................................... 283 Using the DDR2 Memory Controller ............................................................................. 293.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM ............................................. 293.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications ............. 334 DDR2 Memory Controller Registers ............................................................................. 364.1 Module ID and Revision Register (MIDR) ................................................................... 374.2 DDR2 Memory Controller Status Register (DMCSTAT) ................................................... 374.3 SDRAM Configuration Register (SDCFG) ................................................................... 384.4 SDRAM Refresh Control Register (SDRFC) ................................................................ 404.5 SDRAM Timing 1 Register (SDTIM1) ........................................................................ 414.6 SDRAM Timing 2 Register (SDTIM2) ........................................................................ 434.7 Burst Priority Register (BPRIO) ............................................................................... 444.8 DDR2 Memory Controller Control Register (DMCCTL) ................................................... 45Appendix A Revision History ............................................................................................. 46
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List of Figures
1 DDR2 Memory Controller Block Diagram ............................................................................... 102 DDR2 Memory Controller Signals ........................................................................................ 123 DDR2 MRS and EMRS Command ...................................................................................... 144 Refresh Command ......................................................................................................... 155 ACTV Command ........................................................................................................... 156 DCAB Command ........................................................................................................... 167 DEAC Command ........................................................................................................... 168 DDR2 READ Command ................................................................................................... 179 DDR2 WRT Command .................................................................................................... 1810 Byte Alignment .............................................................................................................. 1911 Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM ............................................... 1912 Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM ................................................ 2013 Logical Address-to-DDR2 SDRAM Address Map ...................................................................... 2114 DDR2 SDRAM Column, Row, and Bank Access ...................................................................... 2215 DDR2 Memory Controller FIFO Block Diagram ........................................................................ 2316 DDR2 Memory Controller Reset Block Diagram ....................................................................... 2617 Connecting to Two 16-Bit DDR2 SDRAM Devices .................................................................... 3018 Connecting to a Single 16-Bit DDR2 SDRAM Device ................................................................. 3119 Connecting to Two 8-Bit DDR2 SDRAM Devices ...................................................................... 3220 Module ID and Revision Register (MIDR) ............................................................................... 3721 DDR2 Memory Controller Status Register (DMCSTAT) .............................................................. 3722 SDRAM Configuration Register (SDCFG) .............................................................................. 3823 SDRAM Refresh Control Register (SDRFC)............................................................................ 4024 SDRAM Timing 1 Register (SDTIM1) ................................................................................... 4125 SDRAM Timing 2 Register (SDTIM2) ................................................................................... 4326 Burst Priority Register (BPRIO) .......................................................................................... 4427 DDR2 Memory Controller Control Register (DMCCTL) ............................................................... 45
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List of Tables
1 DDR2 Memory Controller Signal Descriptions ......................................................................... 122 DDR2 SDRAM Commands ............................................................................................... 133 Truth Table for DDR2 SDRAM Commands ............................................................................ 134 Addressable Memory Ranges ............................................................................................ 185 Bank Configuration Register Fields for Address Mapping ............................................................ 196 DDR2 Memory Controller FIFO Description ............................................................................ 227 Refresh Urgency Levels ................................................................................................... 258 Reset Sources .............................................................................................................. 269 DDR2 SDRAM Mode Register Configuration ........................................................................... 2710 DDR2 SDRAM Extended Mode Register 1 Configuration ............................................................ 2711 SDCFG Configuration ..................................................................................................... 3312 DDR2 Memory Refresh Specification ................................................................................... 3413 SDRFC Configuration ...................................................................................................... 3414 SDTIM1 Configuration ..................................................................................................... 3415 SDTIM2 Configuration ..................................................................................................... 3516 DMCCTL Configuration .................................................................................................... 3517 DDR2 Memory Controller Registers ..................................................................................... 3618 Module ID and Revision Register (MIDR) Field Descriptions ........................................................ 3719 DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions ........................................ 3720 SDRAM Configuration Register (SDCFG) Field Descriptions ........................................................ 3821 SDRAM Refresh Control Register (SDRFC) Field Descriptions ..................................................... 4022 SDRAM Timing 1 Register (SDTIM1) Field Descriptions ............................................................. 4123 SDRAM Timing 2 Register (SDTIM2) Field Descriptions ............................................................. 4324 Burst Priority Register (BPRIO) Field Descriptions .................................................................... 4425 DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions ......................................... 45A-1 Document Revision History ............................................................................................... 46
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PrefaceSPRUEK5A – October 2007
Read This First
About This Manual
This document describes the DDR2 memory controller in the TMS320DM647/DM648 Digital SignalProcessor (DSP).
Notational Conventions
This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.
Note: Acronyms 3PSW, CPSW, CPSW_3G, and 3pGSw are interchangeable and all refer to the 3port gigabit switch.
Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM647/DM648 Digital Signal Processor (DSP). Copies ofthese documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com .
SPRS372 —TMS320DM647/DM648 Digital Media Processor Data Manual describes the signals,specifications and electrical characteristics of the device.
SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.
SPRUEK5 —TMS320DM647/DM648 DSP DDR2 Memory Controller User's Guide describes the DDR2memory controller in the TMS320DM647/DM648 Digital Signal Processor (DSP). The DDR2/mDDRmemory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAMdevices and standard Mobile DDR SDRAM devices.
SPRUEK6 —TMS320DM647/DM648 DSP External Memory Interface (EMIF) User's Guide describesthe operation of the asynchronous external memory interface (EMIF) in the TMS320DM647/DM648Digital Signal Processor (DSP). The EMIF supports a glueless interface to a variety of externaldevices.
SPRUEK7 —TMS320DM647/DM648 DSP General-Purpose Input/Output (GPIO) User's Guidedescribes the general-purpose input/output (GPIO) peripheral in the TMS320DM647/DM648 DigitalSignal Processor (DSP). The GPIO peripheral provides dedicated general-purpose pins that can beconfigured as either inputs or outputs. When configured as an input, you can detect the state of theinput by reading the state of an internal register. When configured as an output, you can write to aninternal register to control the state driven on the output pin.
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Related Documentation From Texas Instruments
SPRUEK8 —TMS320DM647/DM648 DSP Inter-Integrated Circuit (I2C) Module User's Guidedescribes the inter-integrated circuit (I2C) peripheral in the TMS320DM647/DM648 Digital SignalProcessor (DSP). The I2C peripheral provides an interface between the DSP and other devicescompliant with the I2C-bus specification and connected by way of an I2C-bus. External componentsattached to this 2-wire serial bus can transmit and receive up to 8-bit wide data to and from theDSP through the I2C peripheral. This document assumes the reader is familiar with the I2C-busspecification.
SPRUEL0 —TMS320DM647/DM648 DSP 64-Bit Timer User's Guide describes the operation of the64-bit timer in the TMS320DM647/DM648 Digital Signal Processor (DSP). The timer can beconfigured as a general-purpose 64-bit timer, dual general-purpose 32-bit timers, or a watchdogtimer.
SPRUEL1 —TMS320DM647/DM648 DSP Multichannel Audio Serial Port (McASP) User's Guidedescribes the multichannel audio serial port (McASP) in the TMS320DM647/DM648 Digital SignalProcessor (DSP). The McASP functions as a general-purpose audio serial port optimized for theneeds of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interfacetransmission (DIT).
SPRUEL2 —TMS320DM647/DM648 DSP Enhanced DMA (EDMA) Controller User's Guide describesthe operation of the enhanced direct memory access (EDMA3) controller in theTMS320DM647/DM648 Digital Signal Processor (DSP). The EDMA3 controller’s primary purpose isto service user-programmed data transfers between two memory-mapped slave endpoints on theDSP.
SPRUEL4 —TMS320DM647/DM648 DSP Peripheral Component Interconnect (PCI) User's Guidedescribes the peripheral component interconnect (PCI) port in the TMS320DM647/DM648 DigitalSignal Processor (DSP). The PCI port supports connection of the C642x DSP to a PCI host via theintegrated PCI master/slave bus interface. The PCI port interfaces to the DSP via the enhancedDMA (EDMA) controller. This architecture allows for both PCI master and slave transactions, whilekeeping the EDMA channel resources available for other applications.
SPRUEL5 —TMS320DM647/DM648 DSP Host Port Interface (UHPI) User's Guide describes the hostport interface (HPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). The HPI is aparallel port through which a host processor can directly access the CPU memory space. The hostdevice functions as a master to the interface, which increases ease of access. The host and CPUcan exchange information via internal or external memory. The host also has direct access tomemory-mapped peripherals. Connectivity to the CPU memory space is provided through theenhanced direct memory access (EDMA) controller.
SPRUEL8 —TMS320DM647/DM648 DSP Universal Asynchronous Receiver/Transmitter (UART)User's Guide describes the universal asynchronous receiver/transmitter (UART) peripheral in theTMS320DM647/DM648 Digital Signal Processor (DSP). The UART peripheral performsserial-to-parallel conversion on data received from a peripheral device, and parallel-to-serialconversion on data received from the CPU.
SPRUEL9 —TMS320DM647/DM648 DSP VLYNQ Port User's Guide describes the VLYNQ port in theTMS320DM647/DM648 Digital Signal Processor (DSP). The VLYNQ port is a high-speedpoint-to-point serial interface for connecting to host processors and other VLYNQ compatibledevices. It is a full-duplex serial bus where transmit and receive operations occur separately andsimultaneously without interference.
SPRUEM1 —TMS320DM647/DM648 DSP Video Port/VCXO Interpolated Control (VIC) Port User'sGuide discusses the video port and VCXO interpolated control (VIC) port in theTMS320DM647/DM648 Digital Signal Processor (DSP). The video port can operate as a videocapture port, video display port, or transport channel interface (TCI) capture port. The VIC portprovides single-bit interpolated VCXO control with resolution from 9 bits to up to 16 bits. When thevideo port is used in TCI mode, the VIC port is used to control the system clock, VCXO, for MPEGtransport channel.
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Related Documentation From Texas Instruments
SPRUEM2 —TMS320DM647/DM648 DSP Serial Port Interface (SPI) User's Guide discusses the SerialPort Interface (SPI) in the TMS320DM647/DM648 Digital Signal Processor (DSP). This referenceguide provides the specifications for a 16-bit configurable, synchronous serial peripheral interface.The SPI is a programmable-length shift register, used for high speed communication betweenexternal peripherals or other DSPs.
SPRUEU6 — TMS320DM647/DM648 DSP Subsystem User's Guide describes the subsystem in theTMS320DM647/DM648 Digital Signal Processor (DSP). The subsystem is responsible forperforming digital signal processing for digital media applications. The subsystem acts as theoverall system controller, responsible for handling many system functions such as system-levelinitialization, configuration, user interface, user command execution, connectivity functions, andoverall system control.
SPRUF57 — TMS320DM647/DM648 DSP 3 Port Switch (3PSW) Ethernet Subsystem User's Guidedescribes the operation of the 3 port switch (3PSW) ethernet subsystem in theTMS320DM647/DM648 Digital Signal Processor (DSP). The 3 port switch gigabit ethernetsubsystem provides ethernet packet communication and can be configured as an ethernet switch(DM648 only). It provides the serial gigabit media independent interface (SGMII), the managementdata input output (MDIO) for physical layer device (PHY) management.Trademarks
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1 Introduction
1.1 Purpose of the Peripheral
1.2 Features
1.3 Functional Block Diagram
User's GuideSPRUEK5A – October 2007
DSP DDR2 Memory Controller
This document describes the DDR2 memory controller in the device.
The DDR2 memory controller is used to interface with JESD79D-2A standard compliant DDR2 SDRAMdevices. Memory types such as DDR1 SDRAM, SDR SDRAM, SBSRAM, and asynchronous memoriesare not supported. The DDR2 memory controller SDRAM can be used for program and data storage.
The DDR2 memory controller supports the following features:•JESD79D-2A standard compliant DDR2 SDRAM•256 Mbyte memory space•Data bus width of 32 or 16 bits•CAS latencies: 2, 3, 4, and 5•Internal banks: 1, 2, 4, and 8•Burst length: 8•Burst type: sequential•1 CE signal•Page sizes: 256, 512, 1024, and 2048•SDRAM auto-initialization
•Self-refresh mode•Prioritized refresh•Programmable refresh rate and backlog counter•Programmable timing parameters
The DDR2 memory controller is the main interface to external DDR2 memory (see Figure 1 ). Masterperipherals, such as the EDMA controller and the CPU can access the DDR2 memory controller throughthe switched central resource (SCR). The DDR2 memory controller performs all memory-relatedbackground tasks such as opening and closing banks, refreshes, and command arbitration.
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L1 S1 M1 D1
Data path A
Register file A Register file B
D2
Data path B
S2M2 L2
L1 data memory controller
Cache control
Memory protection
Interrupt
and exception
controller
Power control
Instruction decode
16/32−bit instruction dispatch
Instruction fetch
SPLOOP buffer
C64x+ CPU
IDMA
Bandwidth management
Cache control
L1 program memory controller Advanced
event
triggering
(AET)
L2 memory
controller
Bandwidth
management
Memory
protection
registers
Configuration
L1P
cache/SRAM
L1D
cache/SRAM
PLL2
DDR2 memory
EMIFA
Other
peripherals
EDMA
Boot
configuration
Switched central resource
PLL2
L2 memory
controller
controller
memory
External
controller
DMA
Master
DMA
Slave
Cache
control
Bandwidth management
Memory protection
1.4 Industry Standard(s) Compliance Statement
Introduction
Figure 1. DDR2 Memory Controller Block Diagram
The DDR2 memory controller is compliant with the JESD79D-2A DDR2 SDRAM standard with theexception of the On Die Termination (ODT) feature. The DSP does not include any on-die terminatingresistors. Furthermore, the on-die terminating resistors of the DDR2 SDRAM device must be disabled bytying the ODT input pin of the DDR2 SDRAM memory to ground.
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2 Peripheral Architecture
2.1 Clock Control
2.2 Memory Map
2.3 Signal Descriptions
Peripheral Architecture
The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices andsupports such features as self-refresh mode and prioritized refresh. In addition, it provides flexibilitythrough programmable parameters such as the refresh rate, CAS latency, and many SDRAM timingparameters.
The following sections describe the architecture of the DDR2 memory controller as well as how tointerface and configure it to perform read and write operations to DDR2 SDRAM devices. Also, Section 3provides a detailed example of interfacing the DDR2 memory controller to a common DDR2 SDRAMdevice.
The DDR2 memory controller is clocked directly from the output of the second phase-locked loop (PLL2)of the device. The PLL2 multiplies its input clock by 20. This clock is divided by 2 to generate DDR_CLK.The frequency of DDR_CLK can be determined by using the following formula:
DDR_CLK frequency = (PLL2 input clock frequency ×20)/2 = PLL2 input clock frequency ×10
The second output clock of the DDR2 memory controller, DDR_CLK, is the inverse of DDR_CLK. Formore information on the PLL2, see the device-specific data manual.
Please see the device-specific data manual for information describing the device memory map.
The DDR2 memory controller signals are shown in Figure 2 and described in Table 1 . The followingfeatures are included:
•The maximum width for the data bus (DDR_D[31:0]) is 32-bits.•The address bus (DDR_A[13:0]) is 14-bits wide with an additional 3 bank address pins (DDR_BA[2:0]).•Two differential output clocks (DDR_CLK and DDR_CLK) driven by internal clock sources.•Command signals: Row and column address strobe ( DDR_RAS and DDR_CAS), write enable strobe( DDR_WE), data strobe (DDR_DQS[3:0] and DDR_DQS[3:0]), and data mask ( DDR_DQM[3:0]).•One chip select signal ( DDR_CS) and one clock enable signal (DDR_CKE).•Two on-die termination output signals (DDR_ODT[1:0]).
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DDR_D[31:0]
DDR2
memory
controller
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_DQS[3:0]
DDR_A[13:0]
DDR_VREF
DDR_DQGATE[3:0]
DDR_DQS[3:0]
DDR_ODT[1:0]
Peripheral Architecture
Figure 2. DDR2 Memory Controller Signals
Table 1. DDR2 Memory Controller Signal Descriptions
Pin Description
DDR_D[31:0] Bidirectional data bus. Input for data reads and output for data writes.DDR_A[13:0] External address output.DDR_CS Active-low chip enable for memory space CE0. DDR_CS is used to enable the DDR2 SDRAM memorydevice during external memory accesses. DDR_CS pin stays low throughout the operation of the DDR2memory controller; it never goes high. Note that this behavior does not affect the ability of the DDR2 memorycontroller to access DDR2 SDRAM memory devices.DDR_DQM[3:0] Active-low output data mask.DDR_CLK/ Differential clock outputs.DDR_CLK
DDR_CKE Clock enable (used for self-refresh mode).DDR_CAS Active-low column address strobe.DDR_RAS Active-low row address strobe.DDR_WE Active-low write enable.DDR_DQS[3:0]/ Differential data strobe bidirectional signals.DDR_DQS[3:0]
DDR_ODT[1:0] On-die termination signals to external DDR2 SDRAM. These pins are reserved for future use and should notbe connected to the DDR2 SDRAM. Note: there are no on-die termination resistors implemented on the dieof this device.DDR_BA[2:0] Bank-address control outputs.DDR_DQGATE[3:0] Data strobe gate pins. These pins are used as a timing reference during memory reads. TheDDR_DQGATE0 and DDR_DQGATE2 pins should be routed out and connected to the DDR_DQGATE1 andDDR_DQGATE3 pins, respectively. For more routing requirements on these pins, see the device-specificdata manual.DDR_VREF DDR2 Memory Controller reference voltage. This voltage must be supplied externally. See thedevice-specific data manual for more details.
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2.4 Protocol Description(s)
Peripheral Architecture
The DDR2 memory controller supports the DDR2 SDRAM commands listed in Table 2 .Table 3 shows thesignal truth table for the DDR2 SDRAM commands.
Table 2. DDR2 SDRAM Commands
Command Function
ACTV Activates the selected bank and row.DCAB Precharge all command. Deactivates (precharges) all banks.DEAC Precharge single command. Deactivates (precharges) a single bank.DESEL Device Deselect.EMRS Extended Mode Register set. Allows altering the contents of the mode register.MRS Mode register set. Allows altering the contents of the mode register.NOP No operation.Power Down Power down mode.READ Inputs the starting column address and begins the read operation.READ with Inputs the starting column address and begins the read operation. The read operation is followed by aautoprecharge precharge.REFR Autorefresh cycle.SLFREFR Self-refresh mode.WRT Inputs the starting column address and begins the write operation.WRT with Inputs the starting column address and begins the write operation. The write operation is followed by aautoprecharge precharge.
Table 3. Truth Table for DDR2 SDRAM CommandsDDR2 SDRAM
Signals CKE CS RAS CAS WE BA[2:0] A[13:11, 9:0] A10
DDR_CKE
DDR2 Memory Previous DDR_BA[2:0Controller Signals Cycles Current Cycle DDR_CS DDR_RAS DDR_CAS DDR_WE ] DDR_A[13:11, 9:0] DDR_A[10]
ACTV H
(1)
H L L H H Bank Row Address
DCAB H H L L H L X X L
DEAC H H L L H L Bank X L
MRS H H L L L L BA
(2)
OP Code
EMRS H H L L L L BA OP Code
READ H H L H L H BA Column Address L
READ with H H L H L H BA Column Address Hprecharge
WRT H H L H L L BA Column Address L
WRT with precharge H H L H L L BA Column Address L
REFR H H L L L H X X X
SLFREFR H L L L L H X X Xentry
SLFREFR L H H X X X X X Xexit
L H H H X X X
NOP H X L H H H X X X
DESEL H X H X X X X X X
Power Down entry H L H X X X X X X
L H H H X X X
Power Down exit L H H X X X X X X
L H H H X X X(1)
Legend: H means logic high; L means logic low; X means don't care (either H or L).(2)
BA refers to the bank address pins (BA[2:0]).
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2.4.1 Mode Register Set (MRS and EMRS)
COL
MRS/EMRS
BANK
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_CAS
DDR_BA[2:0]
DDR_A[13:0]
2.4.2 Refresh Mode
Peripheral Architecture
DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory foroperation. These registers control burst type, burst length, CAS latency, DLL enable/disable, single-endedstrobe, etc.
The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory byissuing MRS and EMRS commands. When the MRS or EMRS command is executed, the value onDDR_BA[1:0] selects the mode register to be written and the data on DDR_A[12:0] is loaded into theregister. Figure 3 shows the timing for an MRS and EMRS command.
The DDR2 memory controller only issues MRS and EMRS commands during the DDR2 memory controllerinitialization sequence. See Section 2.11 for more information.
Figure 3. DDR2 MRS and EMRS Command
The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device (Figure 4 ). REFR isautomatically preceded by a DCAB command, ensuring the deactivation of all CE spaces and banksselected. Following the DCAB command, the DDR2 memory controller begins performing refreshes at arate defined by the refresh rate (REFRESH_RATE) bit in the SDRAM refresh control register (SDRFC).Page information is always invalid before and after a REFR command; thus, a refresh cycle always forcesa page miss. This type of refresh cycle is often called autorefresh. Autorefresh commands may not bedisabled within the DDR2 memory controller. See Section 2.8 for more details on REFR commandscheduling.
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REFR
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_A[13:0]
2.4.3 Activation (ACTV)
ACTV
BANK
ROW
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_A[13:0]
Peripheral Architecture
Figure 4. Refresh Command
The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write toa closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads orwrites) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selectsthe row. When the DDR2 memory controller issues an ACTV command, a delay of t
RCD
is incurred beforea read or write command is issued. Figure 5 shows an example of an ACTV command. Reads or writes tothe currently active row and bank of memory can achieve much higher throughput than reads or writes torandom areas because every time a new row is accessed, the ACTV command must be issued and adelay of t
RCD
incurred.
Figure 5. ACTV Command
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2.4.4 Deactivation (DCAB and DEAC)
DCAB
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_A[13:11, 9:0]
DDR_A[10]
DEAC
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_A[13:11, 9:0]
DDR_A[10]
Peripheral Architecture
The precharge all banks command (DCAB) is performed after a reset to the DDR2 memory controller orfollowing the initialization sequence. DDR2 SDRAMs also require this cycle prior to a refresh (REFR) andmode set register commands (MRS and EMRS). During a DCAB command, DDR_A[10] is driven high toensure the deactivation of all banks. Figure 6 shows the timing diagram for a DCAB command.
Figure 6. DCAB Command
The DEAC command closes a single bank of memory specified by the bank select signals. Figure 7 showsthe timings diagram for a DEAC command.
Figure 7. DEAC Command
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2.4.5 READ Command
DDR_D[31:0]
DDR_DQS[3:0]
COL
BANK
DDR_A[10]
CAS Latency
D0 D1 D2 D3 D4 D5 D6 D7
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_A[13:0]
Peripheral Architecture
Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM. The READcommand initiates a burst read operation to an active row. During the READ command, DDR_CAS driveslow, DDR_WE and DDR_RAS remain high, the column address is driven on DDR_A[12:0], and the bankaddress is driven on DDR_BA[2:0].
The DDR2 memory controller uses a burst length of 8, and has a programmable CAS latency of 2, 3, 4, or5. The CAS latency is three cycles in Figure 8 . Read latency is equal to CAS latency plus additive latency.The DDR2 memory controller always configures the memory to have an additive latency of 0, so readlatency equals CAS latency. Since the default burst size is 8, the DDR2 memory controller returns 8pieces of data for every read command. If additional accesses are not pending to the DDR2 memorycontroller, the read burst completes and the unneeded data is disregarded. If additional accesses arepending, depending on the scheduling result, the DDR2 memory controller can terminate the read burstand start a new read burst. Furthermore, the DDR2 memory controller does not issue a DCAB/DEACcommand until page information becomes invalid.
Figure 8. DDR2 READ Command
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2.4.6 Write (WRT) Command
DDR_D[31:0]
DDR_DQS[3:0]
COL
BANK
DQM7
Sample
D0 D1 D2 D3 D4 D5 D6 D7
DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM8
Write Latency
DDR_A[10]
DDR_CLK
DDR_CLK
DDR_CS
DDR_CKE
DDR_RAS
DDR_WE
DDR_DQM[3:0]
DDR_CAS
DDR_BA[2:0]
DDR_A[13:0]
2.5 Memory Width and Byte Alignment
Peripheral Architecture
Prior to a WRT command, the desired bank and row are activated by the ACTV command. Following theWRT command, a write latency is incurred. Write latency is equal to CAS latency minus 1. All writes havea burst length of 8. The use of the DDR_DQM outputs allows byte and halfword writes to be executed.Figure 9 shows the timing for a write on the DDR2 memory controller.
If the transfer request is for less than 8 words, depending on the scheduling result and the pendingcommands, the DDR2 memory controller can:•Mask out the additional data using DDR_DQM outputs•Terminate the write burst and start a new write burst
The DDR2 memory controller does not perform the DEAC command until page information becomesinvalid.
Figure 9. DDR2 WRT Command
The DDR2 memory controller supports memory widths of 16 bits and 32 bits. Table 4 summarizes theaddressable memory ranges on the DDR2 memory controller.
Table 4. Addressable Memory Ranges
Memory Width Maximum Addressable Bytes Address Type Generated by DDR2Memory Controller
×16 128 Mbytes Halfword address×32 256 Mbytes Word address
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DDR2 memory controller data bus
DDR_D[31:24]
(Byte Lane 3) DDR_D[23:16]
(Byte Lane 2) DDR_D[15:8]
(Byte Lane 1) DDR_D[7:0] (Byte Lane 0)
32-bit memory device
16-bit memory device
2.6 Address Mapping
Peripheral Architecture
Figure 10 shows the byte lanes used on the DDR2 memory controller. The external memory is alwaysright aligned on the data bus.
Figure 10. Byte Alignment
The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory. Thisstatement is true regardless of the number of memory devices located on the chip select space. TheDDR2 memory controller receives DDR2 memory access requests along with a 32-bit logical address fromthe rest of the system. In turn, DDR2 memory controller uses the logical address to generate a row/page,column, and bank address for the DDR2 SDRAM. The number of column and bank address bits used isdetermined by the IBANK and PAGESIZE fields (see Table 5 ). The DDR2 memory controller uses up to14 bits for the row/page address.
Table 5. Bank Configuration Register Fields for Address Mapping
Bit Field Bit Value Bit Description
IBANK Defines the number of internal banks on the external DDR2 memory.0 1 bank1h 2 banks2h 4 banks3h 8 banksPAGESIZE Defines the page size of each page of the external DDR2 memory.0 256 words (requires 8 column address bits)1h 512 words (requires 9 column address bits)2h 1024 words (requires 10 column address bits)3h 2048 words (requires 11 column address bits)
Figure 11 and Figure 12 show how the logical address bits map to the row, column, and bank bits allcombinations of IBANK and PAGESIZE values. Note that the upper four bits of the logical address cannotbe used for memory addressing, as the DDR2 memory controller has a maximum addressable memoryrange of 256 Mbytes.
The DDR2 memory controller address pins provide the row and column address to the DDR2 SDRAM,thus the DDR2 memory controller appropriately shifts the logical address during row and column addressselection. The bank address is driven to the DDR2 SDRAM using the bank address pins. The two lowerbits of the logical address decode the value of the byte enable pins (only used for accesses less than thewidth of the DDR2 memory controller data bus).
Figure 11. Logical Address-to-DDR2 SDRAM Address Map for 32-Bit SDRAM
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Peripheral Architecture
SDCFG Bit Logical Address
IBANK PAGESIZE 31:28 27 26 25 24 23 22:17 16 15 14 13 12 11 10 9:2
0 0 X X X X X nrb=14
(1)
ncb=8
1 0 X X X X nrb=14 nbb=1 ncb=8
2 0 X X X nrb=14 nbb=2 ncb=8
3 0 X X nrb=14 nbb=3 ncb=8
0 1 X X X X nrb=14 ncb=9
1 1 X X X nrb=14 nbb=1 ncb=9
2 1 X X nrb=14 nbb=2 ncb=9
3 1 X nrb=14 nbb=3 ncb=9
0 2 X X X nrb=14 ncb=10
1 2 X X nrb=14 nbb=1 ncb=10
2 2 X nrb=14 nbb=2 ncb=10
3 2 X nrb=13 nbb=3 ncb=10
0 3 X X nrb=14 ncb=11
1 3 X nrb=14 nbb=1 ncb=11
2 3 X nrb=12 nbb=2 ncb=11
3 3 X nrb=11 nbb=3 ncb=11(1)
Legend: nrb = number of row address bits; ncb = number of column address bits; nbb = number of bank address bits; BE = byteenable bits.
Figure 12. Logical Address-to-DDR2 SDRAM Address Map for 16-bit SDRAM
SDCFG Bit Logical Address
IBANK PAGESIZE 31:28 27 26 25 24 23 22 21:16 15 14 13 12 11 10 9 8:1
0 0 X X X X X X nrb=14
(1)
ncb=8
1 0 X X X X X nrb=14 nbb=1 ncb=8
2 0 X X X X nrb=14 nbb=2 ncb=8
3 0 X X X nrb=14 nbb=3 ncb=8
0 1 X X X X X nrb=14 ncb=9
1 1 X X X X nrb=14 nbb=1 ncb=9
2 1 X X X nrb=14 nbb=2 ncb=9
3 1 X X nrb=14 nbb=3 ncb=9
0 2 X X X X nrb=14 ncb=10
1 2 X X X nrb=14 nbb=1 ncb=10
2 2 X X nrb=14 nbb=2 ncb=10
3 2 X nrb=14 nbb=3 ncb=10
0 3 X X X nrb=14 ncb=11
1 3 X X nrb=14 nbb=1 ncb=11
2 3 X nrb=13 nbb=2 ncb=11
3 3 X nrb=12 nbb=3 ncb=11(1)
Legend: nrb = number of row address bits; ncb = number of column address bits; nbb = number of bank address bits; BE = byteenable bit.
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