Texas Instruments UCC14240EVM-052 User manual

User’s Guide
Using the UCC14240EVM-052 for Biasing Traction Inverter
Gate Driver ICs Requiring Single, Positive or Dual,
Positive/Negative Bias Power
ABSTRACT
This user’s guide provides a description and directions for the use of the UCC14240EVM-052 to evaluate the
UCC14240-Q1, high frequency, integrated transformer, DC-DC converter module from Texas Instruments. This
EVM allows designers to quickly and efficiently evaluate the UCC14240-Q1 for use in automotive or industrial
applications requiring gate driver IC bias power, meeting up to 3 kVRMS isolation.
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Pin Configuration and Functions........................................................................................................................................ 3
2 Description.............................................................................................................................................................................. 4
2.1 EVM Electrical Performance Specifications....................................................................................................................... 5
3 Schematic................................................................................................................................................................................6
4 EVM Setup and Operation......................................................................................................................................................7
4.1 Reference...........................................................................................................................................................................7
4.2 External Connections for Easy Evaluation......................................................................................................................... 7
4.3 Powering the EVM............................................................................................................................................................. 8
4.4 EVM Test Points...............................................................................................................................................................10
4.5 Oscilloscope Probes: Probing the EVM............................................................................................................................11
5 Performance Data ................................................................................................................................................................ 12
5.1 Efficiency Data................................................................................................................................................................. 12
5.2 Regulation Data............................................................................................................................................................... 14
5.3 Start-up Waveforms......................................................................................................................................................... 15
5.4 Inrush Current.................................................................................................................................................................. 17
5.5 AC Ripple Voltage............................................................................................................................................................ 18
5.6 EN and /PG Timing.......................................................................................................................................................... 19
5.7 Shutdown......................................................................................................................................................................... 20
5.8 Steady State.....................................................................................................................................................................21
5.9 Thermal Performance...................................................................................................................................................... 22
6 Assembly and Printed Circuit Board (PCB) Layers...........................................................................................................23
7 Bill of Materials (BOM)..........................................................................................................................................................27
8 Revision History................................................................................................................................................................... 28
Trademarks
All trademarks are the property of their respective owners.
www.ti.com Table of Contents
SLUUCJ2 – JULY 2021
Submit Document Feedback
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
1
Copyright © 2021 Texas Instruments Incorporated

1 Introduction
The UCC14240-Q1 is a high efficiency, low-emissions, 3 kVRMS Isolated DC-DC Converter capable of
delivering up to 1.5-W of power. Because the UCC14240-Q1 provides isolated power in an integrated package,
systems can reduce cost and size by removing the need for separate isolated power supplies. The UCC14240-
Q1 delivers class-leading efficiency in power conversion from the primary to the secondary side while removing
the need for bulky external transformers or power modules commonly used in existing designs. This integration
allows for a much smaller printed circuit board (PCB) area as well as a much lower height profile when
compared to industry standards for power isolation techniques used in the field today.
Introduction www.ti.com
2Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
SLUUCJ2 – JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated

1.1 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GNDP
GNDP
/PG
ENA
GNDP
VIN
VIN
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VEE
VEEA
FBVDD
FBVEE
RLIM
VEE
VEE
VDD
VDD
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
Figure 1-1. DWN Package, 36-Pin SSOP (Top View)
Table 1-1. Pin Functions
PIN TYPE1DESCRIPTION
NAME NO.
GNDP
1, 2, 5, 8, 9, 10,
11, 12, 13, 14,
15, 16, 17, 18
G Primary-side ground connection for VIN. Place several vias to copper pours for thermal relief. .
/PG 3 O
Active low powergood open-drain output pin. /PG pulled low when (UVLO ≤ VIN ≤ OVLO); (UVP1
≤ (VDD - VEE) ≤ OVP1); (UVP2 ≤ (COM - VEE) ≤ OVP2); TJ_Primary ≤ TSHUT_primary; & TJ_secondary ≤
TSHUT_secondary
ENA 4 I Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device
functionality. 5.5-V recommended maximum.
VIN 6, 7 P Primary input voltage. Connect a 2.2-µF ceramic capacitor from VIN to GNDP. Connect a 150-pF
highfrequency bypass ceramic capacitor close the pins.
VEE
19, 20, 21, 22,
23, 24, 25,26,
27, 30,31, 36
GSecondary-side Reference connection for VDD and COM. The VEE pins are used for the high
current return paths.
VDD 28, 29 P
Secondary-side isolated output voltage from transformer. Connect a 2.2-µF and a parallel 150-pF
ceramic capacitor from VDD to VEE. The 150 pF is the high frequency bypass and should be next
to the IC.
RLIM 32 P
Secondary-side second isolated output voltage resistor to limit the source current from VDD to
COM node, and the sink current from COM to VEE. Connect a resistor from RLIM to COM to
regulate the (COM – VEE) voltage.
FBVEE 33 I
Feedback (COM – VEE) output voltage sense pin used to adjust the output (COM – VEE) voltage.
Connect a resistor divider from COM to VEE so that the midpoint is connected to FBVEE, and the
equivalent FBVEE voltage when regulating is 2.5 V.
FBVDD 34 I
Feedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage.
Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and the
equivalent FBVDD voltage when regulating is 2.5 V.
VEEA 35 G
Secondary-side analog sense reference connection for the noise sensitive analog feedback inputs,
FBVDD and FBVEE. Low-side resistors and filter capacitor. Connect to secondary-side gate drive
lowest voltage reference, VEE. Use a single point connection ans place the high frequency
ceramic capacitor close to the VEEA pin.
1. P = power, G = ground, I = input, O = output
www.ti.com Introduction
SLUUCJ2 – JULY 2021
Submit Document Feedback
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
3
Copyright © 2021 Texas Instruments Incorporated

2 Description
The UCC14240EVM-052 is intended to allow designers to evaluate the performance characteristics and
capabilities of the UCC14240-Q1 quickly and easily for use in automotive, isolated, gate driver bias applications
as well as a variety of isolated industrial bias power applications. The EVM allows users to test functions of the
UCC14240-Q1 such as: Enable/Disable (ENA) of the device as well as configure the isolated output voltage for
15 V<VDD<20 V, and -5 V<VEE<0 V and easily apply variable loads to the outputs. This EVM allows the user
to measure efficiency across the input voltage range and varying output loads that the system might require.
Another feature of the EVM is the ease of probing during test. Test points, are strategically placed and described
according to Table 4-2
Figure 2-1. UCC14240EVM-052, HVP052E1p1, Top View
Figure 2-2. UCC14240EVM-052, HVP052E1p1, Bottom View
Description www.ti.com
4Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
SLUUCJ2 – JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated

2.1 EVM Electrical Performance Specifications
Table 2-1. EVM Electrical Specifications
VIN = 24 V, VDD = 20 V, VEE = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VIN Input voltage range 21 24 27 V
VIN_ON Input voltage on 19 21 V
VIN_OFF Input voltage off 17.1 18.9 V
IIN_FL Input current at full load VIN = 21 V, IVDD = 80 mA 135
mAVIN = 24 V, IVDD = 80 mA 125
VIN = 27 V, IVDD = 80 mA 113
IIN_NL Input current at no load VIN = 21 V, IVDD =IVEE = 0 mA 11
mAVIN = 24 V, IVDD =IVEE = 0 mA 10
VIN = 27 V, IVDD =IVEE = 0 mA 10
IIN_OFF Input current at EN LOW EN LOW, VDD = VEE = 0V 460 500 µA
EN to /PG
delay
IVDD =IVEE = 0 mA 2.8 5 ms
OUTPUT CHARACTERISTICS
VDD DC full load set-point 21 V<VIN<27 V, IVDD = 80 mA 20.154 20.166 V
IVDD VDD load current range 21 V < VIN < 27 V 0 80 mA
VDD Load regulation VDDREG =
VImin −VImax
VImax
× 100%
0 mA ≤ IVDD ≤ 80 mA
0.107 %
VDD pk-to-pk AC ripple IVDD = 80 mA 200 250 mV
VDDSS Soft-start IVDD = IVEE = 0 mA 1.8 ms
PMAX Maximum output power IVDD = 100 mA, IVEE = 10 mA 1.5 2 W
VEE DC full load set-point 21 V ≤ VIN ≤ 27 V, IVEE = 10 mA 5.061 5.062 V
IVEE VDD load current range 21 V≤ VIN ≤ 27 V 0 10 mA
VEE pk-to-pk AC ripple IVEE = 10 mA 75 90 mV
SYSTEM CHARACTERISTICS
η Full load efficiency IVDD = 80 mA 59 %
η Half load efficiency IVDD = 40 mA 53 %
FSW Switching frequency 1VIN = 21 V, 0 mA < IVDD < 80 mA 30 34
MHzVIN = 24 V, 0 mA < IVDD < 80 mA 20 25
VIN = 27 V, 0 mA < IVDD < 80 mA 10 23
VDD(OCL) VDD overcurrent limit IVDD > 80 mA 135 145 mA
VEE(OCL) VEE overcurrent limit IVEE > 10 mA 13 15 mA
TMAX Maximum temperature rise
above ambient
IVDD = 80 mA, IVEE = 10 mA 36 40 °C
1. Switching frequency is measured at VDD, VEE secondary and is 2x primary switching frequency
www.ti.com Description
SLUUCJ2 – JULY 2021
Submit Document Feedback
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
5
Copyright © 2021 Texas Instruments Incorporated

3 Schematic
Figure 3-1 shows the EVM electrical schematic. C6 is intentionally unpopulated as indicated by a red X on the
secondary side, placed directly over the com
VEE
VDD
COM
21V<VIN<27V
GNDP
1k
R6
3.3V<Vbias <5V -5V
2.2uF
35V
C12
35V
10uF
C4
35V
10uF
C5
+15V
+20V
35V
10uF
C10
2.2uF
35V
C9
35V
10uF
C3
C3-C7 are gate driver bias caps
1
2
3
J3
ENA
G
TP10
50V
0.1uF
C13
50V
0.1uF
C8
35V
10uF
C6
50V
0.1uF
C11
50V
0.1uF
C7
TP7
TP8
TP9
NOTE:
(1) C6 not installed: +15V/-5V configuration
(2) C6 installed: +20V/-5V configuration
TP2
TP3
TP11
G
TP6
49.9k
0.1%
R2
0.1%
69.8k
R3
0.1%
10k
R1
VDD
COM
VEE
VIN
GNDP
VBIAS
GNDP
GNDP
VBIAS
ENA
/PG
GNDP
GNDP
49.9k
0.1%
R4
VEE
VEE
50V
100pF
C1
G
TP4
FBVDD
SH-J1
50V
100pF
C2
ENA
VEE/VEEA Ground Tie
100k
R5
FBVEE
VEE
TP1
TP5
FBVDD
FBVEE
1
2
J1
1
2
J5
1
2
3
J2
VIN
6
VIN
7
VEE 26
VEE 27
VDD 28
VDD 29
RLIM 32
FBVEE 33
FBVDD 34
VEEA 35
GNDP
5
GNDP
1
PG
3
GNDP
2
ENA
4
GNDP
8
GNDP
9
GNDP
10
GNDP
11
GNDP
12
GNDP
13
GNDP
14
GNDP
15
GNDP
16
GNDP
17
GNDP
18 VEE 19
VEE 20
VEE 21
VEE 22
VEE 23
VEE 24
VEE 25
VEE 30
VEE 31
VEE 36
UCC14240DWNQ1
U1
+5V
Figure 3-1. UCC14240EVM-052 Schematic Diagram
Schematic www.ti.com
6Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
SLUUCJ2 – JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated

4 EVM Setup and Operation
4.1 Reference
• VBIAS: DC power supply1: 5 V, 10 mA
• VIN: DC power supply: 30 V, 200 mA
• IVDD: Electronic load or fixed resistor: 25 V, 80 mA
• IVEE: Electronic load or fixed resistor: 5 V, 10 mA
• (3) DVMs measuring DC voltage < 30 V (V3 in must be a battery powered DVM)
• (3) DVMs measuring DC current < 100 mA on IVDD, IVEE, <200 mA on IVIN
• Oscilloscope: 4 channel, 500 MHz or better, voltage probes, current probes
• Minimum wire gauge 20 AWG to 22 AWG or better
• Thermal camera (optional) or thermocouple to measure U1 case temperature
4.2 External Connections for Easy Evaluation
The UCC14240EVM-052 EVM uses screw terminals for quickly connecting to the VIN, VDD ,and VEE pins.
Connect the appropriate ammeters and voltmeters, as shown in Figure 4-1, to get accurate EVM efficiency
measurements.
Connecting Test Equipment
1. Move jumper J3 into the 1-2, EN OFF position. This assures the EVM cannot start while test equipment is
being connected.
2. Connect a +5 V DC bias power supply J1:1-2 (+3.3 V to +5 V). Set the power supply to 0 V. The +5 V supply
at J1 serves as the pullup bias for /PG and ENA. Turn off/disable the +5V DC Bias power supply.
3. Connect the VIN DC power supply capable of 21 V<VIN<27 V, 200 mA at J5:1-2 (VIN). Adjust the power
supply to 24 V, and set the current limit to 300 mA. Set the power supply to 24 V. Turn off/disable the VIN
power supply.
4. Connect a variable load between J2:1 (VDD) and J2:3 (VEE). If using an electronic load, set to constant
current (CC), 80 mA. Leave the load disabled until the EVM is powered.
5. Connect a second load between J2:2 (COM) and J2:3 (VEE). If using an electronic load, set to constant
current (CC), 10 mA. Leave the load disabled until the EVM is powered.
6. Some electronic loads may not be able to regulate/stabilize CC when setting in the low mA range. Monitor
the input current and load currents by inserting ammeters as shown in Figure 4-1. Use a current probe with
the oscilloscope to verify the stability of the DC current being regulated by an electronic load.
V1
A1
VIN
21-27V
+5V
DC Bias
VISO
LOAD
A2
VEE
LOAD
V2
A3V3
Figure 4-1. Typical Efficiency Measurement Setup
www.ti.com EVM Setup and Operation
SLUUCJ2 – JULY 2021
Submit Document Feedback
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
7
Copyright © 2021 Texas Instruments Incorporated

4.3 Powering the EVM
CAUTION: Do not attempt to start the EVM by applying the EN shorting jumper while VIN and +5V DC Bias
power supplies are enabled. Doing so can result in unpredictable, erratic start up due to excessive signal bounce
induced at J3, EN, as seen in Figure 4-2. It is recommended to leave the EN shorting jumper in the J3:2-3
position and control ON/OFF by enabling or turning ON/OFF the +5V DC Bias power supply. If it is desired to
use the EN shorting jumper for ON/OFF control, a simple RC filter can be applied to the J3 header, on the
bottom of the PCB, as shown in Figure 4-3 which gives the proper start-up signals shown in Figure 4-4. Adding
the RC filter inverts the ENA logic as described in Table 4-1 such that removing the jumper turns ON the EVM
with controlled ENA and inserting the EN jumper into J3:1-2 (OFF) turns OFF the EVM. Applying the shorting
jumper to J3:2-3 (ON) has no effect, even though the RC filter is applied as shown in Figure 4-3
Figure 4-2. ENA Erratic Signal Bounce Causing VDD Collapse (top: ENA, 5V/div, mid: /PG, 5V/div, bot:
VDD, 10V/div), time = 10ms/div unless otherwise noted.
Figure 4-3. RC Debounce Filter, J3 PCB Bottom, R=5.11 kΩ, C=100 nF
EVM Setup and Operation www.ti.com
8Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
SLUUCJ2 – JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated

Figure 4-4. ENA Signal Bounce Removed by Addition of RC filter (top: ENA, 5V/div, mid: /PG, 5V/div, bot:
VDD, 10V/div), time = 2ms/div unless otherwise noted.
Table 4-1. ENA Operation
EN Config Jumper Removed Jumper Install J3:1-2
(OFF)
Jumper Install J3:2-3
(ON)
Comment
No RC filter OFF OFF ON EN chatter
500 µs RC filter R = 5.11 kΩ, C =
100 nF
ON OFF No effect No EN chatter
WARNING
• Hot Surface. Contact may cause burns. U1 package surface can reach temperatures of 45°C
above ambient. Do not touch!
• Do not test this EVM unless you are trained in the proper safety, handling and testing of power
electronics.
4.3.1 Power on for Start-up
1. Verify VIN and +5 V DC bias power supplies are OFF/disabled and no voltage is applied to the UUT
2. Move EN shorting jumper to the J3:2-3 EN ON position
3. Turn on the VIN DC power supply. Verify 24 V is present at TP8-to-TP9
4. Verify the loads on VDD and VEE are disabled
5. Turn on the +5 V DC bias power supply. EVM is now enabled with VDD and VEE in regulation under no load
conditions.
6. Verify 20 V is present on VDD and 5 V is present on VEE
7. Enable the 80-mA load on VDD, enable the 10-mA load on VEE
8. The UCC14240-Q1 is now regulating VDD and VEE and processing ~1.6 W of isolated output power
9. Vary VIN between 21 V<VIN<27 V, vary IVDD between 0 mA<IVDD<80 mA, vary IVEE between 0
mA<IVEE<10 mA.
10. Insert oscilloscope probes into TP10, TP6 and TP4 for measuring VIN, VDD and VEE start-up, steady state
and AC ripple voltage
www.ti.com EVM Setup and Operation
SLUUCJ2 – JULY 2021
Submit Document Feedback
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
9
Copyright © 2021 Texas Instruments Incorporated

4.3.2 Power off for Shutdown
1. Move EN shorting jumper to the J3:1-2, EN OFF position
2. Turn off the +5 V, DC bias power supply
3. Disable the IVDD load
4. Disable the IVEE load
5. Turn off VIN power supply
4.4 EVM Test Points
Table 4-2 describes the various EVM test points, allowing easy access for connecting oscilloscope probes, DVM
test leads and wire connections to lab test equipment as outlined in section 4.1. Special care should be taken to
maintain separation between the primary side, GNDP and secondary side, VEE. Primary-side test points should
not be referenced to VEE through improper test equipment insertion. Likewise, secondary-side test points should
not be referenced to GNDP through improper test equipment insertion.
Table 4-2. Test Points
PIN I/O/TP COLOR DESCRIPTION MIN TYP MAX UNIT
J1 I Green VBIAS, EN and /PG bias 3 VBIAS 5 V
J2:1-3 O Green Secondary VDD-to-VEE 15 27 V
J2:2-3 O Green Secondary COM-to-VEE 0 5 V
J3:1-2 I Black EN, off 0 V
J3:2-3 I Black EN, on VBIAS V
J4 N/A N/A Missing reference designator N/A
J5 I Green VIN, primary input voltage 21 24 27 V
TP1 TP Black VEE, secondary side reference 0 V
TP2 TP Yellow /PG, power good test point VBIAS V
TP3 TP Yellow EN, enable test point VBIAS V
TP4 TP PCB COM-to-VEE, secondary COM scope probe point 0 5 V
TP5 TP White COM-to-VEE, secondary COM output midpoint 0 5 V
TP6 TP PCB VDD-to-VEE, secondary VDD scope probe point 15 28 V
TP7 TP Red VDD, secondary VDD test point 15 28 V
TP8 TP Red VIN, positive probe point 21 24 27 V
TP9 TP Black GNDP, shared primary GND test point 0 V
TP10 TP PCB VIN, scope probe point 21 24 27 V
TP11 TP Black GNDP, shared primary GND test point 0 V
EVM Setup and Operation www.ti.com
10 Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
SLUUCJ2 – JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated

4.5 Oscilloscope Probes: Probing the EVM
Using TP4, TP6 and TP10 oscilloscope probe PCB test points: The UCC12240-Q1 is a high frequency DC-
DC module that requires careful measurement for accurately capturing transient events and measuring high
frequency, AC ripple voltage. Remove the “witch hat” probe tip cover and ground lead from the scope probe.
If scope probe ground springs are not available, wrap a piece of 22 AWG bare wire around the scope probe
ground ring and insert the probe tip and ground into the EVM as shown in Figure 4-5.
Figure 4-5. UCC14240EVM-052, PCB Scope Probe Test Points
The EVM output nomenclature (VDD, VEE, COM) corresponds to what is commonly used when referring to
isolated gate driver ICs. As shown in Figure 3-1, TP5 (COM) is the midpoint of a capacitive divider and is
intended to connect to the COM pin of the isolated gate driver IC. When the UCC14240-Q1 is used to bias a
gate driver IC, VDD (VDD-COM) and VEE (VEE-COM) are referred to with respect to COM. In this case consider
COM to be GND as it acts as a virtual GND to the gate driver IC. Because the midpoint of the capacitive divider
is sensitive to charge imbalance, do not connect any ground-referenced, test equipment to TP5 (COM) when
probing the EVM. A battery powered DVM can be used to measure VEE with respect to COM. When testing
the EVM as a stand-alone bias power supply, limit oscilloscope probing of the secondary-side outputs to TP4
and TP6 which are referenced to VEE . As a result, VDD shows an oscilloscope measurement of VDD+|VEE|
and VEE shows |VEE|. Connecting any ground-referenced test equipment to COM results in a false but safe
overcurrent condition causing VDD and VEE to inadvertently drop out of regulation during light-load operation.
www.ti.com EVM Setup and Operation
SLUUCJ2 – JULY 2021
Submit Document Feedback
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
11
Copyright © 2021 Texas Instruments Incorporated

5 Performance Data
5.1 Efficiency Data
PISO (W)
Efficiency (%)
0 0.5 1 1.5 2 2.5
0
10
20
30
40
50
60
D001
VIN = 21 V
VIN = 24 V
VIN = 27 V
Figure 5-1. UCC14240EVM Efficiency, VISO Loading Only
Table 5-1. Efficiency Test Data (VIN = 21 V)
VIN (V) IIN (mA) VISO (V) IISO (mA) VISO1 (V) VISO2 (V) PIN (W) PISO (W) Eff (%)
21.02 10.74 20.17 0.24 15.11 -5.06 0.23 0.00 2.14
21.02 17.06 20.17 4.49 15.11 -5.06 0.36 0.09 25.25
21.02 25.49 20.17 10.16 15.11 -5.06 0.54 0.20 38.26
21.01 40.92 20.17 20.41 15.11 -5.06 0.86 0.41 47.86
21.01 55.96 20.16 30.37 15.11 -5.06 1.18 0.61 52.07
21.01 70.39 20.16 39.98 15.10 -5.06 1.48 0.81 54.50
21.01 85.98 20.16 50.31 15.10 -5.06 1.81 1.01 56.15
21.01 100.92 20.16 60.20 15.10 -5.06 2.12 1.21 57.23
21.01 115.65 20.16 69.86 15.10 -5.06 2.43 1.41 57.95
21.01 131.00 20.15 80.10 15.09 -5.06 2.75 1.61 58.65
21.01 145.92 20.15 89.98 15.09 -5.06 3.07 1.81 59.14
21.01 161.25 20.14 100.09 15.08 -5.06 3.39 2.02 59.50
21.01 175.99 20.13 109.84 15.07 -5.06 3.70 2.21 59.80
21.01 194.01 20.13 120.13 14.94 -5.08 4.08 2.42 59.33
21.01 199.68 19.16 130.13 14.34 -5.06 4.20 2.49 59.42
Performance Data www.ti.com
12 Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
SLUUCJ2 – JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated

Table 5-2. Efficiency Test Data (VIN = 24 V)
VIN (V) IIN (mA) VISO (V) IISO (mA) VISO1 (V) VISO2 (V) PIN (W) PISO (W) Eff (%)
24.02 10.14 20.18 0.24 15.12 -5.06 0.24 0.00 1.99
24.02 16.41 20.17 5.11 15.12 -5.06 0.39 0.10 26.13
24.01 23.22 20.17 10.24 15.12 -5.06 0.56 0.21 37.06
24.01 36.96 20.17 20.59 15.11 -5.06 0.89 0.42 46.79
24.01 49.87 20.17 30.14 15.11 -5.06 1.20 0.61 50.76
24.01 63.13 20.17 40.10 15.11 -5.06 1.52 0.81 53.35
24.01 76.56 20.17 50.03 15.11 -5.06 1.84 1.01 54.88
24.01 90.42 20.17 60.28 15.11 -5.06 2.17 1.22 55.99
24.01 103.68 20.16 70.01 15.10 -5.06 2.49 1.41 56.70
24.01 117.60 20.16 80.17 15.10 -5.06 2.82 1.62 57.24
24.01 131.17 20.16 89.99 15.10 -5.06 3.15 1.81 57.60
24.01 145.13 20.16 100.12 15.10 -5.06 3.48 2.02 57.92
24.01 159.48 20.16 110.28 15.10 -5.06 3.83 2.22 58.06
24.01 173.45 20.16 120.12 15.09 -5.06 4.16 2.42 58.14
24.01 188.00 20.11 130.15 15.05 -5.07 4.51 2.62 57.98
24.01 192.37 19.78 135.13 14.71 -5.06 4.62 2.67 57.86
24.01 196.14 19.23 140.14 14.16 -5.07 4.71 2.69 57.22
24.01 199.87 18.65 145.41 13.58 -5.07 4.80 2.71 56.50
Table 5-3. Efficiency Test Data (VIN = 27 V)
VIN (V) IIN (mA) VISO (V) IISO (mA) VISO1 (V) VISO2 (V) PIN (W) PISO (W) Eff (%)
27.02 9.88 20.19 0.24 15.13 -5.06 0.27 0.00 1.81
27.02 15.69 20.18 5.07 15.12 -5.06 0.42 0.10 24.14
27.02 22.02 20.18 10.24 15.12 -5.06 0.59 0.21 34.75
27.01 34.75 20.18 20.57 15.12 -5.06 0.94 0.42 44.21
27.01 46.73 20.18 30.06 15.12 -5.06 1.26 0.61 48.04
27.01 59.12 20.17 40.04 15.12 -5.06 1.60 0.81 50.58
27.01 71.94 20.17 50.33 15.11 -5.06 1.94 1.02 52.25
27.01 84.68 20.17 60.21 15.11 -5.06 2.29 1.21 53.10
27.01 96.98 20.17 69.94 15.11 -5.06 2.62 1.41 53.85
27.01 110.15 20.17 80.03 15.11 -5.06 2.98 1.61 54.25
27.01 123.36 20.17 90.26 15.11 -5.06 3.33 1.82 54.63
27.01 136.49 20.17 100.36 15.11 -5.06 3.69 2.02 54.90
27.01 149.47 20.17 110.19 15.10 -5.06 4.04 2.22 55.04
27.01 162.32 20.17 120.01 15.10 -5.06 4.38 2.42 55.20
27.01 175.96 20.17 130.02 15.10 -5.07 4.75 2.62 55.17
27.01 189.71 20.17 140.05 15.10 -5.07 5.12 2.82 55.11
27.01 202.86 20.04 150.27 14.96 -5.07 5.48 3.01 54.94
27.01 206.29 19.43 155.03 14.26 -5.07 5.57 3.01 54.06
27.01 209.62 18.79 160.38 13.72 -5.07 5.66 3.01 53.23
www.ti.com Performance Data
SLUUCJ2 – JULY 2021
Submit Document Feedback
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
13
Copyright © 2021 Texas Instruments Incorporated

5.2 Regulation Data
Figure 5-2. UCC14240EVM Regulation vs Power, VISO Loading Only
Figure 5-3. UCC14240EVM Regulation vs Current, VISO Loading Only
Performance Data www.ti.com
14 Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
SLUUCJ2 – JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated

5.3 Start-up Waveforms
Figure 5-4. Start-up 1: VIN=24 V, IISO=0 mA, (top: VISO, 10V/div, mid-1: COM, 5V/div, mid-2: VDD=VISO-
COM, 10V/div, bot: VEE=-COM, 5V/div), time = 2ms/div unless otherwise noted.
Figure 5-5. Start-up 2: VIN=24 V, IISO=80 mA, (top: VISO, 10V/div, mid-1: COM, 5V/div, mid-2: VDD=VISO-
COM, 10V/div, bot: VEE=-COM, 5V/div), time = 2ms/div unless otherwise noted.
www.ti.com Performance Data
SLUUCJ2 – JULY 2021
Submit Document Feedback
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
15
Copyright © 2021 Texas Instruments Incorporated

Figure 5-6. Start-up 3: VIN=24 V, IISO=80 mA, (top: VISO, 10V/div, mid-1: COM, 2V/div, mid-2: VDD=VISO-
COM, 10V/div, mid-3: VEE=-COM, 5V/div, mid-4: /PG, 5V/div, bot: ENA, 5V/div), time = 2ms/div unless
otherwise noted.
Figure 5-7. Start-up 4: VIN=24 V, IISO=80 mA, (top: VISO, 10V/div, bot: COM, 2V/div), time = 2ms/div
unless otherwise noted.
Performance Data www.ti.com
16 Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
SLUUCJ2 – JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated

5.4 Inrush Current
Figure 5-8. Inrush Current: VIN=24 V, IISO=80 mA, (top: VISO, 10V/div, mid-1: COM, 5V/div, mid-2: IIN,
0.1A/div, bot: /PG, 10V/div), time = 2ms/div unless otherwise noted.
Figure 5-9. Inrush Current: VIN=24 V, IISO=80 mA, Zoom, (top: VISO, 10V/div, mid-1: COM, 5V/div, mid-2:
IIN, 0.1A/div, mid-3: /PG, 5V/div, mid-4: VISO, 6.2V/div, 305µs/div, bot: IIN, 0.05A/div, 305µs/div), time =
2ms/div unless otherwise noted.
www.ti.com Performance Data
SLUUCJ2 – JULY 2021
Submit Document Feedback
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
17
Copyright © 2021 Texas Instruments Incorporated

5.5 AC Ripple Voltage
Figure 5-10. VDDAC=250 mV, VEEAC=70 mV, IVDD=80 mA, IVEE=10 mA (top: VISO, 0.1V/div, bot: COM,
0.02V/div), time = 100ms/div unless otherwise noted.
Figure 5-11. AC Ripple: VIN=24V, IVDD=80 mA, IVEE=10 mA, FSW(pri)=12.9 MHz, (top: VISO, 0.1V/div,
mid-1: COM, 0.02V/div, mid-2: COM, 0.02V/divc, 100ns/div, bot: VISO, 5mV/div, 100ns/div), time = 5µs/div
unless otherwise noted.
Performance Data www.ti.com
18 Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
SLUUCJ2 – JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated

Figure 5-12. AC Ripple: VIN=24V, IVDD=80 mA, IVEE=10 mA, FSW(pri)=7.5 kHz, (top: VISO, 0.1V/div, bot:
COM, 0.02V/div), time = 100µs/div unless otherwise noted.
5.6 EN and /PG Timing
Figure 5-13. ENA to /PG Delay, 4.2 ms, IVDD=80 mA, (top: ENA, 5V/div, mid: /PG, 5V/div, bot: VDD, 10V/
div), time = 2ms/div unless otherwise noted.
www.ti.com Performance Data
SLUUCJ2 – JULY 2021
Submit Document Feedback
Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
19
Copyright © 2021 Texas Instruments Incorporated

5.7 Shutdown
Figure 5-14. Shutdown VIN Removal: VIN=17.6 V, IVDD=80 mA (top: VISO, 10V/div, mid-1: COM, 2V/div,
mid-2: VDD=VISO-COM, 10V/div, mid-3: VEE=-COM, 5V/div, mid-4 (blue): VIN, 20V/div, bot: IIN, 0.1A/div),
time = 2ms/div unless otherwise noted.
Figure 5-15. Shutdown EN Low: VIN=24 V, IVDD=80 mA, (top: VISO, 10V/div, mid-1: COM, 2V/div, mid-2:
VDD=VISO-COM, 10V/div, mid-3: VEE=-COM, 5V/div, mid-4: /PG, 5V/div, bot: ENA, 5V/div), time = 2ms/div
unless otherwise noted.
Performance Data www.ti.com
20 Using the UCC14240EVM-052 for Biasing Traction Inverter Gate Driver ICs
Requiring Single, Positive or Dual, Positive/Negative Bias Power
SLUUCJ2 – JULY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated