Xilinx CAN FD v2.0 User manual

CAN FD v2.0
LogiCORE IP Product Guide
Vivado Design Suite
PG223 December 5, 2018

CAN FD v2.0 2
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Table of Contents
IP Facts
Chapter 1: Overview
Core Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 3: Designing with the Core
Operating Modes and States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 5: Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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Chapter 6: Test Bench
Appendix A: Verification, Compliance, and Interoperability
Compliance Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Appendix B: Upgrading
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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CAN FD v2.0 4
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Introduction
The Xilinx® LogiCORE™ IP CAN with Flexible
Data Rate (CAN FD) core is ideally suited for
automotive and industrial applications such as
automotive body control units, automotive test
equipment, instrument clusters, sensor
controls, and industrial networks. The core can
be used in standalone mode or connected to
Xilinx MicroBlaze™ processors or the Arm®
Cortex-A9 processors in Zynq®-7000 SoCs.
Features
• Designed to ISO 11898-1/2015
specification [Ref 1]
• Supports both CAN and CAN FD frames
• Supports the CAN FD frame format
specified in the ISO 11898:2015
specification [Ref 1]
• Supports up to 64 byte CAN FD frames
• Supports flexible data rates up to 8 Mb/s
• Supports nominal data rates up to 1Mb/s
• Up to three data bit transmitter delay
compensation
• TX and RX mailbox buffers with
configurable depth
• Two 64-deep RX FIFOs with 32 ID
Filter-Mask pairs
• Message with lowest ID transmitted first
• Supports TX message cancellation
• Separate error logging for fast data rate
IMPORTANT: It is required to have a valid Bosch CAN
FD protocol license before selling a device containing
the Xilinx CAN FD IP core.
IP Facts
LogiCORE™ IP Facts Table
Core Specifics
Supported
Device Family(1)
UltraScale+™
UltraScale™
Zynq®-7000 SoC, 7 Series,
Zynq UltraScale+ MPSoC Architecture
Supported User
Interfaces AXI4-Lite, APB
Resources Performance and Resource Utilization web page
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Test Bench Verilog
Constraints File XDC
Simulation
Model Not Provided
Supported
S/W Driver(2) Standalone and Linux
Tested Design Flows(3)
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete listing of supported devices, see the Vivado IP
catalog.
2. Standalone driver details can be found in the SDK directory
(\Xilinx\SDK\<release_version>\data\embeddedsw\XilinxPro
cessorIPLib\drivers\canfd_version). Linux OS and driver
support information is available from the Linux CAN FD
Driver Page.
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
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IP Facts
Other Features
• Timestamp for transmitted and received messages
• Supports transmit event FIFO
• Supports the following modes:
°Disable Auto-Retransmission (DAR) mode
°Snoop (Bus Monitoring) mode
°Sleep mode with Wake-Up Interrupt
°Internal Loopback mode
°Bus-Off Recovery mode
-Auto-Recovery
- User intervention for Auto-Recovery
°Disable Protocol Exception Event mode
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Chapter 1
Overview
This product guide describes features of the CAN FD core and the functionality of the
various registers in the design. In addition, the core interface and its customization options
are defined in this document. Information on the CAN or CAN FD protocol is outside the
scope of this document, and knowledge of the relevant CAN and CAN FD specifications is
assumed. Figure 1-1 illustrates the high-level architecture of the CAN FD core and provides
the interface connectivity.
Note: The core requires an external PHY to be connected to communicate on the CAN bus.
X-Ref Target - Figure 1-1
Figure 1-1: CAN FD Core Layered Architecture and Connectivity
CAN FD Core
Host
Control
Object Layer/LLC
AXI4-Lite
I/F
TX Block
RAM
TBMM
Register Module
RX Block
RAM
RBMM
CDC
Sync
AXI Clock Domain
CAN FD Protocol Engine
Transfer Layer/MAC
CAN Clock Domain
PHY
CAN Bus
TX
RX
AXI4-Lite Bus
X14811-081418
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Chapter 1: Overview
Core Description
The core functions are divided into two independent layers as shown in Figure 1-1. The
object layer interfaces with the host control through the AXI4-Lite/APB interface and works
in the AXI4-Lite/APB clock domain. The transfer layer interfaces with the external PHY and
operates in the CAN clock domain. Information exchange between the two layers is done
through the CDC synchronizers. The CAN FD object layer provides a state-of-the-art
transmission and reception method to manage message buffers.
Object Layer (Logical Link Layer)
The object layer is divided into the following submodules:
•Register Module – This module allows for read and write access to the registers
through the external host interface.
•TX Buffer Management Module – The TX Buffer Management Module (TBMM)
interfaces with the CAN FD protocol engine to provide the next buffer to transmit on
the CAN bus. It manages the host access to the TX block RAM.
•RX Buffer Management Module – The RX Buffer Management Module (RBMM)
interfaces with the CAN FD protocol engine to provide storage for message reception
from the CAN bus. It manages the host access to the RX block RAM.
Transfer Layer (Medium Access Control Layer)
The transfer layer provides the following main functions:
• Initiation of the transmission process after recognizing bus idle (compliance with
inter-frame space)
°Serialization of the frame
°Bit stuffing
°Arbitration and passing into receive mode in case of loss of arbitration
°ACK check
°Presentation of a serial bitstream to PHY for transmission
°CRC sequence calculation including stuff bit count for FD frames
°Bit rate switching
• Reception of a serial bitstream from the PHY
°Deserialization and recompiling of the frame structure
°Bit destuffing
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Chapter 1: Overview
°Transmission of ACK
°Bit rate switching
• Bit timing functions
• Error detection and signaling
• Recognition of an overload condition and reaction
Licensing and Ordering
IMPORTANT: It is required to have a valid Bosch CAN FD protocol license before selling a device
containing the Xilinx CAN FD IP core.
License Checkers
If the IP requires a license key, the key must be verified. The Vivado® design tools have
several license checkpoints for gating licensed IP through the flow. If the license check
succeeds, the IP can continue generation. Otherwise, generation halts with error. License
checkpoints are enforced by the following tools:
• Vivado synthesis
• Vivado implementation
• write_bitstream (Tcl command)
IMPORTANT: IP license level is ignored at checkpoints. The test confirms a valid license exists. It does
not check IP license level.
License Type
The core is provided under the terms of the CAN FD LogiCORE™ IP License Agreement for
Automotive or Non-Automotive applications. Click here for more information about
obtaining a CAN FD license.
For more information, visit the CAN FD product web page.
Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual
Property page. For information on pricing and availability of other Xilinx LogiCORE IP
modules and tools, contact your local Xilinx sales representative.
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Chapter 2
Product Specification
Standards
The CAN FD core conforms to the ISO-11898-1/2015 standard specification [Ref 1].
Performance
For full details about performance, visit the Performance and Resource Utilization web
page.
Resource Utilization
For full details about resource utilization, visit the Performance and Resource Utilization
web page.
Port Descriptions
The host interface of the CAN FD core is either the AXI4-Lite or the APB interface,
depending on the parameter selected in the Vivado™ IDE. Tab le 2 -1 defines the core
interface signaling.
Table 2-1: CAN FD Core I/O Signals
Signal Name Interface Type Default Description
AXI4-Lite Interface Signals
s_axi_*(1) S_AXI_LITE – – See the Vivado AXI Reference Guide (UG1037)
[Ref 7] for the description of the AXI4 signals.
Clock, Interrupt, and PHY Signals
ip2bus_intrevent Interrupt O 0x0 Active-High interrupt line.(2)(3)
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Chapter 2: Product Specification
Register Space
The CAN FD core requires a 32 KB memory mapped space to be allocated in the system
memory. Division of this addressable space within the core is shown in Tab le 2 -2 .
Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal,
and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For write access, both the AXI
Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted
together.
can_clk Clock I– CAN clock input. Oscillator frequency tolerance
according to the standard specification.
can_phy_tx PHY O 1 CAN bus transmit signal to PHY.
can_phy_rx PHY I – CAN bus receive signal from PHY.
can_clk_x2 Clock I - This is fully synchronous to the CAN clock and is
a multiple by 2 in frequency.
APB Interface Signals
apb_clk Clock I - APB clock.
apb_resetn Reset I - Active-Low synchronous reset.
apb_pwdata[31:0] APB I - Write data bus.
apb_paddr[14:0] I - Address bus.
apb_pwrite I - Read or Write signaling:
• 0 for Read Transaction.
• 1 for Write Transaction.
apb_psel I - Active-High select.
apb_penable I - Active-High enable.
apb_prdata[31:0] O 0x0 Read Data bus.
apb_pready O 0x0 Active-High ready signal.
apb_perror APB O 0x0 Active-High R/W error signal. Reserved for future
use.
Notes:
1. The core does not support the wstrb signal on the AXI4-Lite interface.
2. The interrupt line is level-sensitive. Interrupts are indicated by the transition of the interrupt line logic from 0 to 1.
3. The AXI4-Lite interface signals and ip2bus_intrevent are synchronous to the s_axi_aclk clock.
Table 2-1: CAN FD Core I/O Signals
Signal Name Interface Type Default Description
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Chapter 2: Product Specification
Table 2-2: CAN FD Address Space Division
Start Address End Address Section Notes
0x0000 0x00FF Core Registers Space This space is implemented with flip-flops. See
Tabl e 2 -3 and Ta b le 2 - 4.
0x0100 0x1FFF TX Message Space
This space is implemented with TX block RAM
and provides storage for a maximum 32 TX
buffers. For RX Sequential buffer mode (FIFO
mode), it also
provides storage for 32 ID Filter-Mask pairs. See
Tabl e 2 -30 .
0x2000 0x7FFF RX Message Space
This space is implemented with RX block RAM.
For RX Sequential buffer mode (FIFO mode), it
provides storage for two 64-deep message RX
FIFO's. See Table 2 - 37 and Ta ble 2- 3 8.
It provides storage for 32 deep TX Event FIFO.
See Tabl e 2 -34 .
For RX Ma ilbox buffer mode, it provides storage
for maximum 48 RX Buffers and respective ID
Masks. See Ta ble 2 - 44.
Table 2-3: CAN FD Core Register Address Map
Start
Address Name Access Description Notes
0x0000 SRR Read, Write Software Reset Register
Registers present in
both RX Mailbox
and RX Sequential/
FIFO buffer modes.
0x0004 MSR Read, Write Mode Select Register
0x0008 BRPR Read, Write Arbitration Phase Baud Rate Prescaler
Register
0x000C BTR Read, Write Arbitration Phase Bit Register
0x0010 ECR Read Error Counter Register
0x0014 ESR Read, Write
1 to clear Error Status Register
0x0018 SR Read Status Register
0x001C ISR Read Interrupt Status Register
0x0020 IER Read, Write Interrupt Enable Register
0x0024 ICR Write Interrupt Clear Register
0x0028 TSR Read, Write Timestamp Register
0x002C-
0x0084 Reserved – Reserved space. Write has no effect. Read always returns 0.
0x0088 DP_BRPR Read, Write Data Phase Baud Rate Prescaler Register
0x008C DP_BTR Read, Write Data Phase Bit Timing Register
0x0090 TRR Read, Write TX Buffer Ready Request Register
0x0094 IETRS Read, Write Interrupt Enable TX Buffer Ready Request
Served/Cleared Register
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Chapter 2: Product Specification
Core Register Descriptions
Tabl e 2 - 4 shows the CAN FD core register space. The thick ruling represents the RX Mailbox
specific register bits and the gray represents the RX FIFO specific register bits. Register bits
that are used in both RX Mailbox and RX FIFO mode and differ in description are shown with
a / separator.
0x0098 TCR Read, Write TX Buffer Cancel Request Register
Registers present in
both RX Mailbox
and RX Sequential/
FIFO buffer modes.
0x009C IETCS Read, Write Interrupt Enable TX Buffer Cancellation
Request Served/Cleared Register
0x00A0 TxE_FSR Read, Write TX Event FIFO Status Register.
0x00A4 TxE_WMR Read, Write TX Event FIFO Watermark Register.
0x00A8-
0x00AC Reserved – Reserved space. Write has no effect. Read always returns 0.
0x00B0 RCS0 Read, Write RX Buffer Control Status Register 0
Registers present
only in RX Mailbox
buffer mode.
Otherwise reserved.
0x00B4 RCS1 Read, Write See RX Buffer Control Status Register 0
0x00B8 RCS2 Read, Write
0x00BC Reserved – Reserved space. Write has no effect. Read
always returns 0.
0x00C0 IERBF0 Read, Write Interrupt Enable RX Buffer Full Register 0
0x00C4 IEBRF1 Read, Write Interrupt Enable RX Buffer Full Register 1
0x00C8-
0x00DC Reserved – Reserved space. Write has no effect. Read always returns 0.
0x00E0 AFR Read, Write Acceptance Filter (Control) Register
Registers present
only in RX
Sequential/FIFO
buffer mode
otherwise reserved.
0x00E4 Reserved – Reserved space. Write has no effect. Read
always returns 0.
0x00E8 FSR Read, Write RX FIFO Status Register
0x00EC WMR Read, Write RX FIFO Watermark Register
0x00F0-
0x00FF Reserved – Reserved space. Write has no effect. Read always returns 0.
Table 2-3: CAN FD Core Register Address Map (Cont’d)
Start
Address Name Access Description Notes
Table 2-4: CAN FD Core Register Space
Start
Address 313029282726252423222120191817161514131211109876543210
Name
(Reset
Value)
0x0000 RSVD
CEN SRST
SRR (0x0)
0x0004 RSVD RSVD
ABR SBR DPEE DAR BRSD SNOOP LBACK SLEEP
MSR (0x0)
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Chapter 2: Product Specification
0x0008 RSVD BRP [7:0] BRPR
(0x0)
0x000C RSVD SJW[6:0]
RSVD
TS2[6:0] TS1[7:0] BTR (0x0)
0x0010 RSVD REC[7:0] TEC[7:0] ECR (0x0)
0x0014 RSVD
F_BERR F_STER F_FMER F_CRCER RSVD ACKER BERR STER FMER CRCER
ESR (0x0)
0x0018 RSVD TDCV[6:0] RSVD
SNOOP RSVD BSFR_CONFIG PEE_CONFIG ESTAT [1:0] ERRWRN BBSY BIDLE NORMAL SLEEP LBACK CONFIG
SR (0x1)
0x001C
TXEWMFLL TXEOFLW
RXBOFLW_I [5:0] RXLRM_BI [5:0]
RXMNF RXBOFLW/RXFWMFLL_1 RXBFL/RXFOFLW_1 TXCRS TXRRS RXFWMFLL WKUP SLP BSOFF ERROR RSVD RXFOFLW TSCNT_OFLW RXOK BSFRD PEE TXOK ARBLST
ISR (0x0)
0x0020
ETXEWMFLL ETXEOFLW
RSVD
ERXMNF ERXBOFLW/ERXFWMFLL_1 ERXBFL/ERXFOFLW_1 ETXCRS ETXRRS ERXFWMFLL EWKUP ESLP EBSOFF EERROR RSVD ERXOFLW ETSCNT_OFLW ERXOK EBSFRD EPEE ETXOK EARBLST
IER (0x0)
0x0024
CTXEWMFLL CTXEOFLW
RSVD
CRXMNF CRXBOFLW/CRXFWMFLL_1 CRXBFL/CRXFOFLW_1 CTXCRS CTXRRS CRXFWMFLL CWKUP CSLP CBSOFF CERROR RSVD CRXOFLW CTSCNT_OFLW CRXOK CBSFRD CPEE CTXOK CARBLST
ICR (0x0)
0x0028 TIMESTAMP_CNT[15:0] RSVD
CTS
TSR (0x0)
0x002C
-
0x0084
RSVD Reserved
0x0088 RSVD
TDC_EN RSVD
TDCOFF [5:0] DP_BRP [7:0] DP_BRPR
(0x0)
0x008C RSVD DP_SJW
[3:0] RSVD DP_TS2 [3:0] RSVD DP_TS1[4:0] DP_BTR (0x0)
0x0090
RR31 RR30 RR29 RR28 RR27 RR26 RR25 RR24 RR23 RR22 RR21 RR20 RR19 RR18 RR17 RR16 RR15 RR14 RR13 RR12 RR11 RR10 RR9 RR8 RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0
TRR (0x0)
Table 2-4: CAN FD Core Register Space (Cont’d)
Start
Address 313029282726252423222120191817161514131211109876543210
Name
(Reset
Value)
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Chapter 2: Product Specification
0x0094
ERRS31 ERRS30 ERRS29 ERRS28 ERRS27 ERRS26 ERRS25 ERRS24 ERRS23 ERRS22 ERRS21 ERRS20 ERRS19 ERRS18 ERRS17 ERRS16 ERRS15 ERRS14 ERRS13 ERRS12 ERRS11 ERRS10 ERRS9 ERRS8 ERRS7 ERRS6 ERRS5 ERRS4 ERRS3 ERRS2 ERRS1 ERRS0
IETRS
(0x0)
0x0098
CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
TCR (0x0)
0x009C
ECRS31 ECRS30 ECRS29 ECRS28 ECRS27 ECRS26 ECRS25 ECRS24 ECRS23 ECRS22 ECRS21 ECRS20 ECRS19 ECRS18 ECRS17 ECRS16 ECRS15 ECRS14 ECRS13 ECRS12 ECRS11 ECRS10 ECRS9 ECRS8 ECRS7 ECRS6 ECRS5 ECRS4 ECRS3 ECRS2 ECRS1 ECRS0
IETCS
(0x0)
0x00A0 RSVD TXE_FL[5:0]
TXE_IRI
RSVD
TXE_RI[4:0] TxE_FSR
(0x0)
0x00A4 RSVD TXE_FWM[4:0] TxE_WMR
(0xF)
0x00A8 RSVD Reserved
0x00AC RSVD Reserved
0x00B0
CSB15 CSB14 CSB13 CSB12 CSB11 CSB10 CSB9 CSB8 CSB7 CSB6 CSB5 CSB4 CSB3 CSB2 CSB1 CSB0 HCB15 HCB14 HCB13 HCB12 HCB11 HCB10 HCB9 HCB8 HCB7 HCB6 HCB5 HCB4 HCB3 HCB2 HCB1 HCB0
RCS0
(0x0)
0x00B4
CSB31 CSB30 CSB29 CSB28 CSB27 CSB26 CSB25 CSB24 CSB23 CSB22 CSB21 CSB20 CSB19 CSB18 CSB17 CSB16 HCB31 HCB30 HCB29 HCB28 HCB27 HCB26 HCB25 HCB24 HCB23 HCB22 HCB21 HCB20 HCB19 HCB18 HCB17 HCB16
RCS1
(0x0)
0x00B8
CSB47 CSB46 CSB45 CSB44 CSB43 CSB42 CSB41 CSB40 CSB39 CSB38 CSB37 CSB36 CSB35 CSB34 CSB33 CSB32 HCB47 HCB46 HCB45 HCB44 HCB43 HCB42 HCB41 HCB40 HCB39 HCB38 HCB37 HCB36 HCB35 HCB34 HCB33 HCB32
RCS2
(0x0)
0x00BC RSVD Reserved
0x00C0
ERBF31 ERBF30 ERBF29 ERBF28 ERBF27 ERBF26 ERBF25 ERBF24 ERBF23 ERBF22 ERBF21 ERBF20 ERBF19 ERBF18 ERBF17 ERBF16 ERBF15 ERBF14 ERBF13 ERBF12 ERBF11 ERBF10 ERBF9 ERBF8 ERBF7 ERBF6 ERBF5 ERBF4 ERBF3 ERBF2 ERBF1 ERBF0
IERBF
(0x0)
0x00C4 RSVD
ERBF47 ERBF46 ERBF45 ERBF44 ERBF43 ERBF42 ERBF41 ERBF40 ERBF39 ERBF38 ERBF37 ERBF36 ERBF35 ERBF34 ERBF33 ERBF32
IERBF
(0x0)
0x00C8 RSVD Reserved
0x00CC RSVD Reserved
0x00D0 RSVD Reserved
0x00D4 RSVD Reserved
0x00D8 RSVD Reserved
0x00DC RSVD Reserved
0x00E0
UAF31 UAF30 UAF29 UAF28 UAF27 UAF26 UAF25 UAF24 UAF23 UAF22 UAF21 UAF20 UAF19 UAF18 UAF17 UAF16 UAF15 UAF14 UAF13 UAF12 UAF11 UAF10 UAF9 UAF8 UAF7 UAF6 UAF5 UAF4 UAF3 UAF2 UAF1 UAF0
AFR (0x0)
0x00E4 RSVD Reserved
0x00E8
RSVD
FL_1[6:0](1)
IRI_1(1) RSVD
RI_1[5:0](1)
RSVD
FL[6:0]
IRI RSVD
RI[5:0] FSR (0x0)
0x00EC RSVD RXFP[4:0]
RSVD
RXFWM_1[5:0]
RSVD
RXFWM[5:0] WMR
(0xF)
0x00F0 RSVD Reserved
0x00F4 RSVD Reserved
Table 2-4: CAN FD Core Register Space (Cont’d)
Start
Address 313029282726252423222120191817161514131211109876543210
Name
(Reset
Value)
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Chapter 2: Product Specification
Software Reset Register (Address Offset + 0x0000)
Writing to the Software Reset register (SRR) places the core in Configuration mode. In
Configuration mode, the core drives recessive on the bus line and does not transmit or
receive messages. During power-up, the CEN and SRST bits are 0 and the CONFIG bit in the
Status register (SR) is 1. The Transfer Layer Configuration registers can be changed only
when the CEN bit in the SRR is 0. Mode Select register bits (except SLEEP and SBR) can be
changed only when the CEN bit is 0. If the CEN bit is changed during core operation, Xilinx
recommends resetting the core so that operation starts over.
Mode Select Register (Address Offset + 0x0004)
Writing to the Mode Select register (MSR) enables the core to enter Snoop, Sleep,
Loopback, or Normal modes. In Normal mode, the core participates in normal bus
communication. If the SLEEP bit is set to 1, the core enters Sleep mode. If the LBACK bit is
set to 1, the core enters Loopback mode. If the SNOOP mode is set to 1, the core enters
Snoop mode and does not participate in bus communication but only receives messages.
0x00F8 RSVD Reserved
0x00FC RSVD Reserved
Notes:
1. These fields are only available when the IP is configured in FIFO (Sequential) Mode and RX FIFO-1 is enabled.
Table 2-4: CAN FD Core Register Space (Cont’d)
Start
Address 313029282726252423222120191817161514131211109876543210
Name
(Reset
Value)
Table 2-5: Software Reset Register
Bits Name Access Default
Value Description
31:2 Reserved – 0 Reserved.
1CENR/W0
CAN Enable.
This is the Enable bit for the core.
• 1 = The core is in Loopback, Sleep, Snoop, or Normal mode,
depending on the LBACK, SLEEP, and SNOOP bits in the MSR.
• 0 = The core is in Configuration mode.
Note: If the CEN bit is cleared during core operation, Xilinx recommends
resetting the core so that operation starts over.
0SRSTWO0
Reset.
This is the software reset bit for the core.
• 1 = Core is reset.
If a 1 is written to this bit, all core configuration registers
(including the SRR) are reset. Reads to this bit always return 0.
Note: After performing a soft or hard reset, wait for 16 AXI4-Lite/APB
clock cycles before initiating next AXI4-Lite/APB transaction.
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IMPORTANT: LBACK, SLEEP, and SNOOP bits should never be set to 1 at the same time. At any given
point, the core can either be in Loopback, Sleep, or Snoop mode. When all three bits are set to 0, the
core can enter Normal mode subject to other conditions.
Table 2-6: Mode Select Register
Bits Name Access Default
Value Description
31:16 Reserved – 0 Reserved.
15:8 Reserved – 0 Reserved.
7ABRR/W0
Auto Bus-Off Recovery Request.
• 1 = Auto Bus-Off Recovery request.
• 0 = No such request.
If this bit is set, the node does auto Bus-Off Recovery
irrespective of the SBR bit setting in this register. This bit can be
written only when the CEN bit in SRR is 0.
6SBRR/W0
Start Bus-Off Recovery Request.
• 1 = Start Bus-Off Recovery request.
• 0 = No such request.
Node stays in Bus-Off state until the SBR bit is set to 1 (providing
that the ABR bit in this register is not set).
This bit can be written only when node is in Bus-Off state.
This bit auto clears after node completes the Bus-Off Recovery
or leaves Bus-Off state due to hard/soft reset or CEN
deassertion.
5DPEER/W 0
Disable Protocol Exception Event Detection/Generation.
• 1 = Disable Protocol Exception Event detection/generation by
CAN FD receiver if “res” bit in CAN FD frame is detected as 1.
In this case, CAN FD receiver generates Form error.
• 0 = PEE detection/generation is enabled. If the CAN FD
rec e iver detect s th e r es bit as 1, it goes to Bus I ntegration state
(PEE_config) and waits for Bus Idle condition (11 consecutive
nominal recessive bits). The error counter remains unchanged.
This bit can be written only when the CEN bit in SRR is 0.
4DARR/W0
Disable Auto-Retransmission.
• 1 = Disable auto retransmission on the CAN bus to provide
single shot transmission.
• 0 = Auto retransmission enabled.
This bit can be written only when the CEN bit in SRR is 0.
3BRSDR/W 0
CAN FD Bit Rate Switch Disable Override.
• 1 = Makes the core transmit CAN FD frames only in nominal
bit rate (by overriding the TX Message element BRS bit
setting).
• 0 = Makes the core transmit CAN FD frames as per BRS bit in
the TX Message element.
This bit can be written only when the CEN bit in SRR is 0.
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Arbitration Phase (Nominal) Baud Rate Prescaler Register (Address Offset +
0x0008)
The CAN clock for the core is divided by (programmed prescaler value + 1) to generate the
quantum clock needed for sampling and synchronization.
2 SNOOP R/W 0
SNOOP Mode Select/Request.
This is the Snoop mode request bit.
• 1 = Request core to be in Snoop mode.
• 0 = No such request.
This bit can be written only when CEN bit in SRR is 0.
Make sure that Snoop mode is programmed only after system
reset or software reset. For the core to enter Snoop mode, LBACK
and SLEEP bits in this register should be set to 0. The features of
Snoop mode are as follows:
• The core transmits recessive bits onto the CAN bus.
• The core receives messages that are transmitted by other
nodes but does not ACK. Stores received messages in RX block
RAM based on programmed ID filtering.
• Error counters are disabled and cleared to 0. Reads to the error
counter register return zero.
1LBACKR/W 0
Loopback Mode Select/Request.
This is the Loopback mode request bit.
• 1 = Request core to be in Loopback mode.
• 0 = No such request.
This bit can be written only when the CEN bit in SRR is 0. For the
core to enter Loopback mode, SLEEP and SNOOP bits in this
register should be set to 0.
0SLEEPR/W 0
Sleep Mode Select/Request.
This is the Sleep mode request bit.
• 1 = Request core to be in Sleep mode.
• 0 = No such request.
This bit is cleared when the core wakes up from Sleep mode. For
the core to enter Sleep mode, LBACK and SNOOP bits in this
register should be set to 0.
Table 2-7: Arbitration Phase Baud Rate Prescaler Register
Bits Name Access Default
Value Description
31:8 Reserved – 0 Reserved.
7:0 BRP[7:0] R/W 0
Arbitration Phase (Nominal) Baud Rate Prescaler.
These bits indicate the prescaler value.
The actual value is one more than the value written to the register.
These bits can be written only when the CEN bit in SRR is 0.
Table 2-6: Mode Select Register (Cont’d)
Bits Name Access Default
Value Description
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Arbitration Phase (Nominal) Bit Timing Register (Address Offset + 0x000C)
Error Count Register (Address Offset + 0x0010)
The ECR is a read-only register. Writes to the ECR have no effect. The values of the error
counters in the register reflect the values of the transmit and receive error counters in the
core. The following conditions reset the Transmit and Receive Error counters:
• When 1 is written to the SRST bit in the SRR.
• When 0 is written to the CEN bit in the SRR.
• When the core enters Bus-Off state.
• During Bus-Off recovery until the core enters Error Active state (after 128 occurrences
of 11 consecutive recessive bits).
IMPORTANT: When in Bus-Off recovery, the Receive Error counter is advanced/incremented by 1 when
a sequence of 11 consecutive nominal recessive bits is seen.
Note: In SNOOP mode, error counters are disabled and cleared to 0. Reads to the Error Counter
register return 0.
Table 2-8: Arbitration Phase Bit Register
Bits Name Access Default
Value Description
31:23 Reserved – 0 Reserved.
22:16 SJW[6:0] R/W 0
Synchronization Jump Width.
Indicates the Synchronization Jump Width as specified in the
standard for Nominal Bit Timing.
The actual value is one more than the value written to the register.
These bits can be written only when the CEN bit in SRR is 0.
15 Reserved – 0 Reserved.
14:8 TS2[6:0] R/W 0
Time Segment 2
Indicates the Phase Segment 2 as specified in the standard for
Nominal Bit Timing.
The actual value is one more than the value written to the register.
These bits can be written only when the CEN bit in SRR is 0.
7:0 TS1[7:0] R/W 0
Time Segment 1
Indicates the Sum of Propagation Segment and Phase Segment 1
as specified in the standard for Nominal Bit Timing.
The actual value is one more than the value written to the register.
These bits can be written only when the CEN bit in SRR is 0.
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.
Error Status Register (Address Offset + 0x0014)
The Error Status register (ESR) indicates the type of error that has occurred on the bus. If
more than one error occurs, all relevant error flag bits are set in this register. The ESR is a
write 1 to clear register. Writes to this register do not set any bits, but clear the bits that are
set.
Table 2-9: Error Counter Register
Bits Name Access Default
Value Description
31:16 Reserved – 0 Reserved.
15:8 REC[7:0] R 0 Receive Error Count.
Indicates the value of Receive Error Counter.
7:0 TEC[7:0] R 0 Transmit Error Count.
Indicates the value of Transmit Error Counter.
Table 2-10: Error Status Register
Bits Name Default
Value Description
31:12 Reserved 0 Reserved
11 F_BERR 0
Bit Error in CAN FD Data Phase(1).
• 1 = Indicates a bit error occurred in Data Phase (Fast) data rate.
• 0 = Indicates a bit error has not occurred in Data Phase (Fast) data rate
after the last write to this bit.
If this bit is set, writing a 1 clears it.
10 F_STER 0
Stuff Error in CAN FD Data Phase.
• 1 = Indicates stuff error occurred in Data Phase (Fast) data rate.
• 0 = Indicates stuff error has not occurred in Data Phase (Fast) data rate.
after the last write to this bit.
If this bit is set, writing a 1 clears it.
9F_FMER 0
Form Error in CAN FD Data Phase.
• 1 = Indicates form error occurred in Data Phase (Fast) data rate.
• 0 = Indicates form error has not occurred in Data Phase (Fast) data rate.
after the last write to this bit.
If this bit is set, writing a 1 clears it.
8F_CRCER 0
CRC Error in CAN FD Data Phase.
• 1 = Indicates CRC error occurred in Data Phase (Fast) data rate.
• 0 = Indicates CRC error has not occurred in Data Phase (Fast) data rate
after the last write to this bit.
If this bit is set, writing a 1 clears it.
7:5 Reserved 0 Reserved.
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4ACKER 0
ACK Error.
Indicates an acknowledgment error.
• 1 = Indicates an acknowledgment error has occurred.
• 0 = Indicates an acknowledgment error has not occurred on the bus
after the last write to this bit.
If this bit is set, writing a 1 clears it.
3BERR 0
Bit Error.
Indicates the received bit is not the same as the transmitted
bit during bus communication.
• 1 = Indicates a bit error has occurred.
• 0 = Indicates a bit error has not occurred on the bus after the last write
to this bit.
If this bit is set, writing a 1 clears it.
2STER 0
Stuff Error.
Indicates an error if there is a stuffing violation.
• 1 = Indicates a stuff error has occurred.
• 0 = Indicates a stuff error has not occurred on the bus after the last
write to this bit.
If this bit is set, writing a 1 clears it.
1FMER 0
Form Error.
Indicates an error in one of the fixed form fields in the message frame.
• 1 = Indicates a form error has occurred.
• 0 = Indicates a form error has not occurred on the bus after the last
write to this bit.
If this bit is set, writing a 1 clears it.
0CRCER 0
CRC Error(3).
Indicates a CRC error has occurred.
• 1 = Indicates a CRC error has occurred.
• 0 = Indicates a CRC error has not occurred on the bus after the last
write to this bit.
If this bit is set, writing a 1 clears it.
Notes:
1. In transmitter delay compensation phase, any error is reported as fast bit error (by the transmitter).
2. Fixed stuff bit errors are reported as form error.
3. In case of a CRC Error and a CRC delimiter corruption, only the FMER bit is set.
Table 2-10: Error Status Register (Cont’d)
Bits Name Default
Value Description
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