Xilinx CAN FD v2.0 User manual

CAN FD v2.0
LogiCORE IP Product Guide
Vivado Design Suite
PG223 December 5, 2018

CAN FD v2.0 2
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Table of Contents
IP Facts
Chapter 1: Overview
Core Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 3: Designing with the Core
Operating Modes and States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Chapter 5: Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Simulating the Example Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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Chapter 6: Test Bench
Appendix A: Verification, Compliance, and Interoperability
Compliance Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Appendix B: Upgrading
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Appendix C: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Appendix D: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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CAN FD v2.0 4
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Introduction
The Xilinx® LogiCORE™ IP CAN with Flexible
Data Rate (CAN FD) core is ideally suited for
automotive and industrial applications such as
automotive body control units, automotive test
equipment, instrument clusters, sensor
controls, and industrial networks. The core can
be used in standalone mode or connected to
Xilinx MicroBlaze™ processors or the Arm®
Cortex-A9 processors in Zynq®-7000 SoCs.
Features
• Designed to ISO 11898-1/2015
specification [Ref 1]
• Supports both CAN and CAN FD frames
• Supports the CAN FD frame format
specified in the ISO 11898:2015
specification [Ref 1]
• Supports up to 64 byte CAN FD frames
• Supports flexible data rates up to 8 Mb/s
• Supports nominal data rates up to 1Mb/s
• Up to three data bit transmitter delay
compensation
• TX and RX mailbox buffers with
configurable depth
• Two 64-deep RX FIFOs with 32 ID
Filter-Mask pairs
• Message with lowest ID transmitted first
• Supports TX message cancellation
• Separate error logging for fast data rate
IMPORTANT: It is required to have a valid Bosch CAN
FD protocol license before selling a device containing
the Xilinx CAN FD IP core.
IP Facts
LogiCORE™ IP Facts Table
Core Specifics
Supported
Device Family(1)
UltraScale+™
UltraScale™
Zynq®-7000 SoC, 7 Series,
Zynq UltraScale+ MPSoC Architecture
Supported User
Interfaces AXI4-Lite, APB
Resources Performance and Resource Utilization web page
Provided with Core
Design Files Encrypted RTL
Example Design Verilog
Test Bench Verilog
Constraints File XDC
Simulation
Model Not Provided
Supported
S/W Driver(2) Standalone and Linux
Tested Design Flows(3)
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete listing of supported devices, see the Vivado IP
catalog.
2. Standalone driver details can be found in the SDK directory
(\Xilinx\SDK\<release_version>\data\embeddedsw\XilinxPro
cessorIPLib\drivers\canfd_version). Linux OS and driver
support information is available from the Linux CAN FD
Driver Page.
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
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IP Facts
Other Features
• Timestamp for transmitted and received messages
• Supports transmit event FIFO
• Supports the following modes:
°Disable Auto-Retransmission (DAR) mode
°Snoop (Bus Monitoring) mode
°Sleep mode with Wake-Up Interrupt
°Internal Loopback mode
°Bus-Off Recovery mode
-Auto-Recovery
- User intervention for Auto-Recovery
°Disable Protocol Exception Event mode
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Chapter 1
Overview
This product guide describes features of the CAN FD core and the functionality of the
various registers in the design. In addition, the core interface and its customization options
are defined in this document. Information on the CAN or CAN FD protocol is outside the
scope of this document, and knowledge of the relevant CAN and CAN FD specifications is
assumed. Figure 1-1 illustrates the high-level architecture of the CAN FD core and provides
the interface connectivity.
Note: The core requires an external PHY to be connected to communicate on the CAN bus.
X-Ref Target - Figure 1-1
Figure 1-1: CAN FD Core Layered Architecture and Connectivity
CAN FD Core
Host
Control
Object Layer/LLC
AXI4-Lite
I/F
TX Block
RAM
TBMM
Register Module
RX Block
RAM
RBMM
CDC
Sync
AXI Clock Domain
CAN FD Protocol Engine
Transfer Layer/MAC
CAN Clock Domain
PHY
CAN Bus
TX
RX
AXI4-Lite Bus
X14811-081418
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Chapter 1: Overview
Core Description
The core functions are divided into two independent layers as shown in Figure 1-1. The
object layer interfaces with the host control through the AXI4-Lite/APB interface and works
in the AXI4-Lite/APB clock domain. The transfer layer interfaces with the external PHY and
operates in the CAN clock domain. Information exchange between the two layers is done
through the CDC synchronizers. The CAN FD object layer provides a state-of-the-art
transmission and reception method to manage message buffers.
Object Layer (Logical Link Layer)
The object layer is divided into the following submodules:
•Register Module – This module allows for read and write access to the registers
through the external host interface.
•TX Buffer Management Module – The TX Buffer Management Module (TBMM)
interfaces with the CAN FD protocol engine to provide the next buffer to transmit on
the CAN bus. It manages the host access to the TX block RAM.
•RX Buffer Management Module – The RX Buffer Management Module (RBMM)
interfaces with the CAN FD protocol engine to provide storage for message reception
from the CAN bus. It manages the host access to the RX block RAM.
Transfer Layer (Medium Access Control Layer)
The transfer layer provides the following main functions:
• Initiation of the transmission process after recognizing bus idle (compliance with
inter-frame space)
°Serialization of the frame
°Bit stuffing
°Arbitration and passing into receive mode in case of loss of arbitration
°ACK check
°Presentation of a serial bitstream to PHY for transmission
°CRC sequence calculation including stuff bit count for FD frames
°Bit rate switching
• Reception of a serial bitstream from the PHY
°Deserialization and recompiling of the frame structure
°Bit destuffing
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Chapter 1: Overview
°Transmission of ACK
°Bit rate switching
• Bit timing functions
• Error detection and signaling
• Recognition of an overload condition and reaction
Licensing and Ordering
IMPORTANT: It is required to have a valid Bosch CAN FD protocol license before selling a device
containing the Xilinx CAN FD IP core.
License Checkers
If the IP requires a license key, the key must be verified. The Vivado® design tools have
several license checkpoints for gating licensed IP through the flow. If the license check
succeeds, the IP can continue generation. Otherwise, generation halts with error. License
checkpoints are enforced by the following tools:
• Vivado synthesis
• Vivado implementation
• write_bitstream (Tcl command)
IMPORTANT: IP license level is ignored at checkpoints. The test confirms a valid license exists. It does
not check IP license level.
License Type
The core is provided under the terms of the CAN FD LogiCORE™ IP License Agreement for
Automotive or Non-Automotive applications. Click here for more information about
obtaining a CAN FD license.
For more information, visit the CAN FD product web page.
Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual
Property page. For information on pricing and availability of other Xilinx LogiCORE IP
modules and tools, contact your local Xilinx sales representative.
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Chapter 2
Product Specification
Standards
The CAN FD core conforms to the ISO-11898-1/2015 standard specification [Ref 1].
Performance
For full details about performance, visit the Performance and Resource Utilization web
page.
Resource Utilization
For full details about resource utilization, visit the Performance and Resource Utilization
web page.
Port Descriptions
The host interface of the CAN FD core is either the AXI4-Lite or the APB interface,
depending on the parameter selected in the Vivado™ IDE. Tab le 2 -1 defines the core
interface signaling.
Table 2-1: CAN FD Core I/O Signals
Signal Name Interface Type Default Description
AXI4-Lite Interface Signals
s_axi_*(1) S_AXI_LITE – – See the Vivado AXI Reference Guide (UG1037)
[Ref 7] for the description of the AXI4 signals.
Clock, Interrupt, and PHY Signals
ip2bus_intrevent Interrupt O 0x0 Active-High interrupt line.(2)(3)
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Chapter 2: Product Specification
Register Space
The CAN FD core requires a 32 KB memory mapped space to be allocated in the system
memory. Division of this addressable space within the core is shown in Tab le 2 -2 .
Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal,
and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For write access, both the AXI
Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted
together.
can_clk Clock I– CAN clock input. Oscillator frequency tolerance
according to the standard specification.
can_phy_tx PHY O 1 CAN bus transmit signal to PHY.
can_phy_rx PHY I – CAN bus receive signal from PHY.
can_clk_x2 Clock I - This is fully synchronous to the CAN clock and is
a multiple by 2 in frequency.
APB Interface Signals
apb_clk Clock I - APB clock.
apb_resetn Reset I - Active-Low synchronous reset.
apb_pwdata[31:0] APB I - Write data bus.
apb_paddr[14:0] I - Address bus.
apb_pwrite I - Read or Write signaling:
• 0 for Read Transaction.
• 1 for Write Transaction.
apb_psel I - Active-High select.
apb_penable I - Active-High enable.
apb_prdata[31:0] O 0x0 Read Data bus.
apb_pready O 0x0 Active-High ready signal.
apb_perror APB O 0x0 Active-High R/W error signal. Reserved for future
use.
Notes:
1. The core does not support the wstrb signal on the AXI4-Lite interface.
2. The interrupt line is level-sensitive. Interrupts are indicated by the transition of the interrupt line logic from 0 to 1.
3. The AXI4-Lite interface signals and ip2bus_intrevent are synchronous to the s_axi_aclk clock.
Table 2-1: CAN FD Core I/O Signals
Signal Name Interface Type Default Description
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