Xilinx Virtex-6 FPGA User manual

Virtex-6 FPGA
Configurable Logic Block
User Guide
UG364 (v1.2) February 3, 2012
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Virtex-6 FPGA CLB User Guide www.xilinx.com UG364 (v1.2) February 3, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
06/24/09 1.0 Initial Xilinx release.
09/16/09 1.1 Add Virtex-6 HXT devices to Table 2. Updated discussions at Look-Up Table (LUT),
page 11, and Static Read Operation, page 29. CLB labeling change in figures throughout
document (Figure 6 through Figure 13, Figure 15, Figure 17, Figure 27 through
Figure 29), including clarifying the TDS/TDH functions, descriptions, and notes in
Table 7, page 39 and Table 8, page 42.
02/03/12 1.2 In Enable – WE/WED, updated second sentence to say that an inactive write enable
prevents writing to memory cells. In Inverting Clock Pins, updated second sentence to
“positive edge of the clock.”
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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Virtex-6 FPGA CLB
CLB Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Slice Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CLB / Slice Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
General Slice Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Slice Distributed RAM Timing Model and Parameters (Available in SLICEM only) 38
Slice SRL Timing Model and Parameters (Available in SLICEM only) . . . . . . . . . . . . 41
Slice Carry-Chain Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CLB Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Distributed RAM Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Shift Registers (SRLs) Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Other Shift Register Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Multiplexer Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Carry Chain Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table of Contents
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UG364 (v1.2) February 3, 2012
Preface
About This Guide
This guide serves as a technical reference describing the Virtex®-6 FPGA configurable
logic blocks (CLBs). Usually, the logic synthesis software assigns the CLB resources
without system designer intervention. It can be advantageous for the designer to
understand certain CLB details, including the varying capabilities of the look-up tables
(LUTs), the physical direction of the carry propagation, the number and distribution of the
available flip-flops, and the availability of the very efficient shift registers. This guide
describes these and other features of the CLB in detail.
Additional Documentation
The following documents are also available for download at
http://www.xilinx.com/support/documentation/virtex-6.htm.
• Virtex-6 Family Overview
The features and product selection of the Virtex-6 family are outlined in this overview.
• Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and Switching Characteristic specifications for the
Virtex-6 family.
• Virtex-6 FPGA Packaging and Pinout Specifications
This specification includes the tables for device/package combinations and maximum
I/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, and
thermal specifications.
• Virtex-6 FPGA Configuration Guide
This all-encompassing configuration guide includes chapters on configuration
interfaces (serial and SelectMAP), bitstream encryption, boundary-scan and JTAG
configuration, reconfiguration techniques, and readback through the SelectMAP and
JTAG interfaces.
• Virtex-6 FPGA Clocking Resources User Guide
This guide describes the clocking resources available in all Virtex-6 devices, including
the MMCM and PLLs.
• Virtex-6 FPGA Memory Resources User Guide
The functionality of the block RAM and FIFO are described in this user guide.
• Virtex-6 FPGA SelectIO Resources User Guide
This guide describes the SelectIO™ resources available in all Virtex-6 devices.
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Preface: About This Guide
• Virtex-6 FPGA GTH Transceivers User Guide
This guide describes the GTH transceivers available in all Virtex-6 HXT FPGAs except
the XC6VHX250T and the XC6VHX380T in the FF1154 package..
• Virtex-6 FPGA GTX Transceivers User Guide
This guide describes the GTX transceivers available in all Virtex-6 FPGAs except the
XC6VLX760.
• Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC User Guide
This guide describes the dedicated Tri-Mode Ethernet Media Access Controller
available in all Virtex-6 FPGAs except the XC6VLX760.
• Virtex-6 FPGA DSP48E1 Slice User Guide
This guide describes the architecture of the DSP48E1 slice in Virtex-6 FPGAs and
provides configuration examples.
• Virtex-6 FPGA System Monitor User Guide
The System Monitor functionality available in all Virtex-6 devices is outlined in this
guide.
• Virtex-6 FPGA PCB Design Guide
This guide provides information on PCB design for Virtex-6 devices, with a focus on
strategies for making design decisions at the PCB and interface level.
Additional Support Resources
To search the database of silicon and software questions and answers or to create a
technical support case in WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
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Virtex-6 FPGA CLB
CLB Overview
The Configurable Logic Blocks (CLBs) are the main logic resources for implementing
sequential as well as combinatorial circuits. Each CLB element is connected to a switch
matrix for access to the general routing matrix (shown in Figure 1). A CLB element
contains a pair of slices. These two slices do not have direct connections to each other, and
each slice is organized as a column. Each slice in a column has an independent carry chain.
For each CLB, slices in the bottom of the CLB are labeled as SLICE(0), and slices in the top
of the CLB are labeled as SLICE(1).
The Xilinx tools designate slices with the following definitions. An “X” followed by a
number identifies the position of each slice in a pair as well as the column position of the
slice. The “X” number counts slices starting from the bottom in sequence 0, 1 (the first CLB
column); 2, 3 (the second CLB column); etc. A “Y” followed by a number identifies a row of
slices. The number remains the same within a CLB, but counts up in sequence from one
CLB row to the next CLB row, starting from the bottom. Figure 2 shows four CLBs located
in the bottom-left corner of the die.
X-Ref Target - Figure 1
Figure 1: Arrangement of Slices within the CLB
Switch
Matrix
Slice(1)
COUTCOUT
CINCIN
Slice(0)
CLB
ug364_01_040209
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CLB Overview
Slice Description
Every slice contains four logic-function generators (or look-up tables), eight storage
elements, wide-function multiplexers, and carry logic. These elements are used by all slices
to provide logic, arithmetic, and ROM functions. In addition to this, some slices support
two additional functions: storing data using distributed RAM and shifting data with 32-bit
registers. Slices that support these additional functions are called SLICEM; others are
called SLICEL. SLICEM (shown in Figure 3) represents a superset of elements and
connections found in all slices. SLICEL is shown in Figure 4.
Each CLB can contain zero or one SLICEM. Every other CLB column contains a SLICEMs.
In addition, the two CLB columns to the left of the DSP48E columns both contain a SLICEL
and a SLICEM.
X-Ref Target - Figure 2
Figure 2: Row and Column Relationship between CLBs and Slices
Slice
X1Y1
COUTCOUT
CINCIN
Slice
X0Y1
CLB
ug364_02_040209
Slice
X1Y0
COUTCOUT
Slice
X0Y0
CLB
Slice
X3Y1
COUTCOUT
CINCIN
Slice
X2Y1
CLB
Slice
X3Y0
COUTCOUT
Slice
X2Y0
CLB
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CLB Overview
X-Ref Target - Figure 3
Figure 3: Diagram of SLICEM
A6:A1
D
COUT
D
DX
C
CX
B
BX
A
AX
O6
DI2
O5
DI1
MC31WEN
CK
DI1
MC31WEN
CK
DI1
MC31WEN
CK
DI1
MC31WEN
CK
ug364_03_040209
DX DMUX
D
DQ
C
CQ
CMUX
B
BQ
BMUX
A
AQ
AMUX
Reset Type
D
FF/LAT
INIT1
INIT0
SRHI
SRLO
SR
CE
CK
FF/LAT
INIT1
INIT0
SRHI
SRLO
FF/LAT
INIT1
INIT0
SRHI
SRLO
FF/LAT
INIT1
INIT0
SRHI
SRLO
D
SR
CE
CK
D
SR
CE
CK
D
SR
Q
CE
CK
CIN
0/1
WEN
CK
Sync/Async
FF/LAT
A6:A1
O6
O5
C6:1
CX
D6:1
DI
A6:A1
O6
O5
B6:1
BX
A6:A1
W6:W1
W6:W1
W6:W1
W6:W1
O6
O5
A6:1
AX
SR
CE
CLK
CE Q
CK SR
Q
Q
Q
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
DI2
DI2
DI2
CI
BI
AI
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CLB Overview
X-Ref Target - Figure 4
Figure 4: Diagram of SLICEL
A6:A1
D
COUT
D
DX
C
CX
B
BX
A
AX
O6
O5
ug364_04_040209
DX DMUX
D
DQ
C
CQ
CMUX
B
BQ
BMUX
A
AQ
AMUX
Reset Type
D
FF/LAT
INIT1
INIT0
SRHI
SRLO
SR
CE
CK
FF/LAT
INIT1
INIT0
SRHI
SRLO
FF/LAT
INIT1
INIT0
SRHI
SRLO
FF/LAT
INIT1
INIT0
SRHI
SRLO
D
SR
CE
CK
D
SR
CE
CK
D
SR
Q
CE
CK
CIN
0/1
Sync/Async
FF/LAT
A6:A1
O6
O5
C6:1
CX
D6:1
A6:A1
O6
O5
B6:1
BX
A6:A1
O6
O5
A6:1
AX
SR
CE
CLK
CE Q
CK SR
Q
Q
Q
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
D
CE Q
CK SR
SRHI
SRLO
INIT1
INIT0
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CLB Overview
CLB/Slice Configurations
Table 1 summarizes the logic resources in one CLB. Each CLB or slice can be implemented
in one of the configurations listed. Table 2 shows the available resources in all CLBs.
Look-Up Table (LUT)
The function generators in Virtex-6 FPGAs are implemented as six-input look-up tables
(LUTs). There are six independent inputs (A inputs - A1 to A6) and two independent
outputs (O5 and O6) for each of the four function generators in a slice (A, B, C, and D). The
function generators can implement any arbitrarily defined six-input Boolean function.
Each function generator can also implement two arbitrarily defined five-input Boolean
functions, as long as these two functions share common inputs. Only the O6 output of the
function generator is used when a six-input function is implemented. Both O5 and O6 are
used for each of the five-input function generators implemented. In this case, A6 is driven
High by the software. The propagation delay through a LUT is independent of the function
implemented, or whether one six-input or two five-input generators are implemented.
Signals from the function generators can exit the slice (through A, B, C, D output for O6 or
AMUX, BMUX, CMUX, DMUX output for O5), enter the XOR dedicated gate from an O6
output (see Fast Lookahead Carry Logic), enter the carry-logic chain from an O5 output
(see Fast Lookahead Carry Logic), enter the select line of the carry-logic multiplexer from
Ta b le 1 : Logic Resources in One CLB
Slices LUTs Flip-Flops Arithmetic and
Carry Chains Distributed RAM(1) Shift Registers(1)
2 8 16 2 256 bits 128 bits
Notes:
1. SLICEM only, SLICEL does not have distributed RAM or shift registers.
Table 2: Virtex-6 FPGA Logic Resources Available in All CLBs
Device Total
Slices SLICELs SLICEMs Number of 6-Input LUTs
Maximum
Distributed RAM (Kb)
Shift
Register (Kb)
Number of
Flip-Flops
XC6VLX75T 11,640 7,460 4,180 46,560 1,045 522.5 93,120
XC6VLX130T 20,000 13,040 6,960 80,000 1,740 870 160,000
XC6VLX195T 31,200 19,040 12,160 124,800 3,140 1,570 249,600
XC6VLX240T 37,680 23,080 14,600 150,720 3,770 1,885 301,440
XC6VLX365T 56,880 40,360 16,520 227,520 4,130 2,065 455,040
XC6VLX550T 85,920 61,120 24,800 343,680 6,200 3,100 687,360
XC6VLX760 118,560 85,440 33,120 474,240 8,280 4,140 948,480
XC6VSX315T 49,200 28,840 20,360 196,800 5,090 2,545 393,600
XC6VSX475T 74,400 48,840 30,560 297,600 7,640 3,820 595,200
XC6VHX250T 39,360 27,200 12,160 157,440 3,040 1,520 314,880
XC6VHX255T 39,600 27,400 12,200 158,400 3,050 1,525 316,800
XC6VHX380T 59,760 41,520 18,240 239,040 4,570 2,285 478,080
XC6VHX565T 88,560 63,080 25,480 354,240 6,370 3,185 708,480
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CLB Overview
O6 output (see Fast Lookahead Carry Logic), feed the D input of the storage element, or go
to F7AMUX/F7BMUX from O6 output.
In addition to the basic LUTs, slices contain three multiplexers (F7AMUX, F7BMUX, and
F8MUX). These multiplexers are used to combine up to four function generators to provide
any function of seven or eight inputs in a slice. F7AMUX and F7BMUX are used to
generate seven input functions from LUTs A and B, or C and D, while F8MUX is used to
combine all LUTs to generate eight input functions. Functions with more than eight inputs
can be implemented using multiple slices. There are no direct connections between slices
to form function generators greater than eight inputs within a CLB.
Storage Elements
As in previous Virtex architectures, there are four (original) storage elements in a slice that
can be configured as either edge-triggered D-type flip-flops or level-sensitive latches. The
D input can be driven directly by a LUT output via AFFMUX, BFFMUX, CFFMUX or
DFFMUX, or by the BYPASS slice inputs bypassing the function generators via AX, BX, CX,
or DX input. When configured as a latch, the latch is transparent when the CLK is Low.
In Virtex-6 devices, there are now four additional storage elements that can only be
configured as edge-triggered D-type flip-flops. The D input can be driven by the O5 output
of the LUT or the BYPASS slice inputs via AX, BX, CX, or DX input. When the original 4
storage elements are configured as latches, these 4 additional storage elements can not be
used.
The control signals clock (CLK), clock enable (CE), and set/reset (SR) are common to all
storage elements in one slice. When one flip-flop in a slice has SR or CE enabled, the other
flip-flops used in the slice will also have SR or CE enabled by the common signal. Only the
CLK signal has independent polarity. Any inverter placed on the clock signal is
automatically absorbed. The CE and SR signals are active High. All flip-flop and latch
primitives have CE and non-CE versions.
The SR signal forces the storage element into the state specified by the attribute SRHIGH or
SRLOW. SRHIGH forces a logic High at the storage element output when SR is asserted,
while SRLOW forces a logic Low at the storage element output (see Table 3).
Figure 5 shows both the register only and the register/latch configuration in a slice.
Ta b le 3 : Truth Table when using SRLOW and SRHIGH
SR SRVAL Function
0 SRLOW (default) No Logic Change
1SRLOW(default)0
0 SRHIGH No Logic Change
1SRHIGH1
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CLB Overview
SRHIGH and SRLOW can be set individually for each storage element in a slice. The choice
of synchronous (SYNC) or asynchronous (ASYNC) set/reset (SRTYPE) cannot be set
individually for each storage element in a slice.
The initial state after configuration or global initial state is defined by separate INIT0 and
INIT1 attributes. By default, setting the SRLOW attribute sets INIT0, and setting the
SRHIGH attribute sets INIT1. Virtex-6 devices can set INIT0 and INIT1 independent of
SRHIGH and SRLOW.
The configuration options for the set and reset functionality of a register or the four storage
elements capable of functioning as a latch are as follows:
• No set or reset
•Synchronousset
• Synchronous reset
• Asynchronous set (preset)
• Asynchronous reset (clear)
X-Ref Target - Figure 5
Figure 5: Two Versions of Configuration in a Slice: 4 Registers Only and 4 Register/Latch
ug364_05_040209
DX
CX
BX
CE
AX
DQ
CQ
BQ
AQ
D
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
SR
DFF/LATCH
LUT D Output
LUT C Output
CE
CK
D
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
SR
CE
CK
D
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
SR
CE
CK
D
FF
LATCH
INIT1
INIT0
SRHIGH
SRLOW
SR
Q
CE
CK
Q
Q
Q
SR
LUT B Output
LUT A OutputAFF/LATCH
BFF/LATCH
CFF/LATCH
CLK
Reset Type
Sync
Async
DX
CX
BX
CE
AX
DQ
CQ
BQ
AQ
D
SR
DFF
LUT D O5 Output
LUT C O5 Output
CE
CK
INIT1
INIT0
SRHIGH
SRLOW
INIT1
INIT0
SRHIGH
SRLOW
INIT1
INIT0
SRHIGH
SRLOW
INIT1
INIT0
SRHIGH
SRLOW
D
SR
CE
CK
D
SR
CE
CK
D
SR
Q
CE
CK
Q
Q
Q
SR
LUT B O5 Output
LUT A O5 OutputAFF
BFF
CFF
CLK
Reset Type
Sync
Async
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CLB Overview
Distributed RAM and Memory (Available in SLICEM only)
Multiple LUTs in a SLICEM can be combined in various ways to store larger amount of
data.
The function generators (LUTs) in SLICEMs can be implemented as a synchronous RAM
resource called a distributed RAM element. RAM elements are configurable within a
SLICEM to implement the following:
• Single-Port 32 x 1-bit RAM
• Dual-Port 32 x 1-bit RAM
• Quad-Port 32 x 2-bit RAM
• Simple Dual-Port 32 x 6-bit RAM
• Single-Port 64 x 1-bit RAM
• Dual-Port 64 x 1-bit RAM
• Quad-Port 64 x 1-bit RAM
• Simple Dual-Port 64 x 3-bit RAM
• Single-Port 128 x 1-bit RAM
• Dual-Port 128 x 1-bit RAM
• Single-Port 256 x 1-bit RAM
Distributed RAM modules are synchronous (write) resources. A synchronous read can be
implemented with a storage element or a flip-flop in the same slice. By placing this flip-flop,
the distributed RAM performance is improved by decreasing the delay into the clock-to-out value of
the flip-flop. However, an additional clock latency is added. The distributed elements share the
same clock input. For a write operation, the Write Enable (WE) input, driven by either the
CE or WE pin of a SLICEM, must be set High.
Table 4 shows the number of LUTs (four per slice) occupied by each distributed RAM
configuration.
Ta b le 4 : Distributed RAM Configuration
RAM Number of LUTs
32 x 1S 1
32 x 1D 2
32 x 2Q(2) 4
32 x 6SDP(2) 4
64 x 1S 1
64 x 1D 2
64 x 1Q(3) 4
64 x 3SDP(3) 4
128 x 1S 2
128 x 1D 4
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CLB Overview
For single-port configurations, distributed RAM has a common address port for
synchronous writes and asynchronous reads. For dual-port configurations, distributed
RAM has one port for synchronous writes and asynchronous reads, and another port for
asynchronous reads. In simple dual-port configuration, there is no data out (read port)
from the write port. For quad-port configurations, distributed RAM has one port for
synchronous writes and asynchronous reads, and three additional ports for asynchronous
reads.
In single-port mode, read and write addresses share the same address bus. In dual-port
mode, one function generator is connected with the shared read and write port address.
The second function generator has the A inputs connected to a second read-only port
address and the WA inputs shared with the first read/write port address.
Figure 6 through Figure 14 illustrate various example distributed RAM configurations
occupying one SLICEM. When using x2 configuration (RAM32X2Q), A6 and WA6 are
driven High by the software to keep O5 and O6 independent.
256 x 1S 4
Notes:
1. S = single-port configuration; D = dual-port configuration; Q = quad-port configuration; SDP = simple
dual-port configuration.
2. RAM32M is the associated primitive for this configuration.
3. RAM64M is the associated primitive for this configuration.
Ta b le 4 : Distributed RAM Configuration (Cont’d)
RAM Number of LUTs
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16 www.xilinx.com Virtex-6 FPGA CLB User Guide
UG364 (v1.2) February 3, 2012
CLB Overview
X-Ref Target - Figure 6
Figure 6: Distributed RAM (RAM32X2Q)
ug364_06_080609
DI1 DOD[0]
DOC[0]
DOD[1]
DOC[1]
DOB[0]
DOB[1]
DOA[0]
DOA[1]
DI2
DID[1]
DID[0]
ADDRD[4:0]
ADDRC[4:0]
ADDRB[4:0]
ADDRA[4:0]
WCLK
WED
(CLK)
(WE)
5
5
DPRAM32
RAM 32X2Q
A[6:1]
WA[6:1]
CLK
WE
O6
O5
DI1
DI2
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DI2
DI2
B[5:1]
C[5:1]
D[5:1]
(AX/BX/CX/DX)
(DI)
A[5:1]
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
O5
O5
O5
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Virtex-6 FPGA CLB User Guide www.xilinx.com 17
UG364 (v1.2) February 3, 2012
CLB Overview
X-Ref Target - Figure 7
Figure 7: Distributed RAM (RAM32X6SDP)
ug364_07_080609
DI1
O[2]
O[1]
O[4]
O[3]
O[6]
O[5]
DI2
unused
unused
WADDR[5:1]
WADDR[6] = 1
RADDR[5:1]
RADDR[6] = 1
DATA[1]
DATA[2]
DATA [ 3]
DATA[4]
DATA[5]
DATA[6]
WCLK
WED
(CLK)
(WE)
5
5
DPRAM32
RAM 32X6SDP
A[6:1]
WA[6:1]
CLK
WE
DI1
DI2
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DI2
DI2
B[5:1]
C[5:1]
D[5:1]
A[5:1]
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
5
5
DPRAM32
A[6:1]
WA[6:1]
CLK
WE
O6
O5
O5
O5
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18 www.xilinx.com Virtex-6 FPGA CLB User Guide
UG364 (v1.2) February 3, 2012
CLB Overview
If four single-port 64 x 1-bit modules are built, the four RAM64X1S primitives can occupy
a SLICEM, as long as they share the same clock, write enable, and shared read and write
port address inputs. This configuration equates to 64 x 4-bit single-port distributed RAM.
If two dual-port 64 x 1-bit modules are built, the two RAM64X1D primitives can occupy a
SLICEM, as long as they share the same clock, write enable, and shared read and write port
address inputs. This configuration equates to 64 x 2-bit dual-port distributed RAM.
X-Ref Target - Figure 8
Figure 8: Distributed RAM (RAM64X1S)
X-Ref Target - Figure 9
Figure 9: Distributed RAM (RAM64X1D)
ug364_08_080609
Output
Registered
Output
(Optional)
DI1
DQ
(DI)
D
A[5:0]
WCLK
WE
(D[6:1])
(CLK)
(WE/CE)
6
SPRAM64
RAM64X1S
A[6:1]
WA[6:1]
CLK
WE
O6 O
6
ug364_09_080609
DI1
(DI)
D
A[5:0]
WCLK
WE
(D[6:1])
(CLK)
(WE/CE)
6
6
DPRAM64
RAM64X1D
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DPRA[5:0] (C[6:1]) 6
6
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
Registered
Output
(Optional)
DQ
SPO
Registered
Output
(Optional)
DQ
DPO
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Virtex-6 FPGA CLB User Guide www.xilinx.com 19
UG364 (v1.2) February 3, 2012
CLB Overview
X-Ref Target - Figure 10
Figure 10: Distributed RAM (RAM64X1Q)
ug364_10_080609
DI1
DID
ADDRD
ADDRC
ADDRB
ADDRA
WCLK
WE
(CLK)
(WE)
DPRAM64
RAM64X1Q
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
(B[6:1])
(C[6:1])
(D[6:1])
(DI)
(A[6:1])
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
Registered
Output
DOD
DOC
DOB
DOA
(Optional)
DQ
Registered
Output
(Optional)
DQ
Registered
Output
(Optional)
DQ
Registered
Output
(Optional)
DQ
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20 www.xilinx.com Virtex-6 FPGA CLB User Guide
UG364 (v1.2) February 3, 2012
CLB Overview
Implementation of distributed RAM configurations with depth greater than 64 requires the
usage of wide-function multiplexers (F7AMUX, F7BMUX, and F8MUX).
X-Ref Target - Figure 11
Figure 11: Distributed RAM (RAM64X3SDP)
ug364_11_080609
DI1
O[1]
O[2]
O[3]
DI2
unused
unused
WADDR[6:1]
RADDR[6:1]
DATA[1]
DATA[2]
DATA [ 3]
WCLK
WED
(CLK)
(WE)
6
6
DPRAM64
RAM 64X3SDP
A[6:1]
WA[6:1]
CLK
WE
DI1
DI2
6
6
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
DI2
DI2
B[6:1]
C[6:1]
D[6:1]
A[6:1]
6
6
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
DI1
6
6
DPRAM64
A[6:1]
WA[6:1]
CLK
WE
O6
O5
O5
O5
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