Xilinx Virtex UltraScale FPGA VCU1287 User manual

VCU1287
Characterization Board
User Guide
UG1121 (v1.0) December 11, 2015

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UG1121 (v1.0) December 11, 2015
Revision History
The following table shows the revision history for this document.
Date Version Revision
12/11/2015 1.0 Initial Xilinx release.
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Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 1: Introduction
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
FPGA Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: Board Setup and Configuration
Board Component Location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 3: Board Component Descriptions
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Component Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Appendix A: Default Jumper Settings
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Appendix B: VITA 57.1 FMC Connector Pinouts
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Appendix C: Master Constraints File Listing
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
VCU1287 Board XDC Listing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Appendix D: System Controller
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Programmable Clocks Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PMBus Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Power Monitoring Data Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
FPGA Mezzanine Card (FMC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
GPIO Data Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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Board EEPROM Data Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
FPGA CONFIG Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Appendix E: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
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UG1121 (v1.0) December 11, 2015
Chapter 1
Introduction
Overview
This user guide describes the components, features, and operation of the VCU1287
UltraScale® FPGA GTH and GTY transceivers characterization board. The VCU1287 board
provides the hardware environment for characterizing and evaluating the GTH and GTY
transceivers available on the UltraScale XCVU095-FFVB2104E FPGA. The VCU1287 board
schematic, bill-of-material (BOM), layout files, and reference designs are available online at
the VCU1287 Characterization Kit website.
FPGA Compatibility
The VCU1287 board is provided with the Virtex UltraScale XCVU095-FFVB2104E FPGA. The
board also supports other Virtex UltraScale device densities (XCVU080, XCVU125, and
XCVU160), as well as the Kintex® UltraScale XCKU115 device in the pin-compatible
FFVB2104 package. However, some transceivers available in large density devices are not
available in the XCVU095 device (for example, GTH QUAD_232 and QUAD_233).
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Chapter 1: Introduction
Block Diagram
The VCU1287 board block diagram is shown in Figure 1-1.
X-Ref Target - Figure 1-1
Figure 1-1: VCU1287 Board Block Diagram
Power In
12VDC
Board Utility Power
On-Board Power Regulation:
5.0V, 12A
3.3V, 40A
2.5V, 4A
System Controller
MGT Transceivers
QUAD 124
QUAD 125
QUAD 126
QUAD 127
QUAD 128
QUAD 129
QUAD 130
QUAD 131
QUAD 224
QUAD 225
QUAD 226
QUAD 227
QUAD 228
QUAD 229
QUAD 230
QUAD 231 UltraScale FPGA
XCVU095-FFVB2104E
Analog/Digital
Converter
(SYSMON)
FPGA Power Source
On-Board Regulation:
VCCINT 0.95V, 60A
VCCBRAM 0.95V, 7A
VCCAUX 1.8V, 8A
VCCO_HP 1.8V, 10A
VCCO_HR 1.8V, 2.5A
USB to UART
Bridge
Select I/O
Termination
I2C Bus
Management
FMC1 Interface
High Performance
I/O
FMC2 Interface
High Performance
I/O
FMC3 Interface
High Performance
I/O
GTY Power
Module
Interface for
Quads 124-131
GTH Power
Module
Interface for
Quads 224-231
MGT
Power Monitoring
Push Buttons,
DIP Switches,
And LEDs
User Clocks
SuperClock-2
Module Interface
12V
5V
3.3V
12V
5V
3.3V
PMBus
PMBus
PMBus
2.5V
5V
3.3V
VCCO_HP
;
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Chapter 1: Introduction
Board Features
The VCU1287 characterization board features are listed here. Detailed information for each
feature is provided in Chapter 3, Board Component Descriptions.
• UltraScale XCVU095-FFVB2104E FPGA
• BullsEye cable access to all 32 GTH and 32 GTY transceivers on the UltraScale
XCVU095-FFVB2104E FPGA
• Onboard power supplies for all necessary voltages
• Power connectors for optional use of external power supplies
• Digilent USB JTAG programming port
• System controller (Zynq-7000 AP SoC XC7Z010-CLG225 FPGA)
• Two MGT power modules supporting UltraScale FPGA GTY and GTH transceiver power
requirements
• A fixed 300 MHz 2.5V LVDS oscillator wired to multi-region clock capable (MRCC)
inputs
• Two pairs of differential MRCC inputs with SMA connectors
• SuperClock-2 module supporting programmable clock outputs
• Samtec BullsEye connector pads for the GTY and GTH transceivers and reference clocks
• General purpose DIP switches, LEDs, pushbuttons, and test I/O
• Three VITA 57.1 FPGA mezzanine card (FMC) high pin count (HPC) connectors
• USB-to-UART bridge
•I2Cbus
• PMBus connectivity to the boards digital power supplies
• Active cooling for the FPGA
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Chapter 2
Board Setup and Configuration
Board Component Location
Figure 2-1 shows the VCU1287 board component locations. Each numbered component
shown in the figure is keyed to Table 2-1. Table 2-1 identifies the components and links to
a detailed functional description of the components and board features in Chapter 3, Board
Component Descriptions.
IMPORTANT: Figure 2-1 is for visual reference only and might not reflect the current revision of the
board.
CAUTION! The VCU1287 board can be damaged by electrostatic discharge (ESD). Follow standard ESD
prevention measures when handling the board.
CAUTION! Do not remove the rubber feet from the board. The feet provide clearance to prevent short
circuits on the back side of the board.
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Chapter 2: Board Setup and Configuration
X-Ref Target - Figure 2-1
Figure 2-1: VCU1287 Characterization Board Components
11
19
26
27
28
29
20
19
38
37
23
151413
303132
12
19
22
19
21
17
40
25
16
18
1
5435
39
7
33
19
2
34
36
24 986
3
10
19
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Chapter 2: Board Setup and Configuration
Table 2-1: VCU1287 Board Components
Callout Reference Designator Feature Description
1U1Virtex UltraScale XCVU095-FFVB2104E Device
2SW1Power Switch
3 J28 12V mini-fit connector (12V Input Power)
4J37, J155, J38, J80, J39,
J82, J141, J142, J71
GTY transceiver connector pads Q124, Q125, Q126, Q127, Q128,
Q129, Q130, Q131, Q132 (MGT Transceivers and Reference
Clocks)
5J40, J88, J89, J41, J42,
J92, J43, J156, J143, J68
GTH transceiver connector pads Q224, Q225, Q226, Q227, Q228,
Q229, Q230, Q231, Q232, Q233 (MGT Transceivers and
Reference Clocks)
6U80
Digilent USB JTAG connector (micro-B receptacle) (A list of
jumpers and switches and their required positions for normal
board operation is provided in Appendix A, Default Jumper
Settings.)
7J2
Platform USB JTAG connector (alternate access for programming
cables) (A list of jumpers and switches and their required
positions for normal board operation is provided in Appendix A,
Default Jumper Settings.)
8J10
SD card connector (back-side of board) (A list of jumpers and
switches and their required positions for normal board
operation is provided in Appendix A, Default Jumper Settings.)
9SW13System Controller Configuration DIP Switches
10 SW4 System Controller Reset
11 J36 SuperClock-2 Module
12 U42 300 MHz LVDS Oscillator
13 DS17 FPGA DONE status LED (DONE LED)
14 DS3 FPGA INIT_B status LED (INIT LED)
15 SW7 FPGA PROG_B pushbutton (PROGRAM Pushbutton)
16 DS18 12V power status LED (Power Switch)
17
DS4, DS5, DS6, DS7,
DS8, DS9, DS10, DS11,
DS13, DS14, DS15,
DS28, DS29, DS30,
DS32
Status LEDs for FPGA logic, transceiver, and utility power
18 SW2 Power regulation inhibitor switch for onboard regulators (Using
External Power Sources)
19 J5, J18, J19, J20, J22,
J23, J26, J27, J67, J69
External power supply connectors (Using External Power
Sources)
20 J93, J138
Bank 124-132 GTY transceiver power supply module (Onboard
Power Regulation and A list of jumpers and switches and their
required positions for normal board operation is provided in
Appendix A, Default Jumper Settings.)
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