Xilinx VIODC User manual

R
Video
Input/Output
Daughter Card
User Guide
UG235 (v1.2.1) October 31, 2007
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Revision History
Video Input/Output Daughter Card
UG235 (v1.2.1) October 31, 2007
The following table shows the revision history for this document.
R
Version Revision
01/25/06 1.0 Initial Xilinx release.
02/13/06 1.1 Added two sentences to pages 17 and 43.
02/23/07 1.2 Corrected 3 pins and column 6 heading in Table A-2.
10/31/07 1.2.1 Defined the following acronyms on p. 48: EAV, CRC, NTSC, and PAL.
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Contents
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 1: VIODC Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Video Interface Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 2: VIODC to ML402 Card Interface
VIOBUS Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VIOBUS Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 3: Component and S-Video Interfaces
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ADV7403 Video Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ADV7321 Video Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Video Signal Input and Output Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
S-Video Input and Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
S-Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
S-Video Input Signal Conditioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ADV7403 S-Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
S-Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
ADV7321 S-Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
S-Video Output Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Composite Video Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Composite Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Composite Video Input Conditioning Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ADV7403 Composite Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Composite Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ADV7321A Composite Video Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Composite Video Conditioning Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Component Video Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Component Video Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input Signal Conditioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ADV7403 Connection to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Component Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FPGA to ADV7321 Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Analog Output Signal Conditioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ADV7403 Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ADV7321A Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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Chapter 4: DVI/VGA Input Interface
Interface Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DVI Connectivity on VIODC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DVI Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
VGA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Display Data Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AD9887 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
VGA Standard Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Setting the PLL and Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Setting Black Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Setting Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DVI Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
I2C Initialization Table (in Hex). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
References to VGA, DVI Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 5: DVI/VGA Output Interface
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
TPF410 I2C Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Chapter 6: SDI Interface
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reference Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SDI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PicoBlaze Controller for the ADV7321B Video Encoder . . . . . . . . . . . . . . . . . . . . . . 45
SDI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 7: Image Sensor Camera Interface
LVDS Camera Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Camera Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 8: Attaching the VIODC to the ML40x Development Board
Appendix A: Reference Information
Schematic and Data Sheet Links. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
VIOBUS Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Appendix B: VSK I/O Connector Location Pictures
VIODC Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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LVDS Camera. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ML402 Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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Schedule of Figures
Chapter 1: VIODC Overview
Figure 1-1: VIODC Attached to an ML402 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 1-2: VIODC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chapter 2: VIODC to ML402 Card Interface
Figure 2-1: VIOBUS Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 3: Component and S-Video Interfaces
Figure 3-1: S-Video, Composite, and Component Video Input and Output Block
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3-2: S-Video, Composite, and Component Input and Output Signal
Conditioning Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3-3: Component Video Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 3-4: Connections from ADV7403 Video Decoder to XC2VP4 FGPA . . . . . . . . . . . 27
Figure 3-5: Component Video Output Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 4: DVI/VGA Input Interface
Figure 4-1: DVI Connectivity on VIODC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 4-2: VGA Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 4-3: Synchronization Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 4-4: Pixel Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 4-5: Ideal ADC Sampling Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Chapter 5: DVI/VGA Output Interface
Figure 5-1: DVI/VGA Video Output Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . 41
Chapter 6: SDI Interface
Figure 6-1: SDI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 6-2: ADV7321B Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 6-3: SDI Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chapter 7: Image Sensor Camera Interface
Figure 7-1: LVDS Camera Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7-2: Camera Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Chapter 8: Attaching the VIODC to the ML40x Development Board
Figure 8-1: Configuration Jumper Locations on the ML40x Bottom,
Configured for VIODC Mounted to an ML402 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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Figure 8-2: Configuration Jumper Locations on the VIODC Top,
Configured for VIODC Mounted to an ML402 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Appendix A: Reference Information
Appendix B: VSK I/O Connector Location Pictures
Figure B-1: VIODC Rear View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure B-2: VIODC Left Side View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure B-3: VIODC Right Side View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure B-4: LVDS Camera. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure B-5: ML402 Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure B-6: ML402 Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
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Schedule of Tables
Chapter 1: VIODC Overview
Chapter 2: VIODC to ML402 Card Interface
Table 2-1: VIOBUS Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 3: Component and S-Video Interfaces
Table 3-1: Configuration Modes for ADV7403 Video Decoder Chip. . . . . . . . . . . . . . . . . 28
Table 3-2: Configuration Modes for ADV7321A Video Encoder Chip . . . . . . . . . . . . . . . 30
Chapter 4: DVI/VGA Input Interface
Table 4-1: VGA Standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 4-2: Analog VGA60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 4-3: Analog XGA60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 4-4: Analog SXGA60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 4-5: Analog UXGA60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 4-6: DVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 5: DVI/VGA Output Interface
Table 5-1: Configuration Modes for TPF410 I2C Video Encoder Chip . . . . . . . . . . . . . . . 42
Chapter 6: SDI Interface
Table 6-1: RocketIO Reference Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 6-2: ADV7321B Register Settings for HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 6-3: ADV7321B HD Mode Register 1 (0x10) Settings by Video Format . . . . . . . . . 47
Table 6-4: ADV7321B Register Settings for NTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 6-5: ADV7321B Register Settings for PAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Chapter 7: Image Sensor Camera Interface
Table 7-1: Camera Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 8: Attaching the VIODC to the ML40x Development Board
Table 8-1: Required Jumper Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Appendix A: Reference Information
Table A-1: VIODC ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table A-2: VIOBUS Signals XGI Header Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table A-3: VIOBUS ML402 FPGA Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table A-4: VIOBUS VIODC FPGA Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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Preface
About This Guide
This guide describes the Video Input and Output Daughter Card (VIODC), a standard
video interface card that is compatible with the Xilinx ML401, ML402, and ML403
development platforms.
Guide Contents
This manual contains the following chapters:
•Chapter 1, “VIODC Overview” – provides an overview of the VIODC, interfaces, and
I/Os.
•Chapter 2, “VIODC to ML402 Card Interface” – describes the VIODC to ML402 card
interface.
•Chapter 3, “Component and S-Video Interfaces” – describes the High Definition (HD)
and Standard Definition (SD) component video and S-video interfaces.
•Chapter 4, “DVI/VGA Input Interface” – provides an overview of the VGA and DVI
input interface.
•Chapter 5, “DVI/VGA Output Interface”– provides an overview of the VGA and DVI
output interface.
•Chapter 6, “SDI Interface”– provides an overview of the SDI video interface.
•Chapter 7, “Image Sensor Camera Interface”– describes the Irvine Sensors LVDS RGB
camera interface.
•Chapter 8, “Attaching the VIODC to the ML40x Development Board” – provides
information necessary for proper attachment of the VIODC to a ML40xdevelopment
board.
•Appendix A, “Reference Information”– contains VIODC pinout information.
•Appendix B, “VSK I/O Connector Location Pictures” – shows I/O connection
locations.
Additional Resources
To find additional documentation, see the Xilinx website at:
http://www.xilinx.com/literature/index.htm.
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support Web Case, see the Xilinx website at:
http://www.xilinx.com/support.
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Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention Meaning or Use Example
Courier font
Messages, prompts, and
program files that the system
displays
speed grade: - 100
Courier bold Literal commands that you
enter in a syntactical statement ngdbuild design_name
Helvetica bold
Commands that you select
from a menu File →Open
Keyboard shortcuts Ctrl+C
Italic font
Variables in a syntax
statement for which you must
supply values
ngdbuild design_name
References to other manuals
See the Development System
Reference Guide for more
information.
Emphasis in text
If a wire is drawn so that it
overlaps the pin of a symbol,
the two nets are not connected.
Square brackets [ ]
An optional entry or
parameter. However, in bus
specifications, such as
bus[7:0], they are required.
ngdbuild [ option_name]
design_name
Braces { } A list of items from which you
must choose one or more lowpwr ={on|off}
Vertical bar | Separates items in a list of
choices lowpwr ={on|off}
Vertical ellipsis
.
.
.
Repetitive material that has
been omitted
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
Horizontal ellipsis . . . Repetitive material that has
been omitted
allow block block_name
loc1 loc2 ... locn;
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Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Blue text
Cross-reference link to a
location in the current
document
See the section “Additional
Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Red text Cross-reference link to a
location in another document See Figure 2-5 in the Handbook.
Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com
for the latest speed files.
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Chapter 1
VIODC Overview
Introduction
The Video Input and Output Daughter Card (VIODC) is a standard video interface card for
Xilinx development platforms. It is compatible with ML401, ML402, and ML403 boards
and other future Xilinx development platforms. The VIODC is shown in Figure 1-1
mounted on a ML402 platform. The VIODC provides access to high definition (HD) and
standard definition (SD) video streams, as well as computer graphics video interfaces,
such as VGA over DVI and SDI interfaces.
Figure 1-2 shows a block diagram of the VIODC card. The VIODC consists of a number of
video interface ICs connected to a Xilinx XCV2P7 FPGA. The VIODC is a daughter card
which plugs onto a Xilinx ML40x FPGA platform via the XGI connector. The XGI connector
provides a 64-signal bus between the ML40xand the VIODC. Collectively these signals are
called the VIOBUS in this document.
Figure 1-1: VIODC Attached to an ML402 Platform
UG239_01_122005
DVI out
VGA out
Video
DVI in
Power
ML402 MOTHERBOARD
XCV4SX35
VGA in LVDS Camera
SDI in
SDI out
S-Video
VIDEO IO
DAUGHTER CARD
JTAG
Compact Flash
Component
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Video Interface Support
The VIODC supports the following video interfaces:
•LVDS Camera Input Port – The LVDS camera input port supports the Irvine Sensors
LVDS RGB camera with a Micron MT9V022 1/3 inch CMOS image sensor. The camera
provides 752 x 480 pixels at 60 Hz progressive scan. It features low noise and very
high dynamic range. The interface is implemented using LVDS signaling over
standard Cat-6 Ethernet cables. Note that the LVDS camera interface is not compatible
with Ethernet.
•S-Video and Composite Video – The VSK supports S-Video inputs and outputs.
These interfaces can be configured to support NTSC, PAL, and virtually any other SD
video format. The S-video input interface is supported by the ADV7403 decoder IC
and output by the ADV7321 encoder IC. In addition to the encoder and decoder,
analog filters are used to limit the video bandwidth.
•Component Video I/O – The component video I/O use standard RCA connectors to
provide HD video the VSK. Component video is encoded as YPbPr video channels.
The component video input on the supports 1080I, 720P, and 525P video standards.
The Component video interface devices on the VSK support 10-bit digital video.
Component video input is supported by the ADV7403 IC decoder IC and output by
the ADV7321 encoder IC and analog filter sections.
•DVI Digital Video I/O – The VSK supports DVI video inputs and outputs. DVI is
commonly used to interface to flat panel displays and computer graphics cards. The
VSK DVI interfaces supports up to a pixel clock of up to 165 MHz. In addition to
computer graphics, DVI is also used to carry HD video and is commonly found in
high-end consumer video equipment, such as plasma displays, and can be found on
some DVD players. The DVI ports can also be connected to HDMI interfaces by using
a DVI/HDMI adapter. A TP410 IC is used to support DVI output and an AD9887 IC
provides DVI input.
•VGA Interface – VGA input and outputs are is available on the VIODC card. The
VGA output is routed to the analog output pins of the DVI output connector. It is
sourced by an ADV7123 10-bit DAC. VGA input is captured by the AD9887 IC.
Figure 1-2: VIODC Block Diagram
VIODC
XCV2P7
FPGA
/
SDI Interface I/O
Clock
Composite Video I/O
S-Video I/O
Component Video I/O
LVDS Camera
DVI I/O
VGA I/O
VIOBUS
XGI
Connector
ug235_ch1_02_011306
ML402
Platform
64
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Video Interface Support
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•SDI Video Interface – A complete SDI video interface capable of supporting both SD
and HD video rates is available on the VSK. The SDI standard is a high-speed serial
interface used to carry digital video over coax cable. It is generally used in a studio
environment. The SDI system includes cable equalizers and Genlock circuitry. (The
VSK is a demonstration platform only. For HD-SDI verification and compliance,
Xilinx recommends using the Cook Technologies SDV board).
•Clock Generator – The clock generator section is used to generate standard video
clock frequencies. It is based on an ICS 1523 clock generator IC.
•XCV2P7 FPGA – The VSK also includes a Xilinx XCV2P7 FPGA, which is used to
interface to the various video interfaces, as well as the ML402 main board. It features
Multi-Gigabit Transceivers (MGTs), which are used to support the SDI interface. It
also enables the VIODC to be used in a stand-alone fashion.
•XGI Connector– The XGI connector is a standard connector interface used on XiIinx
ML40xFPGA development platforms. The XGI connector is used to connect to the
VIODC to a standard FPGA development platform, such as the ML402. The signals
consist of 32 single-ended LVCMOS25 signals and 32 signals that can be configured as
either 32 LVCMOS25 signals or 16 LVDS signal pairs. The LVDS pairs are length
matched and routed as pairs on the PCB. In addition, 5V power is passed up to the
VIODC over the XGI connector.
•VIOBUS – The Video Starter Kit (VSK) uses the VIODC as a Video I/O interface. For
compatibility with the VSK, the 64 XGI signals have been specified as a bus named the
VIOBUS. In this use, the signals on the VIODC XGI connector have been specified as a
set of buses that transmit a27-bit digital video channel from the VIODC to the FPGA
development platform and a 27-bit bus to transmit a similar digital video channel
from the ML40xto the VIODC. Each video channel consists of a 24-bit digital video
bus, HSYNC, VSYNC and a clock enable signal. The pinout for the VIOBUS can be
found in Appendix A, “Reference Information.” This implementation of the interface
runs synchronous to the interface clock supplied by the ML402 board. The VIOBUS
also specifies an LVDS clock, a reset signal, an I2C interface, and a 4-pin serial bus.
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Chapter 2
VIODC to ML402 Card Interface
When the VIODC is used as part of the Video Starter Kit (VSK) from Xilinx, the 64-pin XGI
connector connects the VIODC to a ML402 card to communicate with the VIODC card.
When the VIODC is used with the VSK, the 64 XGI signals are allocated to a bus named the
VIOBUS, which serves the following functions:
•Transfers video data between the ML402 card and the VIODC card.
•Provides a clock to the VIODC card.
•Provides reset to the VIODC card.
•Provides a low-pin count serial bus to access registers on the VIODC.
•Provides an I2C bus (an industry standard 2-pin serial data bus used to communicate
and configure ICs) to access registers on the VIODC video interface FPGA.
VIOBUS Clocking
The VIOBUS uses a simple synchronous interface running at 100 MHz (Figure 2-1).
A clock is passed from the ML402 FPGA to the VIODC using differential signaling. All
data signals are single ended. The VIODC transmits data back to the ML402 FPGA using
the received clock. Data returning back from the VIODC is clocked into the ML402 FPGA
using the internal 100 MHz clock.
Future VIODC bus interfaces may implement a differential bus using the 16 differential
pairs available on HDR2 and more sophisticated clocking.
Figure 2-1: VIOBUS Clocking
ML402 XC4VSX35 VIODC XC2VP7
CMOS25
CMOS25
OBUF
OBUF IBUF +
Delay
Idelay
LVDS
100 MHz
Clock
BUFG
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VIOBUS Signal Definitions
Refer to the VIOBUS pinout in Appendix A, “Reference Information” for signal locations.
Table 2-1: VIOBUS Signal Definitions
Signal Description nbits Type Targ et
Speed
Source
FPGA XGI Pins
VIO Data Bus (a moderate-speed single-ended bus)
vio_up[25:0] Data bus to the VIODC 26 LVCMOS25 100 MHz ML402 hdr1[20:2],
hdr2[2:32]
vio_up_ena Pixel enable for
vio_up[25:0]
1 LVCMOS25 100 Mhz ML402 hdr1[22]
vio_dn[25:0] Data bus from the VIODC 26 LVCMOS25 100 MHz VIODC hdr1[42:24],
hdr2[64:34]
vio_dn_ena Pixel enable for
vio_up[25:0]
1 LVCMOS25 100 MHz VIODC hdr1[44]
Sport Serial Bus (used to configure registers in the VIODC FPGA)
vio_sport_up Sport write data (16-bit
data, 16-bit address)
1 LVCMOS25 10 MHz ML402 hdr1[54]
vio_sport_dn Sport return data 1 LVCMOS25 10 MHz VIODC hdr1[52]
vio_sport_sync Sport sync pulse 1 LVC MOS25 10 MHz ML402 hdr1[50]
vio_sport_clk Sport clock 1 LVCMOS25 10 MHz ML402 hdr1[48]
I2C Serial Bus (used to configure registers in the video devices)
vio_i2c_sda_up I2C write data 1 LVCMOS25 400 kHz ML402 hdr1[60]
vio_i2c_sda_dn I2C return data 1 LVCMOS25 400 kHz VIODC hdr1[58]
vio_i2c_scl_up I2C clock signal 1 LVCMOS25 400 kHz ML402 hdr1[56]
Miscellaneous
vio_reset Active High reset to
VIODC
1 LVCMOS25 10 MHz ML402 hdr1[46]
Clock
vio_up_clk_lvds_P,N 1 LVDS25 400 MHz ML402 hdr1[64:62]]
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