Xilinx LogiCORE IP AXI User manual

LogiCORE IP AXI
Bridge for PCI Express
v2.4
Product Guide
Vivado Design Suite
PG055 June 4, 2014

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PG055 June 4, 2014
Table of Contents
IP Facts
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bridge Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Parameter Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Chapter 3: Designing with the Core
General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Shared Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
AXI Transactions for PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Transaction Ordering for PCIe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Malformed TLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Abnormal Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Root Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Chapter 4: Design Flow Steps
Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 5: Example Design
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Simulation Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Implementation Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Example Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Example Design Output Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Chapter 6: Test Bench
Appendix A: Migrating and Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Simulation Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Transceiver Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Interface Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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Introduction
The Xilinx®LogiCORE™ IP AXI Root Port/
Endpoint (RP/EP) Bridge for PCI Express® core
is an interface between the AXI4 and PCI
Express. Definitions and references are
provided in this document for all of the
functional modules, registers, and interfaces
that are implemented in the AXI Bridge for PCI
Express core. Definitions are also provided for
the hardware implementation and software
interfaces to the AXI Bridge for PCI Express core
in supported FPGA devices.
Features
• Zynq®-7000, Kintex®-7, Virtex®-7, and
Artix®-7 FPGA Integrated Blocks for PCI
Express
• Maximum Payload Size (MPS) up to 256 bytes
• Multiple Vector Messaged Signaled Interrupts
(MSIs)
•Legacyinterruptsupport
• Memory-mapped AXI4 access to PCIe® space
• PCIe access to memory-mapped AXI4 space
• Tracks and manages Transaction Layer Packets
(TLPs) completion processing
• Detects and indicates error conditions with
interrupts
• Optimal AXI4 pipeline support for enhanced
performance
• Compliant with Advanced RISC Machine
(ARM®) Advanced Microcontroller Bus
Architecture 4 (AMBA®) AXI4 specification
• Supports up to three PCIe 32-bit or 64-bit
PCIe Base Address Registers (BARs) as
Endpoint
• Supports a single PCIe 32-bit or 64-bit BAR as
Root Port
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family(1)
Zynq-7000, 7 Series(1)
Supported
User Interfaces AXI4
Resources See Ta b l e 2-2
Provided with Core
Design Files VHDL and Verilog
Example
Design Verilog
Test Bench Verilog
Constraints
File XDC
Simulation
Model Not Provided
Supported
S/W Driver(2) Standalone and Linux
Tested Design Flows(3)
Design Entry Vivado® Design Suite
Vivado IP integrator
Simulation For supported simulators, see the
Xilinx Design Tools: Release Notes Guide
Synthesis Vivado Synthesis
Support
Provided by Xilinx @ www.xilinx.com/support
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog. See also Table 2-1, page 11.
2. Standalone driver details can be found in the SDK directory
(<install_directory>/doc/usenglish/xilinx_drivers.htm). Linux
OS and driver support information is available from
wiki.xilinx.com.
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
4. Except for XC7VX485T, Virtex 7 devices are not supported.
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Chapter 1
Overview
The AXI Bridge for PCI Express® core is designed for the Vivado® IP integrator in the
Vivado Design Suite. The AXI Bridge for PCI Express core provides an interface between an
AXI4 customer user interface and PCI Express using the Xilinx Integrated Block for PCI
Express. The AXI Bridge for PCI Express core provides the translation level between the AXI4
embedded system to the PCI Express system. The AXI Bridge for PCI Express core translates
the AXI4 memory read or writes to PCIe Transaction Layer Packets (TLP) packets and
translates PCIe memory read and write request TLP packets to AXI4 interface commands.
The architecture of the AXI Bridge for PCI Express is shown in Figure 1-1.
X-Ref Target - Figure 1-1
Figure 1-1: High-Level AXI Bridge for PCI Express Architecture
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Chapter 1: Overview
Feature Summary
The AXI Bridge for PCI Express core is an interface between the AXI4 and PCI Express. It
contains the memory mapped AXI4 to AXI4-Stream Bridge and the AXI4-Stream Enhanced
Interface Block for PCIe. The memory-mapped AXI4 to AXI4-Stream Bridge contains a
register block and two functional half bridges, referred to as the Slave Bridge and Master
Bridge. The Slave Bridge connects to the AXI4 Interconnect as a slave device to handle any
issued AXI4 master read or write requests. The Master Bridge connects to the AXI4
Interconnect as a master to process the PCIe generated read or write TLPs. The core uses a
set of interrupts to detect and flag error conditions.
The AXI Bridge for PCI Express core supports both Root Port and Endpoint configurations.
• When configured as an Endpoint, the AXI Bridge for PCI Express core supports up to
three 32-bit or 64-bit PCIe Base Address Registers (BARs).
• When configured as a Root Port, the core supports a single 32-bit or 64-bit PCIe BAR.
The AXI Bridge for PCI Express core is compliant with the PCI Express Base Specification v2.0
[Ref 5] and with the AMBA® AXI4 specification [Ref 4].
Unsupported Features
The following features are not supported in the AXI Bridge for PCI Express core.
• Tandem PROM and Tandem PCIe
• Advanced Error Reporting (AER)
Limitations
Reference Clock for PCIe Frequency Value
The refclk input used by the serial transceiver for PCIe must be 100 MHz, 125 MHz, and
250 MHz for 7 series and Zynq®-7000 device configurations. The C_REF_CLK_FREQ
parameter is used to set this value, as defined in Table 2-4, page 15.
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Chapter 1: Overview
Licensing and Ordering Information
This Xilinx® LogiCORE™ IP module is provided at no additional cost with the Xilinx Vivado
Design Suite under the terms of the Xilinx End User License.
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information on pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.
For more information, visit the AXI Bridge for PCI Express product page.
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Chapter 2
Product Specification
Figure 2-1 shows the architecture of the AXI Bridge for PCI Express® core.
The Register block contains registers used in the AXI Bridge for PCI Express core for
dynamically mapping the AXI4 memory mapped (MM) address range provided using the
AXIBAR parameters to an address for PCIe range.
The Slave Bridge provides termination of memory-mapped AXI4 transactions from an AXI
master device (such as a processor). The Slave Bridge provides a way to translate addresses
that are mapped within the AXI4 memory mapped address domain to the domain addresses
for PCIe. When a remote AXI master initiates a write transaction to the Slave Bridge, the
write address and qualifiers are captured and write data is queued in a first in first out
(FIFO). These are then converted into one or more MemWr TLPs, depending on the
X-Ref Target - Figure 2-1
Figure 2-1: AXI Bridge for PCI Express Architecture
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Chapter 2: Product Specification
configured Max Payload Size setting, which are passed to the Integrated Block for PCI
Express.
A second remote AXI master initiated write request write address and qualifiers can then be
captured and the associated write data queued, pending the completion of the previous
write TLP transfer to the core. The resulting AXI Slave Bridge write pipeline is two-deep.
When a remote AXI master initiates a read transaction to the Slave Bridge, the read address
and qualifiers are captured and a MemRd request TLP is passed to the core and a
completion timeout timer is started. Completions received through the core are correlated
with pending read requests and read data is returned to the AXI master. The Slave bridge is
capable of handling up to eight memory mapped AXI4 read requests with pending
completions.
The Master Bridge processes both PCIe MemWr and MemRd request TLPs received from the
integrated block for PCI Express and provides a means to translate addresses that are
mapped within the address for PCIe domain to the memory mapped AXI4 address domain.
Each PCIe MemWr request TLP header is used to create an address and qualifiers for the
memory mapped AXI4 bus and the associated write data is passed to the addressed
memory mapped AXI4 Slave. The Master Bridge can support up to four active PCIe MemWr
request TLPs.
Each PCIe MemRd request TLP header is used to create an address and qualifiers for the
memory-mapped AXI4 bus. Read data is collected from the addressed memory mapped
AXI4 Slave and used to generate completion TLPs which are then passed to the integrated
block for PCI Express. The Master bridge can handle up to four read requests with pending
completions for improved AXI4 pipelining performance.
The instantiated AXI4-Stream Enhanced PCIe block contains submodules including the
Requester/Completer interfaces to the AXI bridge and the Register block. The Register
block contains the status, control, interrupt registers, and the AXI4-Lite interface.
Standards
The AXI Bridge for PCIe core is compliant with the ARM® AMBA® AXI4 Protocol
Specification [Ref 4] and the PCI Express Base Specification v2.0 [Ref 5].
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Chapter 2: Product Specification
Performance
Figure 2-2 shows a configuration diagram for a target FPGA.
The target FPGA is filled with logic to drive the lookup table (LUT) and block RAM utilization
to approximately 70% and the I/O utilization to approximately 80%.
Maximum Frequencies
The maximum frequency for the AXI clock is 125 MHz for 7 series FPGAs.
Line Rate Support for PCIe Gen1/Gen2
The link speed, number of lanes supported, and support of line rate for PCIe are defined in
Table 2-1. Achieving line rate for PCIe is dependent on the device family, the AXI clock
X-Ref Target - Figure 2-2
Figure 2-2: FPGA System Configuration Diagram
AXI4-Lite
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Chapter 2: Product Specification
frequency, the AXI data width, the number of lanes, and Gen1 (2.5 GT/s) or Gen2 (5.0 GT/s)
link speed.
Resource Utilization
Table 2-2 illustrates a subset of IP core configurations and the device utilization estimates.
Variation in tools and optimization settings can result in variance of these reported
numbers.
Table 2-2 shows the resource utilization for the AXI Bridge for PCIe core for different
configurations on the Virtex-7 XC7V2000T device. These numbers were generated in the
Vivado® Design Suite. Resource Utilization numbers for other devices can be generated by
implementing the provided example design and checking for the resources used by only
the core in the resource utilization report.
Table 2-1: Line Rate for PCIe Support for Gen1/Gen2
C_FAMILY C_X_AXI_DATA_WIDTH PCIe Link
Speed C_NO_OF_LANES AXI_ACLK _OUT Userclk1 Userclk2
7 series,
Zynq®-7000
64 Gen1 x1 62.5 MHz 62.5 MHz 62.5 MHz x2, 4 125 MHz 125 MHz 125 MHz
Gen2 x1, 2
128 Gen1,
Gen2 x1, 2, 4, 8(1) 125 MHz 250 MHz 125 MHz
Notes:
1. x8 Gen2 configuration is not supported. Artix-7 does not support x8 Gen1.
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Chapter 2: Product Specification
Port Descriptions
The interface signals for the AXI Bridge for PCI Express are described in Table 2-3.
Table 2-2: Resource Utilization Summary
Configuration Slice Registers Slice LUTs
Endpoint x1 Gen1 8678 13054
Endpoint x2 Gen1 8963 13300
Endpoint x4 Gen1 9558 13666
Endpoint x8 Gen1 11912 17355
Endpoint x1 Gen2 8620 14041
Endpoint x2 Gen2 8897 14362
Endpoint x4 Gen2 10629 16477
Root Port x1 Gen1 10703 15909
Root Port x2 Gen1 10836 15537
Root Port x4 Gen1 11431 15924
Root Port x8 Gen1 13805 20128
Root Port x1 Gen2 10674 16734
Root Port x2 Gen2 11062 17137
Root Port x4 Gen2 12563 19325
Table 2-3: Top-Level Interface Signals
Signal Name I/O Description
Global Signals
refclk IPCIe Reference Clock
axi_aresetn IGlobal reset signal for AXI Interfaces
axi_aclk_out OPCIe derived clock output for axi_aclk
axi_ctl_aclk_out OPCIe derived clock output for axi_ctl_aclk
mmcm_lock Oaxi_aclk_out from the axi_enhanced_pcie block is stable
interrupt_out OInterrupt signal
AXI Slave Interface
s_axi_awid[c_s_axi_id_width-1:0] ISlave write address ID
s_axi_awaddr[c_s_axi_addr_width-1:0] ISlave address write
s_axi_awregion[3:0] ISlave write region decode
s_axi_awlen[7:0] ISlave write burst length
s_axi_awsize[2:0] ISlave write burst size
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Chapter 2: Product Specification
s_axi_awburst[1:0] ISlave write burst type
s_axi_awvalid ISlave address write valid
s_axi_awready OSlave address write ready
s_axi_wdata[c_s_axi_data_width-1:0] ISlave write data
s_axi_wstrb[c_s_axi_data_width/8-1:0] ISlave write strobe
s_axi_wlast ISlave write last
s_axi_wvalid ISlave write valid
s_axi_wready OSlave write ready
s_axi_bid[c_s_axi_id_width-1:0] OSlave response ID
s_axi_bresp[1:0] OSlave write response
s_axi_bvalid OSlave write response valid
s_axi_bready ISlave response ready
s_axi_arid[c_s_axi_id_width-1:0] I Slave read address ID
s_axi_araddr[c_s_axi_addr_width-1:0] I Slave read address
s_axi_arregion[3:0] ISlave read region decode
s_axi_arlen[7:0] ISlave read burst length
s_axi_arsize[2:0] ISlave read burst size
s_axi_arburst[1:0] ISlave read burst type
s_axi_arvalid ISlave read address valid
s_axi_arready OSlave read address ready
s_axi_rid[c_s_axi_id_width-1:0] OSlave read ID tag
s_axi_rdata[c_s_axi_data_width-1:0] OSlave read data
s_axi_rresp[1:0] OSlave read response
s_axi_rlast OSlave read last
s_axi_rvalid OSlave read valid
s_axi_rready ISlave read ready
AXI Master Interface
m_axi_awaddr[c_m_axi_addr_width-1:0] OMaster address write
m_axi_awlen[7:0] OMaster write burst length
m_axi_awsize[2:0] OMaster write burst size
m_axi_awburst[1:0] OMaster write burst type
m_axi_awprot[2:0] OMaster write protection type
m_axi_awvalid OMaster write address valid
m_axi_awready IMaster write address ready
m_axi_wdata[c_m_axi_data_width-1:0] OMaster write data
Table 2-3: Top-Level Interface Signals (Cont’d)
Signal Name I/O Description
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m_axi_wstrb[c_m_axi_data_width/8-1:0] OMaster write strobe
m_axi_wlast OMaster write last
m_axi_wvalid OMaster write valid
m_axi_wready IMaster write ready
m_axi_bresp[1:0] IMaster write response
m_axi_bvalid IMaster write response valid
m_axi_bready OMaster response ready
m_axi_araddr[c_m_axi_addr_width-1:0] OMaster read address
m_axi_arlen[7:0] OMaster read burst length
m_axi_arsize[2:0] OMaster read burst size
m_axi_arburst[1:0] OMaster read burst type
m_axi_arprot[2:0] OMaster read protection type
m_axi_arvalid OMaster read address valid
m_axi_arready IMaster read address ready
m_axi_rdata[c_m_axi_data_width-1:0] IMaster read data
m_axi_rresp[1:0] IMaster read response
m_axi_rlast IMaster read last
m_axi_rvalid IMaster read valid
m_axi_rready OMaster read ready
AXI4-Lite Control Interface
s_axi_ctl_awaddr[31:0] ISlave write address
s_axi_ctl_awvalid ISlave write address valid
s_axi_ctl_awready OSlave write address ready
s_axi_ctl_wdata[31:0] ISlave write data
s_ax_ctl_wstrb[3:0] ISlave write strobe
s_axi_ctl_wvalid ISlave write valid
s_axi_ctl_wready OSlave write ready
s_axi_ctl_bresp[1:0] OSlave write response
s_axi_ctl_bvalid OSlave write response valid
s_axi_ctl_bready ISlave response ready
s_axi_ctl_araddr[31:0] I Slave read address
s_axi_ctl_arvalid ISlave read address valid
s_axi_ctl_arready OSlave read address ready
s_axi_ctl_rdata[31:0] OSlave read data
s_axi_ctl_rresp[1:0] OSlave read response
Table 2-3: Top-Level Interface Signals (Cont’d)
Signal Name I/O Description
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Chapter 2: Product Specification
Bridge Parameters
Because many features in the AXI Bridge for PCI Express core design can be parameterized,
you are able to uniquely tailor the implementation of the core using only the resources
required for the desired functionality. This approach also achieves the best possible
performance with the lowest resource usage.
The parameters defined for the AXI Bridge for PCI Express are shown in Table 2-4.
s_axi_ctl_rvalid OSlave read valid
s_axi_ctl_rready ISlave read ready
MSI Signals
intx_msi_request I
Legacy interrupt input (see c_interrupt_pin) when
msi_enable = 0.
Initiates a MSI write request when msi_enable = 1.
Intx_msi_request is asserted for one clock period.
intx_msi_grant O
Indicates legacy interrupt/MSI grant signal. The
intx_msi_grant signal is asserted for one clock period
when the interrupt is accepted by the PCIe core.
msi_enable OIndicates when MSI is enabled.
msi_vector_num [4:0] IIndicates MSI vector to send when writing a MSI write
request.
msi_vector_width [2:0] OIndicates the size of the MSI field (the number of MSI
vectors allocated to the device).
PCIe Interface
pci_exp_rxp[c_no_of_lanes-1: 0] IPCIe RX serial interface
pci_exp_rxn[c_no_of_lanes-1: 0] IPCIe RX serial interface
pci_exp_txp[c_no_of_lanes-1: 0] OPCIe TX serial interface
pci_exp_txn[c_no_of_lanes-1:0] OPCIe TX serial interface
Table 2-3: Top-Level Interface Signals (Cont’d)
Signal Name I/O Description
Table 2-4: Top-Level Parameters
Generic Parameter Name Description Allowable Values Default Value VHDL Type
Bridge Parameters
C_PCIE_BLK_LOCN
PCIe integrated
block location
within FPGA
0: X0Y0
1: X0Y1
2: X0Y2
3: X1Y0
4: X1Y1
0String
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C_XLNX_REF_BOARD Target FPGA Board
NONE
KC705_REVA
KC705_REVB
KC705_REVC
VC707
NONE String
G1 C_FAMILY Target FPGA Family kintex7, virtex7, artix7,
zynq String
G2 C_INCLUDE_RC
Configures the AXI
bridge for PCIe to be
a Root Port or an
Endpoint
0: Endpoint
1: Root Port (applies only
for 7 series, and
Zynq-7000 devices)
0Integer
G3 C_COMP_TIMEOUT
Selects the Slave
Bridge completion
timeout counter
value
0: 50 µs
1: 50 ms 0Integer
G4 C_INCLUDE_
BAROFFSET_REG
Include the registers
for high-order bits
to be substituted in
translation in Slave
Bridge
0: Exclude
1: Include 0Integer
G5 C_SUPPORTS_
NARROW_BURST
Instantiates internal
logic to support
narrow burst
transfers. Only
enable when AXI
master bridge
generates narrow
burst traffic.
0: Not supported
1: Supported 0Integer
G6 C_AXIBAR_NUM
Number of AXI
address apertures
that can be accessed
1-6;
1: BAR_0 enabled
2: BAR_0, BAR_1 enabled
3: BAR_0, BAR_1, BAR_2
enabled
4: BAR_0 through BAR_3
enabled
5: BAR_0 through BAR_4
enabled
6: BAR_0 through BAR_5
enabled
6Integer
G7 C_AXIBAR_0 AXI BAR_0 aperture
low address Valid AXI address(1)(3)(4) 0xFFFF_FFFF std_logic_
vector
G8 C_AXIBAR_
HIGHADDR_0
AXI BAR_0 aperture
high address Valid AXI address(1)(3)(4) 0x0000_0000 std_logic_
vector
G9 C_AXIBAR_AS_0 AXI BAR_0 address
size
0: 32 bit
1: 64 bit 0Integer
Table 2-4: Top-Level Param eters (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
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Chapter 2: Product Specification
G10 C_AXIBAR2PCIEBAR_0
PCIe BAR to which
AXI BAR_0 is
mapped
Valid address for PCIe(2) 0xFFFF_FFFF std_logic_
vector
G11 C_AXIBAR_1 AXI BAR_1 aperture
low address Valid AXI address(1)(3)(4) 0xFFFF_FFFF std_logic_
vector
G12 C_AXIBAR_
HIGHADDR_1
AXI BAR_1 aperture
high address Valid AXI address(1)(3)(4) 0x0000_0000 std_logic_
vector
G13 C_AXIBAR_AS_1 AXI BAR_1 address
size
0: 32 bit
1: 64 bit 0Integer
G14 C_AXIBAR2PCIEBAR_1
PCIe BAR to which
AXI BAR_1 is
mapped
Valid address for PCIe(2) 0xFFFF_FFFF std_logic_
vector
G15 C_AXIBAR_2 AXI BAR_2 aperture
low address Valid AXI address(1)(3)(4) 0xFFFF_FFFF std_logic_
vector
G16 C_AXIBAR_
HIGHADDR_2
AXI BAR_2 aperture
high address Valid AXI address(1)(3)(4) 0x0000_0000 std_logic_
vector
G17 C_AXIBAR_AS_2 AXI BAR_2 address
size
0: 32 bit
1: 64 bit 0Integer
G18 C_AXIBAR2PCIEBAR_2
PCIe BAR to which
AXI BAR_2 is
mapped
Valid address for PCIe(2) 0xFFFF_FFFF std_logic_
vector
G19 C_AXIBAR_3 AXI BAR_3 aperture
low address Valid AXI address(1)(3)(4) 0xFFFF_FFFF std_logic_
vector
G20 C_AXIBAR_
HIGHADDR_3
AXI BAR_3 aperture
high address Valid AXI address(1)(3)(4) 0x0000_0000 std_logic_
vector
G21 C_AXIBAR_AS_3 AXI BAR_3 address
size
0: 32 bit
1: 64 bit 0Integer
G22 C_AXIBAR2PCIEBAR_3
PCIe BAR to which
AXI BAR_3 is
mapped
Valid address for PCIe(2) 0xFFFF_FFFF std_logic_
vector
G23 C_AXIBAR_4 AXI BAR_4 aperture
low address Valid AXI address(1)(3)(4) 0xFFFF_FFFF std_logic_
vector
G24 C_AXIBAR_
HIGHADDR_4
AXI BAR_4 aperture
high address Valid AXI address(1)(3)(4) 0x0000_0000 std_logic_
vector
G25 C_AXIBAR_AS_4 AXI BAR_4 address
size
0: 32 bit
1: 64 bit 0Integer
G26 C_AXIBAR2PCIEBAR_4
PCIe BAR to which
AXI BAR_4 is
mapped
Valid address for PCIe(2) 0xFFFF_FFFF std_logic_
vector
G27 C_AXIBAR_5 AXI BAR_5 aperture
low address Valid AXI address(1)(3)(4) 0xFFFF_FFFF std_logic_
vector
Table 2-4: Top-Level Param eters (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
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G28 C_AXIBAR_
HIGHADDR_5
AXI BAR_5 aperture
high address Valid AXI address(1)(3)(4) 0x0000_0000 std_logic_
vector
G29 C_AXIBAR_AS_5 AXI BAR_5 address
size
0: 32 bit
1: 64 bit 0Integer
G30 C_AXIBAR2PCIEBAR_5
PCIe BAR to which
AXI BAR_5 is
mapped
Valid address for PCIe(2) 0xFFFF_FFFF std_logic_
vector
G31 C_PCIEBAR_NUM
Number of address
for PCIe apertures
that can be accessed
1-3;
1: BAR_0 enabled
2: BAR_0, BAR_1 enabled
3: BAR_0, BAR_1, BAR_2
enabled
3Integer
G32 C_PCIEBAR_AS
Configures PCIEBAR
aperture width to be
32 bits wide or 64
bits wide
0: Generates three 32-bit
PCIEBAR address
apertures.
32-bit BAR example:
PCIEBAR_0 is 32 bits
PCIEBAR_1 is 32 bits
PCIEBAR_2 is 32 bits
1: Generates three 64 bit
PCIEBAR address
apertures.
64-bit BAR example:
PCIEBAR_0 and PCIEBAR_1
concatenate to comprise
64-bit PCIEBAR_0.
PCIEBAR_2 and PCIEBAR_3
concatenate to comprise
64-bit PCIEBAR_1.
PCIEBAR_4 and PCIEBAR_5
concatenate to comprise
64-bit PCIEBAR_2
1Integer
G33 C_PCIEBAR_LEN_0
Power of 2 in the
size of bytes of PCIE
BAR_0 space
13-31 16 Integer
G34 C_PCIEBAR2AXIBAR_0
AXIBAR to which
PCIE BAR_0 is
mapped
Valid AXI address 0x0000_0000 std_logic_
vector
Table 2-4: Top-Level Param eters (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
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Chapter 2: Product Specification
C_PCIEBAR2AXIBAR_0
_SEC
Defines the AXIBAR
memory space (PCIe
BAR_0) (accessible
from PCIe) to be
either secure or
non-secure memory
mapped.
0: Denotes a non-secure
memory space
1: Marks the AXI memory
space as secure
0Integer
G35 C_PCIEBAR_LEN_1
Power of 2 in the
size of bytes of PCIE
BAR_1 space
13-31 16 Integer
G36 C_PCIEBAR2AXIBAR_1
AXIBAR to which
PCIE BAR_1 is
mapped
Valid AXI address 0x0000_0000 std_logic_
vector
C_PCIEBAR2AXIBAR_1
_SEC
Defines the AXIBAR
memory space (PCIe
BAR_1) (accessible
from PCIe) to be
either secure or
non-secure memory
mapped.
0: Denotes a non-secure
memory space
1: Marks the AXI memory
space as secure
0Integer
G37 C_PCIEBAR_LEN_2
Power of 2 in the
size of bytes of PCIE
BAR_2 space
13-31 16 Integer
G38 C_PCIEBAR2AXIBAR_2
AXIBAR to which
PCIE BAR_2 is
mapped
Valid AXI address 0x0000_0000 std_logic_
vector
C_PCIEBAR2AXIBAR_2
_SEC
Defines the AXIBAR
memory space (PCIe
BAR_2) (accessible
from PCIe) to be
either secure or
non-secure memory
mapped.
0: Denotes a non-secure
memory space
1: Marks the AXI memory
space as secure
0Integer
AXI4-Lite Parameters
G39 C_BASEADDR
Device base address
Note: When
configured as an
RP, the minimum
alignment
granularity must be
256 MB. Bit [27:0]
are used for Bus
Number, Device
Number, Function
number.
Valid AXI address 0xFFFF_FFFF std_logic_
vector
G40 C_HIGHADDR Device high address Valid AXI address 0x0000_0000 std_logic_
vector
Table 2-4: Top-Level Param eters (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
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Chapter 2: Product Specification
C_S_AXI_CTL_
PROTOCOL
AXI4-Lite port
connection
definition to AXI
Interconnect in the
Vivado IP integrator.
AXI4LITE AXI4LITE String
Core for PCIe Configuration Parameters
G41 C_NO_OF_LANES Number of PCIe
Lanes 1, 2, 4, 8: 7 series FPGAs 1Integer
G42 C_DEVICE_ID Device ID 16-bit vector 0x0000 std_logic_
vector
G43 C_VENDOR_ID Vendor ID 16-bit vector 0x0000 std_logic_
vector
G44 C_CLASS_CODE Class Code 24-bit vector 0x00_0000 std_logic_
vector
G45 C_REV_ID Rev ID 8-bit vector 0x00 std_logic_
vector
G46 C_SUBSYSTEM_ID Subsystem ID 16-bit vector 0x0000 std_logic_
vector
G47 C_SUBSYSTEM_
VENDOR_ID
Subsystem Vendor
ID 16-bit vector 0x0000 std_logic_
vector
C_PCIE_USE_MODE
Specifies PCIe use
mode for underlying
serial transceiver
wrapper usage/
configuration
(specific only to 7
series).
This parameter
ignored for
Zynq-7000 devices
(set to 3.0).
See Tab le 2-6.
1.0: For Kintex-7 325T IES
(initial ES) silicon
1.1: For Virtex-7 485T IES
(initial ES) silicon
3.0: For GES (general ES)
silicon
1.0 String
G48 C_PCIE_CAP_SLOT_
IMPLEMENTED
PCIE Capabilities
Register Slot
Implemented
0: Not add-in card slot
1: Downstream port is
connected to add-in card
slot
(valid only for Root
Complex)
0Integer
G49 C_REF_CLK_FREQ REFCLK input
Frequency
0: 100 MHz
1: 125 MHz
2: 250 MHz - 7 series
FPGAs only
0Integer
Table 2-4: Top-Level Param eters (Cont’d)
Generic Parameter Name Description Allowable Values Default Value VHDL Type
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