Xilinx Virtex-4 FX FPGA User manual

R
ML42xUser Guide
Virtex-4 FX FPGA RocketIO
Characterization Platform
UG087 (v1.3) May 30, 2008
P/N 0402349-02
www.BDTIC.com/XILINX

ML42xUser Guide www.xilinx.com UG087 (v1.3) May 30, 2008
Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development
of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the
Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,
without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves
the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors
contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with
technical support or assistance that may be provided to you in connection with the Information.
THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER
WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY
RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL
DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.
© 2005–2008 Xilinx, Inc. All rights reserved.
XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks
are the property of their respective owners.
Revision History
The following table shows the revision history for this document.
Date Version Revision
06/28/05 1.0 Initial Xilinx release.
09/28/05 1.0.1 In “Package Contents” section, added SMA wrench and deleted NQSL board.
Minor text edits for clarity.
11/06/06 1.1 Added “22. System ACE MPU Port” section. Miscellaneous typographical edits.
03/02/07 1.2 Added “Additional Documentation”section. Updated “Package Contents”section.
Added “Additional Information” section.
02/06/08 1.2.1 Updated Legal disclaimer. Updated the link to the product page in “Additional
Information.”
05/30/08 1.3
Added the ML421 reference designators in Table 2, page 13. Added the ML424 reference
designators in Table 3, page 14. Corrected VTT RX LEFT and VTT RX RIGHT for the
ML421 and ML423 in Table 3, page 14. Corrected labels for ML423 in Table 8, page 16.
Corrected pins 29, 31, 33, and 35 for ML424 in Table 14, page 19. Corrected VCC for
ML421, ML423, and ML424 in Table 16, page 21. Corrected pin 62 for ML423 and pins 30
and 32 for ML424 in Table 18, page 22. Corrected labels J115 through J118 for ML423 in
Table 21, page 25. Corrected MPA00 and MPA04 for ML421, and MPA06 for ML423 in
Table 23, page 30.
R
www.BDTIC.com/XILINX

ML42xUser Guide www.xilinx.com 3
UG087 (v1.3) May 30, 2008
Preface: About This Guide
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ML42x RocketIO Characterization Platform
Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1. Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2. FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Oscillator Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Single-Ended SMA Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Differential SMA MGT Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Differential SMA Global Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Differential SMA Regional Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8. User LEDs (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9. User DIP Switches (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10. User Pushbutton Switches (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11. Xilinx Generic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
12. LVDS Header Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13. Program Switch (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
14. Reset Switch (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15. DONE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16. INIT LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
17. System ACE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
18. Configuration Address DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
19. RocketIO Transceiver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
20. RS-232 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
21. External Bias Potentiometers (RTERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
22. System ACE MPU Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table of Contents
www.BDTIC.com/XILINX

4www.xilinx.com ML42xUser Guide
UG087 (v1.3) May 30, 2008
R
www.BDTIC.com/XILINX

ML42xUser Guide www.xilinx.com 5
UG087 (v1.3) May 30, 2008
Preface: About This Guide
ML42x RocketIO Characterization Platform
Table 1: Platforms, Devices, and Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2: Onboard Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3: Power Supply Module Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4: OSC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5: SMA Clock Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6: Differential SMA MGT Clock Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7: Differential SMA Global Clock Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8: Differential SMA Regional Clock Pin Connections . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9: User LED, Row 1 (Top). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10: User LED, Row 2 (Bottom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11: User DIP Switches, Row 1 (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12: User DIP Switches, Row 2 (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13: User Pushbutton Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 14: XGI Header (J13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 15: XGI Header (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 16: XGI Header (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 17: XGI Header (J14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 18: LVDS Header (J139) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 19: LVDS Header (J101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 20: Bitstream Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21: RocketIO Transceiver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22: RS-232 Port Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 23: System ACE Port Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Schedule of Tables
www.BDTIC.com/XILINX

6www.xilinx.com ML42xUser Guide
UG087 (v1.3) May 30, 2008
R
www.BDTIC.com/XILINX

ML42xUser Guide www.xilinx.com 7
UG087 (v1.3) May 30, 2008
R
Preface
About This Guide
This document describes the features and operation of the Virtex®-4 FX FPGA ML42x
series of RocketIO™ characterization platforms.
Additional Documentation
Information about the Virtex-4 family of FPGAs at http://www.xilinx.com/virtex4
includes:
•Product highlights
•Data sheets
•User guides
•Application notes
Additional information is available from the data sheets and application notes from the
component manufacturers.
Additional Support Resources
To search the database of silicon and software questions and answers, or to create a
technical support cae WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
www.BDTIC.com/XILINX

8www.xilinx.com ML42xUser Guide
UG087 (v1.3) May 30, 2008
Preface: About This Guide
R
Typographical Conventions
This document uses the following conventions. An example illustrates each convention.
Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Italic font
References to other documents. See the Virtex-4 FPGA Configuration
User Guide for more information.
Emphasis in text. The address (F) is asserted after clock
event 2.
Underlined Text Indicates a link to a web page. http://www.xilinx.com/virtex4
Convention Meaning or Use Example
Blue text Cross-reference link to a location
in the current document
See the section “Additional
Support Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Red text Cross-reference link to a location
in another document
See Figure 2 in the Virtex-4
FPGA Data Sheet.
Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com
for the latest documentation.
www.BDTIC.com/XILINX

ML42xUser Guide www.xilinx.com 9
UG087 (v1.3) May 30, 2008
R
ML42x RocketIO Characterization Platform
Package Contents
•Virtex®-4 FX FPGA RocketIO™ characterization platform (referred to as the ML42x
platform)
•User guide
•SMA-to-SMA cable assemblies
♦Four 24-inch cables
♦Two 12-inch cables
•System ACE™ CompactFlash memory card
•RS-232 cable
•SuperClock module
•Power supply module
•Power supply brick
•SMA wrench
Note: Development tools and PC download cable are not included and must be ordered separately.
Additional Information
The ML42x product page contains the platform’s current information, including:
•Current version of this user guide in PDF format
•Example design files for demonstration of Virtex-4 FPGA features and technology
•Demonstration hardware and software configuration files for the System ACE
controller
•Full schematics in PDF format and ViewDraw schematic format
•PC board layout in PADS PCB format
•Gerber files for the PC board (Many free or shareware Gerber file viewers are
available on the Internet for viewing and printing these files.)
•Additional documentation, errata, frequently asked questions, and the latest news
•Contents of the CompactFlash card provided with the ML42xplatform
www.BDTIC.com/XILINX

10 www.xilinx.com ML42xUser Guide
UG087 (v1.3) May 30, 2008
Related Documents
R
Related Documents
Prior to using the ML42xplatforms, users should be familiar with Xilinx resources. See
“References,” page 30 for direct links to Xilinx documentation. See the following locations
for additional documentation on Xilinx tools and solutions:
•EDK: www.xilinx.com/edk
•ISE®Design Suite: www.xilinx.com/ise
•Answer Browser: www.xilinx.com/support
•Virtex-4 FPGAs: www.xilinx.com/virtex-4
•ChipScope™ Pro: www.xilinx.com/chipscope
Introduction
The ML42xplatform allows designers to investigate and experiment with the features of
RocketIO multi-gigabit transceivers (MGTs). This document describes the features and
operation of the boards.
The platforms and their corresponding packages are shown in Table 1.
Features
•Virtex-4 FPGA (referred to as the device under test, or DUT, in this user guide)
•Onboard power supplies for all necessary voltages capable of supplying 1.5A to 6A
•Power supply jacks for optional use of external power supplies
•JTAG configuration port for use with Parallel Cable III and Parallel Cable IV cables
•System ACE configuration controller
•RS-232 serial port
•MGT power supply module for supporting all transceiver power requirements
•Two 2.5V/3.3V global clock oscillator sockets
•Two single-ended global clock inputs with SMA connectors
•Two differential global clock inputs with SMA connectors
•Xilinx Generic Interface (XGI)
•SuperClock module with XGI
•24 or 96 pairs of SMA connectors for the RocketIO transceivers
•Power indicator LEDs
•General purpose DIP switches, LEDs, and pushbutton switches
•One differential local clock input with SMAs
•Four differential MGT clock inputs with SMAs
•EU-RoHS-compliant
Ta b le 1 : Platforms, Devices, and Packages
Platform Device Package
ML421 XC4VFX60 FF672
ML423 XC4VFX100 FF1152
ML424 XC4VFX100 FF1517
www.BDTIC.com/XILINX