Xilinx Virtex-4 FX FPGA User manual

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ML42xUser Guide
Virtex-4 FX FPGA RocketIO
Characterization Platform
UG087 (v1.3) May 30, 2008
P/N 0402349-02
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Revision History
The following table shows the revision history for this document.
Date Version Revision
06/28/05 1.0 Initial Xilinx release.
09/28/05 1.0.1 In “Package Contents” section, added SMA wrench and deleted NQSL board.
Minor text edits for clarity.
11/06/06 1.1 Added “22. System ACE MPU Port” section. Miscellaneous typographical edits.
03/02/07 1.2 Added “Additional Documentation”section. Updated “Package Contents”section.
Added “Additional Information” section.
02/06/08 1.2.1 Updated Legal disclaimer. Updated the link to the product page in “Additional
Information.”
05/30/08 1.3
Added the ML421 reference designators in Table 2, page 13. Added the ML424 reference
designators in Table 3, page 14. Corrected VTT RX LEFT and VTT RX RIGHT for the
ML421 and ML423 in Table 3, page 14. Corrected labels for ML423 in Table 8, page 16.
Corrected pins 29, 31, 33, and 35 for ML424 in Table 14, page 19. Corrected VCC for
ML421, ML423, and ML424 in Table 16, page 21. Corrected pin 62 for ML423 and pins 30
and 32 for ML424 in Table 18, page 22. Corrected labels J115 through J118 for ML423 in
Table 21, page 25. Corrected MPA00 and MPA04 for ML421, and MPA06 for ML423 in
Table 23, page 30.
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Preface: About This Guide
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typographical Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ML42x RocketIO Characterization Platform
Package Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1. Power Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2. FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Oscillator Sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Single-Ended SMA Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Differential SMA MGT Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. Differential SMA Global Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7. Differential SMA Regional Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8. User LEDs (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9. User DIP Switches (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10. User Pushbutton Switches (Active-High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11. Xilinx Generic Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
12. LVDS Header Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
13. Program Switch (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
14. Reset Switch (Active-Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
15. DONE LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
16. INIT LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
17. System ACE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
18. Configuration Address DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
19. RocketIO Transceiver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
20. RS-232 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
21. External Bias Potentiometers (RTERM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
22. System ACE MPU Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table of Contents
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Preface: About This Guide
ML42x RocketIO Characterization Platform
Table 1: Platforms, Devices, and Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2: Onboard Regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3: Power Supply Module Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4: OSC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5: SMA Clock Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6: Differential SMA MGT Clock Pin Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7: Differential SMA Global Clock Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8: Differential SMA Regional Clock Pin Connections . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9: User LED, Row 1 (Top). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10: User LED, Row 2 (Bottom). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11: User DIP Switches, Row 1 (Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12: User DIP Switches, Row 2 (Bottom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 13: User Pushbutton Switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 14: XGI Header (J13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 15: XGI Header (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 16: XGI Header (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 17: XGI Header (J14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 18: LVDS Header (J139) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 19: LVDS Header (J101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 20: Bitstream Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 21: RocketIO Transceiver Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 22: RS-232 Port Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 23: System ACE Port Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Schedule of Tables
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Preface
About This Guide
This document describes the features and operation of the Virtex®-4 FX FPGA ML42x
series of RocketIO™ characterization platforms.
Additional Documentation
Information about the Virtex-4 family of FPGAs at http://www.xilinx.com/virtex4
includes:
•Product highlights
•Data sheets
•User guides
•Application notes
Additional information is available from the data sheets and application notes from the
component manufacturers.
Additional Support Resources
To search the database of silicon and software questions and answers, or to create a
technical support cae WebCase, see the Xilinx website at:
http://www.xilinx.com/support.
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Preface: About This Guide
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Typographical Conventions
This document uses the following conventions. An example illustrates each convention.
Online Document
The following conventions are used in this document:
Convention Meaning or Use Example
Italic font
References to other documents. See the Virtex-4 FPGA Configuration
User Guide for more information.
Emphasis in text. The address (F) is asserted after clock
event 2.
Underlined Text Indicates a link to a web page. http://www.xilinx.com/virtex4
Convention Meaning or Use Example
Blue text Cross-reference link to a location
in the current document
See the section “Additional
Support Resources” for details.
Refer to “Title Formats” in
Chapter 1 for details.
Red text Cross-reference link to a location
in another document
See Figure 2 in the Virtex-4
FPGA Data Sheet.
Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com
for the latest documentation.
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ML42x RocketIO Characterization Platform
Package Contents
•Virtex®-4 FX FPGA RocketIO™ characterization platform (referred to as the ML42x
platform)
•User guide
•SMA-to-SMA cable assemblies
♦Four 24-inch cables
♦Two 12-inch cables
•System ACE™ CompactFlash memory card
•RS-232 cable
•SuperClock module
•Power supply module
•Power supply brick
•SMA wrench
Note: Development tools and PC download cable are not included and must be ordered separately.
Additional Information
The ML42x product page contains the platform’s current information, including:
•Current version of this user guide in PDF format
•Example design files for demonstration of Virtex-4 FPGA features and technology
•Demonstration hardware and software configuration files for the System ACE
controller
•Full schematics in PDF format and ViewDraw schematic format
•PC board layout in PADS PCB format
•Gerber files for the PC board (Many free or shareware Gerber file viewers are
available on the Internet for viewing and printing these files.)
•Additional documentation, errata, frequently asked questions, and the latest news
•Contents of the CompactFlash card provided with the ML42xplatform
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Related Documents
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Related Documents
Prior to using the ML42xplatforms, users should be familiar with Xilinx resources. See
“References,” page 30 for direct links to Xilinx documentation. See the following locations
for additional documentation on Xilinx tools and solutions:
•EDK: www.xilinx.com/edk
•ISE®Design Suite: www.xilinx.com/ise
•Answer Browser: www.xilinx.com/support
•Virtex-4 FPGAs: www.xilinx.com/virtex-4
•ChipScope™ Pro: www.xilinx.com/chipscope
Introduction
The ML42xplatform allows designers to investigate and experiment with the features of
RocketIO multi-gigabit transceivers (MGTs). This document describes the features and
operation of the boards.
The platforms and their corresponding packages are shown in Table 1.
Features
•Virtex-4 FPGA (referred to as the device under test, or DUT, in this user guide)
•Onboard power supplies for all necessary voltages capable of supplying 1.5A to 6A
•Power supply jacks for optional use of external power supplies
•JTAG configuration port for use with Parallel Cable III and Parallel Cable IV cables
•System ACE configuration controller
•RS-232 serial port
•MGT power supply module for supporting all transceiver power requirements
•Two 2.5V/3.3V global clock oscillator sockets
•Two single-ended global clock inputs with SMA connectors
•Two differential global clock inputs with SMA connectors
•Xilinx Generic Interface (XGI)
•SuperClock module with XGI
•24 or 96 pairs of SMA connectors for the RocketIO transceivers
•Power indicator LEDs
•General purpose DIP switches, LEDs, and pushbutton switches
•One differential local clock input with SMAs
•Four differential MGT clock inputs with SMAs
•EU-RoHS-compliant
Ta b le 1 : Platforms, Devices, and Packages
Platform Device Package
ML421 XC4VFX60 FF672
ML423 XC4VFX100 FF1152
ML424 XC4VFX100 FF1517
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Introduction
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Figure 1 shows a block diagram of the board.
Figure 1: Virtex-4 FPGA ML42xPlatform Block Diagram
XGI XGI
LEDs
GP SWs
PB SW 3
PB SW 4
OSC
SMA
OSC
Socket
SMA
2 X 1
SMA
2 X1
Right Angle SMA
Right Angle SMA
Right Angle SMA
Right Angle SMA
PROGRAM
MGT MGT
System ACE
UART
DONE
LED
INIT
LED
LEDs
GP SWs
PB SW 1
PB SW 2
Power Busand Switches
5V Jack 5V Brick-or-
MGT_VTT_RX_LEFT Jack
MGT_VTT_RX_RIGHT Jack
MGT_VTT_TX_LEFT Jack
MGT_VTT_TX_RIGHT Jack
AVCCAUX_TX Jack
AVCCAUX_RX Jack
AVCCAUXMGT Jack
MGT_VREF Jack
1.5V - 2.5V
1.5V - 2.5V
2.5V
1.2V
LVD S*
UG087_01_092006
Virtex-4
FPGA
(DUT)
MGT
Launch SMA
Active High Active High
DIFF
SMA
DIFF
SMA CC*
OSC
SMA
OSC
Socket
SMA
2 X 1
SMA
2 X1
MGTMGT
LVD S*
MGT Clock
MGT Clock
DIFF
SMA
1.2V
1.2V
VCCO Jack
VCCINT Jack
VAUX Jack
VCCINT
VAUX
VCCO
V5
1.5V
1.5V
12 Transceivers= 48SMAsin FF672
16 Transceivers= 64 SMAsin FF1152
20 Transceivers= 80 SMAsin FF1517
*Note: LVD Sheadersand clock capable regional clocks
are not available on ML421 platforms.
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Detailed Description
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Detailed Description
The ML423 platform, shown in Figure 2, is an example of the ML42xseries described in
this user guide. Each feature is detailed in the numbered sections that follow.
Note: The image might not reflect the current revision of the board.
Figure 2: Detailed Description of Virtex-4 FPGA ML42xPlatform Components
4
19
11
1
4
21
20
13 15
16
12
19
7
17
22
5
8
9
10
12
3
3
5
6
6
18
2
14
UG087_02_102006
Power Supply Jacks/Jumpers
MGT Power Supply Module
Note: LVDS headers (12) and clock capable regional clocks (7)
are not available on ML421 platforms.
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Detailed Description
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1. Power Switch
The board has onboard power supplies and an ON|OFF power switch. When lit, the V5
LED indicates power.
On Position
In the ON position, the power switch enables delivery of all power on the board by way of
voltage regulators situated close to the left side of the board and the MGT power supply
module situated close to the right side of the board. These regulators feed off the 5V
external power brick or the 5V power supply jack.
The 5V power brick is capable of providing a maximum of 6.5A. For designs that require
greater than 6.5A, an ATX power supply can be connected to the J16 hard drive power
connector.
Note: 5V must always be supplied to the board to enable the 3.3V regulator for the System ACE
chip.
Off Position
In the OFF position, the power switch disables all modes of power on the board.
Onboard Regulation
The ML42xplatform has onboard regulation for the DUT main power supplies listed in
Table 2. These regulators also have a corresponding input voltage jack to supply each
voltage independently from the bench-top power supply.
Power Select Jumpers
The power select jumpers are labeled JACK on one side of the header and SUPPLY on the
other side of the header. Appropriate placement of the jumpers on these headers enables
delivery of power from either the onboard regulators or the corresponding power supply
jack.
Table 2: Onboard Regulation
Power
Supply
Name
Max
Current
Rating
Typical
Voltag e
Jack
Description
ML421 ML423
ML424
Select
Jumper
5V N/A 5V J9/J33 J27/J12 N/A
Main input voltage for the board supplied
through the jack, barrel connector, or Molex
connector
VCC3 3A 3.3V N/A N/A N/A Supplies 3.3V to the System ACE chip and
other onboard circuits
VCCINT 6A 1.2V J37 J34 J105 Core voltage for the FPGA
VCCO 6A 2.5V-3.3V J34 J28 J106 I/O voltage for the FPGA
VCCAUX 3A 2.5V J36 J33 J58 Auxiliary supply voltage for the FPGA
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MGT Power Supply Module
The MGT power supply module supplies all voltages shown in Table 3 to the DUT
RocketIO transceivers. This module plugs in on the right side of the board on header J12
for the ML421 platform, and on header J9 for the ML423 and ML424 platforms.
The onboard regulators also have corresponding input voltage jacks to supply each
voltage independently from a bench-top power supply. This is done by removing the MGT
power supply enable jumpers from the headers that correspond to each supply voltage
listed in Table 3. An MGT power enable jumper must be removed before supplying an
external supply on its corresponding supply jack.
2. FPGA Configuration
The FPGA can only be configured in JTAG mode using one of the following options:
•Parallel Cable III cable
•Parallel Cable IV cable
•System ACE controller
Using the configuration address DIP switches, one of eight bitstreams stored in the
CompactFlash memory card can be accessed through the onboard System ACE controller.
Note: The System ACE controller is bypassed when the flying wire leads or the Parallel Cable IV
cable is used, thus causing no disruption in the JTAG chain.
Table 3: Power Supply Module Jumpers
Power
Supply
Name
Max
Current
Rating
Typical
Voltag e
Jack Enable
Jumper Description
ML421 ML423 ML424
AVCCAUXMGT 1.5A 2.5V J22 J22 J37 J11 Analog supply for global bias
VREF 1.5A 1.2V J23 J23 J58 J10
Optional supply for VREF circuit
(not required) or band gap
reference voltage
VTT TX LEFT 5A 1.5V J19 J19 J24 J7 X 2 Termination supply voltage for
transmitter A and B (left column)
AVCCAUXRX 5A 1.2V J20 J20 J25 J5 X 2
Analog supply for non-I/O
circuits in receiver A and analog
supply for non-I/O circuits in
receiver B, global bias, and
reference clock circuits
AVCCAUXTX 5A 1.2V J21 J21 J26 J4 X 2 Analog supply for non-I/O
circuits in transmitter pair
VTT TX RIGHT 5A 1.5V J18 J18 J18 J6 X 2
Termination supply voltage for
transmitter A and B (right
column)
VTT RX LEFT 1.5A 1.5V–2.5V J16 J15 J15 J8 Termination supply voltage for
receiver A and B (left column)
VTT RX RIGHT 1.5A 1.5V–2.5V J105 J81 J105 J9 Termination supply voltage for
receiver A and B (right column)
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Detailed Description
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3. Oscillator Sockets
The ML42xplatform has two crystal oscillator sockets, each wired for standard
LVTTL-type oscillators. These connect to the FPGA clock pins shown in Table 4. The
oscillator sockets accept both half and full sized oscillators and are powered by 3.3V or the
VCCO 2.5V power supply.
4. Single-Ended SMA Clocks
The ML42xplatform has two single-ended clock input SMA connectors that allow
connection to an external function generator. These connect to the FPGA clock pins as
shown in Table 5.
5. Differential SMA MGT Clocks
The ML42xplatform has four pairs of LVDS differential SMA MGT clock inputs as shown
in Table 6. These are dedicated clock inputs for RocketIO transceivers.
Ta b le 4 : OSC Connections
Label Clock Name
Pin
ML421 ML423 ML424
X3 L8N_GC_LC_3 B12 L14 H18
X2 L5P_GC_LC_4 AB14 AF20 AK21
Ta b le 5 : SMA Clock Pin Connections
Label Clock Name
Pin
ML421 ML423 ML424
J96 L7N_GC_LC_3 A13 H18 J21
J103 L4P_GC_LC_4 AE13 AE18 AL20
Ta b le 6 : Differential SMA MGT Clock Pin Connections
Label MGT Clock Name
Pin
ML421 ML423 ML424
J60 MGTCLK110_N AF11 AP4 AW7
J61 MGTCLK110_P AF10 AP3 AW6
J62 MGTCLK113_N L1 K1 G1
J64 MGTCLK113_P K1 J1 F1
J82 MGTCLK102_N G26 N34 G39
J83 MGTCLK102_P F26 M34 F39
J79 MGTCLK105_N AF20 AP28 AW33
J80 MGTCLK105_P AF21 AP29 AW34
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6. Differential SMA Global Clocks
Two pairs of 100Ωdifferentially routed SMA connectors allow the user to connect to an
external differential function generator. These connect to the global clock (GC) pins of the
FPGA as shown in Table 7. These SMA connectors can also be used as single-ended clock
inputs.
7. Differential SMA Regional Clocks
Two pairs of 100Ωdifferentially routed SMA connectors allow the user to connect to an
external differential function generator. These connect to the clock capable (CC) regional
clock pins of the FPGA as shown in Table 8. These SMAs can also be used as single-ended
clock inputs.
8. User LEDs (Active-High)
Twenty active-High LEDs, shown in Table 9 and Table 10, page 17, are connected to user
I/O pins on the FPGA. These LEDs can be used to indicate status or for any other user-
designated purpose.
Ta b le 7 : Differential SMA Global Clock Pin Connections
Label Clock Name
Pin
ML421 ML423 ML424
J97 L5N_GC_LC_3 B14 J19 L20
J98 L5P_GC_LC_3 C14 K19 L21
J102 L1N_GC_LC_4 AF15 AD20 AP21
J99 L1P_GC_LC_4 AE15 AD21 AP22
Ta b le 8 : Differential SMA Regional Clock Pin Connections
Label
Clock Name
Pin
ML421 ML423 ML424 ML421 ML423 ML424
J140 J157 L8N_CC_LC_9 E29 H32
J141 J156 L8P_CC_LC_9 F29 H33
Ta b le 9 : User LED, Row 1 (Top)
Label
Pin
ML421 ML423 ML424
DS11 AC9 AJ16 AK13
DS12 AD8 AG15 AP14
DS13 AD9 AF15 AN14
DS14 V6 AF14 AL14
DS15 U7 AE14 AM15
DS16 U9 AE13 AJ14
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9. User DIP Switches (Active-High)
There are 20 active-High DIP switches, as shown in Table 11 and Table 12, page 18,
connected to user I/O pins on the FPGA. These pins can be used to set control pins or any
other purpose the user designates.
DS17 N4 AH7 AU7
DS18 M4 AH8 AU8
DS19 AB9 AJ15 AH12
DS20 P3 AK9 AR9
Table 10: User LED, Row 2 (Bottom)
Label Pin
ML421 ML423 ML424
DS31 V4 AH9 AK9
DS29 U4 AJ9 AL9
DS28 T3 AD9 AN9
DS32 T4 AD10 AP9
DS33 V8 AF13 AK14
DS34 R5 AM7 AR8
DS35 P5 AM8 AT8
DS8 AC3 AK11 AU11
DS9 AC4 AJ11 AT11
DS10 AC8 AK16 AK12
Ta b le 9 : User LED, Row 1 (Top) (Continued)
Label
Pin
ML421 ML423 ML424
Table 11: User DIP Switches, Row 1 (Top)
SW5 Pin
ML421 ML423 ML424
1L3AJ7AP7
2AB6AH15AJ12
3 AB4 AE11 AP15
4AB5AD11AN15
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10. User Pushbutton Switches (Active-High)
Four active-High pushbutton switches, shown in Table 13, are connected to user I/O pins
on the FPGA. These switches can be used for any purpose that the user designates.
5AD3AE9AM11
6 AD4 AM12 AR12
7U5AM13AP12
8U6AH12AT13
9 AA8 AF9 AL11
10 AA9 AG11 AR13
Table 12: User DIP Switches, Row 2 (Bottom)
SW6 Pin
ML421 ML423 ML424
1N3AL9AT9
2Y8AK7AR7
3Y7AB12AU16
4 T9 AA13 AU17
5 AA7 AL14 AU12
6T8AK14AU13
7AC11AG12AT14
8AB11AF11AR14
9AB7AC12AT16
10 L4 AB13 AT18
Table 11: User DIP Switches, Row 1 (Top) (Continued)
SW5 Pin
ML421 ML423 ML424
Table 13: User Pushbutton Switches
Label Pin
ML421 ML423 ML424
SW7 Y3 AH10 AP10
SW3 W4 AJ10 AN10
SW2 AA4 AF10 AJ10
SW1 AA3 AG10 AJ9
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11. Xilinx Generic Interface
The XGI is an expansion interface for plug-in modules (for example, the SuperClock
module) and provides the user access to the I/O pins listed in Table 14, Table 15, page 20,
and Table 16, page 21. Table 17, page 21 shows header J10 with all pins connected to VCCO
for powering modules tied to this connector.
Table 14: XGI Header (J13)
Pin Number ML421 ML423 ML424
1 U19 AC23 AU25
3 T18 AC22 AT25
5AA17AE22AR27
7 Y17 AD22 AP27
9AA20AF25AN30
11 AA19 AF24 AP30
13 AB22 AG25 AL30
15 AB21 AH25 AM30
17 AC21 AJ24 AM28
19 AD21 AH24 AL28
21 AB20 AL24 AN28
23 AB19 AK24 AN27
25 AC19 AK23 AK27
27 AC18 AK22 AL26
29 AB17 AH23 AU28
31 AB16 AG23 AU27
33 AA24 AE28 AM32
35 AA23 AF28 AN32
37 AB24 AH27 AT31
39 AC24 AJ27 AU31
41 AD24 AJ26 AK29
43 AD23 AJ25 AL29
45 AC23 AL26 AT30
47 AC22 AM26 AU30
49 AD20 AL25 AR29
51 AD19 AM25 AT29
53 AD18 AM23 AM27
55 AC17 AL23 AM26
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The pin order in Table 15 is arranged from top to bottom as viewed on the board. It does
not reflect the physical connection to this connector.
57 AD16 AM22 AR26
59 AC16 AM21 AP26
61 AB15 AL19 AT24
63 AA15 AL18 AR24
Table 15: XGI Header (J11)
Pin Number ML421 ML423 ML424
1 IIC IIC IIC
2 IIC IIC IIC
3 U24 AG18 AP35
4 T24 AF18 AP34
5 Y16 AG16 AU26
6 Y15 AG17 AT26
7 W24 AF19 AT35
8 V24 AE17 AU35
9 AF14 AF21 AN20
10 AF13 AE21 AP20
11 AD15 AE16 AM22
12 AD14 AF16 AN22
13 AD13 AK29 AL19
14 AC14 AJ29 AL21
15 AC13 AK21 AK19
16 AC12 AL21 AJ19
17 AB12 AL29 AM21
18 AA12 AM30 AM20
19 TDO TDO TDO
20 X TDO X TDO X TDO
21 TCK TCK TCK
22 TMS TMS TMS
23 NC NC NC
24 VCC3 VCC3 VCC3
25 VCC3 VCC3 VCC3
Table 14: XGI Header (J13) (Continued)
Pin Number ML421 ML423 ML424
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