Xilinx Spartan-3A DSP FPGA Series User manual

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Spartan-3A DSP Starter
Platform User Guide
UG454 (v1.1) January 30, 2009
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Spartan-3A DSP Starter Platform User Guide www.xilinx.com UG454 (v1.1) January 30, 2009
© 2007-2009 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx,
Inc. All other trademarks are the property of their respective owners.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one
possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any
claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any
warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that
this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
Revision History
The following table shows the revision history for this document.
Date Version Revision
10/3/07 1.0 Initial Xilinx release.
1/30/09 1.1 Updated to v1.1.
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Table of Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Xilinx Spartan-3A DSP FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Micron DDR2 SDRAM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Intel J3 Parallel Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Intel S33 Serial Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SystemACE Module (SAM) Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
National Semiconductor 10/100/1000 Ethernet PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digilent Headers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Eridon Debug Connector (This is not a Serial ATA Connector) . . . . . . . . . . . . . . . . . . . 18
VGA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Miscellaneous I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
EXP Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Board Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Board Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PCB Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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UG454 (v1.1) January 30, 2009
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Spartan-3A DSP 1800A Board Features
Overview
The purpose of this manual is to describe the functionality and contents of the Spartan®-
3A DSP Starter Platform from Xilinx. This document includes instructions for operating
the board and descriptions of the hardware features.
For more information about this product, reference designs, and additional
documentation, please visit the product home page found at
www.xilinx.com/s3adspstarter or www.xilinx.com/s3adspmb or
www.xilinx.com/s3adsp_sk.
Design Description
The Spartan-3A Starter Platform provides a platform for engineers designing with the
Xilinx Spartan-3A DSP FPGA. The board provides the hardware to not only evaluate the
advanced features of the Spartan-3A DSP, but also to implement complete user
applications using peripherals on the Spartan-3A DSP Starter Platform and EXP modules,
or both, plugged into EXP expansion connectors on the Spartan-3A DSP Starter Platform.
Features
The Spartan-3A DSP Starter Platform provides the following features:
•Xilinx 3SD1800A-FG676 FPGA
•Clocks
♦125 MHz LVTTL SMT oscillator
♦LVTTL oscillator socket
♦25.175 MHz LVTTL SMT oscillator (video clock)
•Memory
♦32M x 32 (128 MB) DDR2 SDRAM
♦16Mx8 parallel and BPI configuration flash
♦64Mb SPI Configuration and Storage Flash (with 4 extra SPI selects)
•Interfaces
♦10/100/1000 PHY
♦JTAG programming and configuration Port
♦RS232 Port
♦Low-cost VGA
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UG454 (v1.1) January 30, 2009
Design Description R
•Buttons and switches
♦8 User LEDs
♦8-position user DIP switch
♦4 User push button switches
♦Reset push button switch
•User I/O and expansion
♦Digilent 6-pin header (2)
♦EXP expansion connector (2)
•Configuration and debug
♦JTAG
♦SystemACE™ module connector
♦Eridon debug connector (SATA)
Ordering Information
Table 1 lists the evaluation kit part numbers.
Part Number Hardware
HW-SD1800A-DSP-SB-UNI-G XtremeDSP Starter Platform - Spartan-3A DSP 1800A
Edition
Ta b l e 1 : Evaluation Kit and Hardware Ordering Information
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UG454 (v1.1) January 30, 2009
Functional Description
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Functional Description
A high-level block diagram of the Spartan-3A DSP Starter Platform is shown in Figure 1.
Subsequent sections provide details of the board design.
X-Ref Target - Figure 1
Figure 1: Spartan-3A DSP Starter Platform Block Diagram
3SD1800A-FG676
UG454_01_050908
16 MB Parallel NOR Flash
(16M x 8)
16 MbSPI Flash
Memory
128 MB DDR2
(32M X 32)
LVTTL OSC Socket
25.175 MHz VGA Clock
Clock Sources
125 MHz LVTTL OSC
RS232 Port
Low-cost VGA
Interfaces
10/100/1000 PHY
Dip Switches
User LEDs
2x Digilent Headers
Miscellaneous IO
Push Switches
Power
2.5V
Regulator
1.8
Regulator
1.2V
Regulator
0.9V Termination
Regulator
3.3V R
Regulator
Connector
EXP Slot
(168 IO)
Connector
Parallel Cable IV
JTAG Port
Eridon
Debug/Comm Port
Configuration and
Debug
System ACE
Connector
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Functional Description R
Xilinx Spartan-3A DSP FPGA
The Xilinx XC3SD1800A-4FG676C device designed into the Spartan-3A DSP Starter
Platform provides four I/O banks — two are fixed voltage and two are I/O voltage-
selectable. The four I/O banks are described in Table 2 and detailed I/O pin usage is
provided throughout this document. In some cases, voltage translation of I/O signals may
be necessary in order to meet requirements of peripheral devices that are connected to a
particular I/O bank, or EXP modules plugged into the EXP expansion connectors. Table 2
indicates where voltage translation will occur or, if a source is fixed at a particular voltage,
even though the bank to which it is connected may be at different I/O voltage.
Ta b l e 2 : XC3SD1800A Input and Output Allocation
I/O Bank
Number I/O Function
Number
of I/O
Pins
Number of
Input-only
Pins
Voltage
Translation
Bank I/O
Voltage
0EXPConnectorJX1840
2.5 or 3.3 V
0 User Pushbuttons 0 4
08-posDIPSwitch08
0 125 MHz Clock 1 0
0 SMA Connector 1 0
0Configuration(PUDC_B)1 0
1 SystemACE Module 28 1
3.3 V
1 J3 Flash Memory 28 0
1 SPI Selects (4) 4 0
1 DAC 14 0
1UserLEDs80
1 Digilent Connectors 8 (1) 0
1 RS-232 2 0
1EridonDebugConnector4 0
1 Configuration (Suspend) 1 0
1 25.175 MHz Clock 1 0
1 EXP Connector JX2 8 0 2.5 or 3.3 V
2EXPConnectorJX2760
2.5 or 3.3 V
2 J3 Flash Memory 8 [Ref 1] 0 2.5 or 3.3 V
2SPI4
[Ref 1] 0
2Configuration50
2 Plug-in Reset 1 0
2 LED 1 0
2Power-onReset01
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UG454 (v1.1) January 30, 2009
Functional Description
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Memory
The Spartan-3A DSP Starter Platform is populated with both high-speed RAM (128Mbytes
DDR2) and non-volatile ROM (16Mbytes parallel, and 64Mbit serial) to support various
types of applications. Additionally, a 50-pin connector is provided for SystemACE
interface (not included) that can be used to configure the Spartan-3A DSP FPGA, and to
provide storage for A/V media files from removable Compact Flash cards. Figure 2 shows
a high-level block diagram of the memory interfaces on this board.
Micron DDR2 SDRAM Interface
Two Micron MT47H32M16BM DDR2 devices provide 128Mbytes of 32-bit wide memory
to the FPGA. The FPGA DDR2 interface supports SSTL18 signaling and all DDR2 signals
are controlled impedance. The DDR2 data, mask, and strobe signals are matched length
across all signals. Using I/O Bank 3 the DDR2 pinout on the FPGA is MIG-compliant.
Pinout of the FPGA DDR2 interface is provided in Table 3 below.
SSTL18 Class I termination (series termination at the driving node and stub termination at
the receiving node) is used between the FPGA and DDR on all unidirectional signals, such
as Address, Control, and Clock. SSTL18 Class II termination (series and stub termination
at both nodes) is used on the FPGA side of the interface for all bidirectional signals such as
Data and Strobe. No board terminations are implemented for Data and Strobe on the
memory side. ODT is strapped as enabled, although an FPGA I/O is still connected to
allow the FPGA to drive this off. Note that stub terminations for address and control
signals are not populated in production based on HyperLynx simulation and exhaustive,
error-free testing of the FPGA-DDR2 interface at 133MHz.
3 DDR2 Memory 73 0 1.8 V
3 Ethernet 17 13 2.5 V
Note:
1. FLASH_DO and SPI_MISO are a common pin.
Ta b l e 2 : XC3SD1800A Input and Output Allocation (Cont’d)
I/O Bank
Number I/O Function
Number
of I/O
Pins
Number of
Input-only
Pins
Voltage
Translation
Bank I/O
Voltage
X-Ref Target - Figure 2
Figure 2: Spartan-3A DSP Memory Interface
Spartan
3A DSP
FPGA
System ACE
Connector
DDR2 SDRAM
(128 MB)
Parallel Flash
(16 MB)
Serial Flash
(64 Mbit)
32
8
1
UG454_02_050908
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Functional Description R
Figure 3 shows terminator locations relative to the FPGA and the DDR2 memory devices.
The following guidelines were used in the design of the DDR2 interface to the Spartan-3A
DSP FPGA. These guidelines are based on Micron recommendations and board level
simulation. Ideal impedance values are listed. Actual values may vary.
•Memory clocks routed differentially
•50-ohm controlled trace impedance
•24-ohm series termination on bidirectional signals at the FPGA
•Parallel termination following the memory device connection on all signals
•60-ohm pull-up resistor to the termination supply (0.9V) on data and strobe signals at
the FPGA
X-Ref Target - Figure 3
Figure 3: DDR2 SDRAM Interface
UDM0
LDM0
Spartan
3A DSP
FPGA
Stub terminationsare not necessary on the DM
tracesbecause they are unidirectional signals.
32M x 16
DDR2 SDRAM
(64MB)
32M x 16
DDR2 SDRAM
(64MB)
Stub terminationsare not necessary on the DM
tracesbecause they are unidirectional signals.
Stub TerminationsNear FPGA
SeriesTerminationsNear FPGA
SeriesTerminationsNear FPGA
Stub Terminations
at Split points
Stub Termination Near FPGA
LDQS1_n
LDQS1_p
LDQS0_n
LDQS0_p
CLK0_n
CLK0_p
Data[15:0]
CLK1_n
CLK1_p
UDQS0_p
UDQS0_n
UDQS1_p
UDQS1_n
UDM1
LDM1
Data[31:16]
Addr [13:0]
Control (RAS#, CAS#,
WE#, BS0, BS1, CS#)
Control (CKE)
UG454_03_050908
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