Xilinx Spartan-3A DSP FPGA Series User manual

R
Spartan-3A DSP Starter
Platform User Guide
UG454 (v1.1) January 30, 2009
www.BDTIC.com/XILINX

R
Spartan-3A DSP Starter Platform User Guide www.xilinx.com UG454 (v1.1) January 30, 2009
© 2007-2009 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx,
Inc. All other trademarks are the property of their respective owners.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one
possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any
claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any
warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that
this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
Revision History
The following table shows the revision history for this document.
Date Version Revision
10/3/07 1.0 Initial Xilinx release.
1/30/09 1.1 Updated to v1.1.
www.BDTIC.com/XILINX

UG454 (v1.1) January 30, 2009 www.xilinx.com Spartan-3A DSP Starter Platform User Guide
Table of Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Design Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Xilinx Spartan-3A DSP FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Micron DDR2 SDRAM Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Intel J3 Parallel Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Intel S33 Serial Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SystemACE Module (SAM) Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
National Semiconductor 10/100/1000 Ethernet PHY. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPI Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Digilent Headers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Eridon Debug Connector (This is not a Serial ATA Connector) . . . . . . . . . . . . . . . . . . . 18
VGA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Miscellaneous I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Expansion Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
EXP Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Board Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Board Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PCB Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
www.BDTIC.com/XILINX

Spartan-3A DSP Starter Platform User Guide www.xilinx.com UG454 (v1.1) January 30, 2009
www.BDTIC.com/XILINX

Spartan-3A DSP Starter Platform User Guide www.xilinx.com 29
UG454 (v1.1) January 30, 2009
R
Spartan-3A DSP 1800A Board Features
Overview
The purpose of this manual is to describe the functionality and contents of the Spartan®-
3A DSP Starter Platform from Xilinx. This document includes instructions for operating
the board and descriptions of the hardware features.
For more information about this product, reference designs, and additional
documentation, please visit the product home page found at
www.xilinx.com/s3adspstarter or www.xilinx.com/s3adspmb or
www.xilinx.com/s3adsp_sk.
Design Description
The Spartan-3A Starter Platform provides a platform for engineers designing with the
Xilinx Spartan-3A DSP FPGA. The board provides the hardware to not only evaluate the
advanced features of the Spartan-3A DSP, but also to implement complete user
applications using peripherals on the Spartan-3A DSP Starter Platform and EXP modules,
or both, plugged into EXP expansion connectors on the Spartan-3A DSP Starter Platform.
Features
The Spartan-3A DSP Starter Platform provides the following features:
•Xilinx 3SD1800A-FG676 FPGA
•Clocks
♦125 MHz LVTTL SMT oscillator
♦LVTTL oscillator socket
♦25.175 MHz LVTTL SMT oscillator (video clock)
•Memory
♦32M x 32 (128 MB) DDR2 SDRAM
♦16Mx8 parallel and BPI configuration flash
♦64Mb SPI Configuration and Storage Flash (with 4 extra SPI selects)
•Interfaces
♦10/100/1000 PHY
♦JTAG programming and configuration Port
♦RS232 Port
♦Low-cost VGA
www.BDTIC.com/XILINX

30 www.xilinx.com Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
Design Description R
•Buttons and switches
♦8 User LEDs
♦8-position user DIP switch
♦4 User push button switches
♦Reset push button switch
•User I/O and expansion
♦Digilent 6-pin header (2)
♦EXP expansion connector (2)
•Configuration and debug
♦JTAG
♦SystemACE™ module connector
♦Eridon debug connector (SATA)
Ordering Information
Table 1 lists the evaluation kit part numbers.
Part Number Hardware
HW-SD1800A-DSP-SB-UNI-G XtremeDSP Starter Platform - Spartan-3A DSP 1800A
Edition
Ta b l e 1 : Evaluation Kit and Hardware Ordering Information
www.BDTIC.com/XILINX

Spartan-3A DSP Starter Platform User Guide www.xilinx.com 31
UG454 (v1.1) January 30, 2009
Functional Description
R
Functional Description
A high-level block diagram of the Spartan-3A DSP Starter Platform is shown in Figure 1.
Subsequent sections provide details of the board design.
X-Ref Target - Figure 1
Figure 1: Spartan-3A DSP Starter Platform Block Diagram
3SD1800A-FG676
UG454_01_050908
16 MB Parallel NOR Flash
(16M x 8)
16 MbSPI Flash
Memory
128 MB DDR2
(32M X 32)
LVTTL OSC Socket
25.175 MHz VGA Clock
Clock Sources
125 MHz LVTTL OSC
RS232 Port
Low-cost VGA
Interfaces
10/100/1000 PHY
Dip Switches
User LEDs
2x Digilent Headers
Miscellaneous IO
Push Switches
Power
2.5V
Regulator
1.8
Regulator
1.2V
Regulator
0.9V Termination
Regulator
3.3V R
Regulator
Connector
EXP Slot
(168 IO)
Connector
Parallel Cable IV
JTAG Port
Eridon
Debug/Comm Port
Configuration and
Debug
System ACE
Connector
www.BDTIC.com/XILINX

32 www.xilinx.com Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
Functional Description R
Xilinx Spartan-3A DSP FPGA
The Xilinx XC3SD1800A-4FG676C device designed into the Spartan-3A DSP Starter
Platform provides four I/O banks — two are fixed voltage and two are I/O voltage-
selectable. The four I/O banks are described in Table 2 and detailed I/O pin usage is
provided throughout this document. In some cases, voltage translation of I/O signals may
be necessary in order to meet requirements of peripheral devices that are connected to a
particular I/O bank, or EXP modules plugged into the EXP expansion connectors. Table 2
indicates where voltage translation will occur or, if a source is fixed at a particular voltage,
even though the bank to which it is connected may be at different I/O voltage.
Ta b l e 2 : XC3SD1800A Input and Output Allocation
I/O Bank
Number I/O Function
Number
of I/O
Pins
Number of
Input-only
Pins
Voltage
Translation
Bank I/O
Voltage
0EXPConnectorJX1840
2.5 or 3.3 V
0 User Pushbuttons 0 4
08-posDIPSwitch08
0 125 MHz Clock 1 0
0 SMA Connector 1 0
0Configuration(PUDC_B)1 0
1 SystemACE Module 28 1
3.3 V
1 J3 Flash Memory 28 0
1 SPI Selects (4) 4 0
1 DAC 14 0
1UserLEDs80
1 Digilent Connectors 8 (1) 0
1 RS-232 2 0
1EridonDebugConnector4 0
1 Configuration (Suspend) 1 0
1 25.175 MHz Clock 1 0
1 EXP Connector JX2 8 0 2.5 or 3.3 V
2EXPConnectorJX2760
2.5 or 3.3 V
2 J3 Flash Memory 8 [Ref 1] 0 2.5 or 3.3 V
2SPI4
[Ref 1] 0
2Configuration50
2 Plug-in Reset 1 0
2 LED 1 0
2Power-onReset01
www.BDTIC.com/XILINX

Spartan-3A DSP Starter Platform User Guide www.xilinx.com 33
UG454 (v1.1) January 30, 2009
Functional Description
R
Memory
The Spartan-3A DSP Starter Platform is populated with both high-speed RAM (128Mbytes
DDR2) and non-volatile ROM (16Mbytes parallel, and 64Mbit serial) to support various
types of applications. Additionally, a 50-pin connector is provided for SystemACE
interface (not included) that can be used to configure the Spartan-3A DSP FPGA, and to
provide storage for A/V media files from removable Compact Flash cards. Figure 2 shows
a high-level block diagram of the memory interfaces on this board.
Micron DDR2 SDRAM Interface
Two Micron MT47H32M16BM DDR2 devices provide 128Mbytes of 32-bit wide memory
to the FPGA. The FPGA DDR2 interface supports SSTL18 signaling and all DDR2 signals
are controlled impedance. The DDR2 data, mask, and strobe signals are matched length
across all signals. Using I/O Bank 3 the DDR2 pinout on the FPGA is MIG-compliant.
Pinout of the FPGA DDR2 interface is provided in Table 3 below.
SSTL18 Class I termination (series termination at the driving node and stub termination at
the receiving node) is used between the FPGA and DDR on all unidirectional signals, such
as Address, Control, and Clock. SSTL18 Class II termination (series and stub termination
at both nodes) is used on the FPGA side of the interface for all bidirectional signals such as
Data and Strobe. No board terminations are implemented for Data and Strobe on the
memory side. ODT is strapped as enabled, although an FPGA I/O is still connected to
allow the FPGA to drive this off. Note that stub terminations for address and control
signals are not populated in production based on HyperLynx simulation and exhaustive,
error-free testing of the FPGA-DDR2 interface at 133MHz.
3 DDR2 Memory 73 0 1.8 V
3 Ethernet 17 13 2.5 V
Note:
1. FLASH_DO and SPI_MISO are a common pin.
Ta b l e 2 : XC3SD1800A Input and Output Allocation (Cont’d)
I/O Bank
Number I/O Function
Number
of I/O
Pins
Number of
Input-only
Pins
Voltage
Translation
Bank I/O
Voltage
X-Ref Target - Figure 2
Figure 2: Spartan-3A DSP Memory Interface
Spartan
3A DSP
FPGA
System ACE
Connector
DDR2 SDRAM
(128 MB)
Parallel Flash
(16 MB)
Serial Flash
(64 Mbit)
32
8
1
UG454_02_050908
www.BDTIC.com/XILINX

34 www.xilinx.com Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
Functional Description R
Figure 3 shows terminator locations relative to the FPGA and the DDR2 memory devices.
The following guidelines were used in the design of the DDR2 interface to the Spartan-3A
DSP FPGA. These guidelines are based on Micron recommendations and board level
simulation. Ideal impedance values are listed. Actual values may vary.
•Memory clocks routed differentially
•50-ohm controlled trace impedance
•24-ohm series termination on bidirectional signals at the FPGA
•Parallel termination following the memory device connection on all signals
•60-ohm pull-up resistor to the termination supply (0.9V) on data and strobe signals at
the FPGA
X-Ref Target - Figure 3
Figure 3: DDR2 SDRAM Interface
UDM0
LDM0
Spartan
3A DSP
FPGA
Stub terminationsare not necessary on the DM
tracesbecause they are unidirectional signals.
32M x 16
DDR2 SDRAM
(64MB)
32M x 16
DDR2 SDRAM
(64MB)
Stub terminationsare not necessary on the DM
tracesbecause they are unidirectional signals.
Stub TerminationsNear FPGA
SeriesTerminationsNear FPGA
SeriesTerminationsNear FPGA
Stub Terminations
at Split points
Stub Termination Near FPGA
LDQS1_n
LDQS1_p
LDQS0_n
LDQS0_p
CLK0_n
CLK0_p
Data[15:0]
CLK1_n
CLK1_p
UDQS0_p
UDQS0_n
UDQS1_p
UDQS1_n
UDM1
LDM1
Data[31:16]
Addr [13:0]
Control (RAS#, CAS#,
WE#, BS0, BS1, CS#)
Control (CKE)
UG454_03_050908
www.BDTIC.com/XILINX

Spartan-3A DSP Starter Platform User Guide www.xilinx.com 35
UG454 (v1.1) January 30, 2009
Functional Description
R
•60-ohm pull-up resistor to the termination supply at the split-point of shared signals
(control, address)
•Termination supply that can both source and sink current
•Feedback clock routed with twice the length to simulate the total flight time
All DDR2 routing is length-matched within certain tolerances; these are:
•Members of a differential pair matched to +/-10mil
•DQ, DQS, DM and CK matched to +/- 45mil
•Control matched to +/- 100mil of data interface
•RST_DQS_DIV and MB_FB_CLK matched to +/- 45mil of sum of average DQS and
average CK
The DDR2 signals are connected to I/O Bank 3 of the Spartan-3 SA DSP FPGA. The output
supply pins (VCCO) for Bank 3 is connected to 1.8 Volts. A Texas Instruments TPS51116
Buck Controller and ancillary circuitry provides the 1.8V DDR2 power, the 0.9V
termination voltage (FPGA_0.9V_TT) and the DDR2 reference voltage
(FPGA_DDR2_VREF). This power source also supplies the 1.8V core voltage to the
Ethernet PHY.
Ta b l e 3 : FPGA DDR2 Interface Pinout
DDR2 Signal FPGA Pin
Number DDR2 Signal FPGA Pin Number
FPGA_DDR_A0 J5 FPGA_DDR_LDM_0 V2
FPGA_DDR_A1 M8 FPGA_DDR_LDM_0 V1
FPGA_DDR_A2 M10 FPGA_DDR_LDM_1 R2
FPGA_DDR_A3 K4 FPGA_DDR_UDM_1 M6
FPGA_DDR_A4 K5 DDR2_ODT_Control G3
FPGA_DDR_A5 K2 FPGA_DDR_D0 U9
FPGA_DDR_A6 K3 FPGA_DDR_D1 V8
FPGA_DDR_A7 L3 FPGA_DDR_D2 AB1
FPGA_DDR_A8 L4 FPGA_DDR_D3 AC1
FPGA_DDR_A9 M7 FPGA_DDR_D4 Y5
FPGA_DDR_A10 M8 FPGA_DDR_D5 Y6
FPGA_DDR_A11 M3 FPGA_DDR_D6 U7
FPGA_DDR_A12 M4 FPGA_DDR_D7 U8
FPGA_DDR_BS0 K6 FPGA_DDR_D8 AA2
FPGA_DDR_BS1 J4 FPGA_DDR_D9 AA3
FPGA_DDR_RAS# H1 FPGA_DDR_D10 Y1
FPGA_DDR_CAS# L10 FPGA_DDR_D11 Y2
FPGA_DDR_WE# L9 FPGA_DDR_D12 T7
FPGA_DDR_CS# H2 FPGA_DDR_D13 U6
FPGA_DDR_CKE L7 FPGA_DDR_D14 U5
www.BDTIC.com/XILINX

36 www.xilinx.com Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
Functional Description R
Intel J3 Parallel Flash
The Flash memory consists of a single J3 Flash device in a TSOP-56 package and connected
to the dedicated BPI configuration port of the FPGA. The Intel JS28F128J3D is a 128-Mbit
device organized as 16-Mbit x 8. The installed J3 device supports asynchronous memory
accesses at a 75 nanosecond access time. The Flash interface is split across two banks, with
all but the 8 data bits connected to Bank 1 (3.3V), and the 8 data bits connected to Bank 2.
Because Bank 2 may be set to either 2.5V or 3.3V, the 8 Flash data bits are interfaced to Bank
2 via a Texas Instruments SN74AVC8T245 dual-supply bus transceiver with the Flash
Write Enable (FLASH_WE#) signal controlling transceiver direction and the Flash chip
select signal (FLASH_CS) enabling the transceiver. The maximum propagation delay of
2.9 nanoseconds through this transceiver is not significant with the 75 nanosecond Flash
access time. Jumper JP1 may be used to write-protect the Flash memory by placing a shunt
across pins 2 and 3. Default setting is JP1 1:2. Table 4 details the Parallel Flash FPGA
interface pinout.
FPGA_DDR_CLK_0 N1 FPGA_DDR_D15 V5
FPGA_DDR_CLK_0# N2 FPGA_DDR_D16 R8
FPGA_DDR_CLK_1 N5 FPGA_DDR_D17 R7
FPGA_DDR_CLK_1# N4 FPGA_DDR_D18 U1
MB_FB_CLK (out) M2 FPGA_DDR_D19 U2
MB_FB_CLK (in) N7 FPGA_DDR_D20 P8
RST_DQS_DIV (out) T10 FPGA_DDR_D21 P9
RST_DQS_DIV (in) T9 FPGA_DDR_D22 R5
FPGA_DDR_LDQS_0 V7 FPGA_DDR_D23 R6
FPGA_DDR_LDQS_#0 V6 FPGA_DDR_D24 P7
FPGA_DDR_LDQS_1 W3 FPGA_DDR_D25 P6
FPGA_DDR_LDQS_#_1 W4 FPGA_DDR_D26 T3
FPGA_DDR_UDQS_0 T5 FPGA_DDR_D27 T4
FPGA_DDR_UDQS_#0 U4 FPGA_DDR_D28 N9
FPGA_DDR_UDQS_1 R2 FPGA_DDR_D29 P10
FPGA_DDR_UDQS_#_1 R4 FPGA_DDR_D30 P4
FPGA_DDR_D31 P3
Ta b l e 3 : FPGA DDR2 Interface Pinout (Cont’d)
DDR2 Signal FPGA Pin
Number DDR2 Signal FPGA Pin Number
www.BDTIC.com/XILINX

J3 Flash Signal FPGA Pin No. J3 Flash Signal FPGA Pin No.
Spartan-3A DSP Starter Platform User Guide www.xilinx.com 37
UG454 (v1.1) January 30, 2009
Functional Description
R
Intel S33 Serial Flash
64Mbits of serial flash memory is provided by an Intel QH25F640S33B8 device interfaced
to the Spartan 3A device via its dedicated SPI configuration interface. Jumper JP8 may be
utilized to write-protect the device by placing a shunt across JP8 1:2 (default is open). The
SPI interface signals are also connected to 0.1” 2x6 header J10 along with four additional
SPI select lines (SPISEL_[1:4]); signals in Table 6 marked with an asterisk are common to
both the SPI serial Flash and header J10. The built-in SPI interface is available only during
configuration. The user must build the SPI controller during normal operation, or use IP
available in Xilinx Platform Studio (XPS).
J3 Flash Signal FPGA Pin J3 Flash Signal FPGA Pin
Ta b l e 4 : Parallel Flash Interface Pinout
FLASH_A0 AC23 FLASH_A18 J26
FLASH_A1 AC24 FLASH_A19 J25
FLASH_A2 R21 FLASH_A20 J21
FLASH_A3 R22 FLASH_A21 H21
FLASH_A4 T23 FLASH_A22 C26
FLASH_A5 T24 FLASH_A23 C25
FLASH_A6 R18 FLASH_WE# Y20
FLASH_A7 R17 FLASH_OE# AE26
FLASH_A8 R25 FLASH_CE# AE25
FLASH_A9 R26 FLASH_Reset# N24
FLASH_A10 M26 FLASH_D0 AF24
FLASH_A11 M25 FLASH_D1 AE18
FLASH_A12 L24 FLASH_D2 AF18
FLASH_A13 M23 FLASH_D3 Y15
FLASH_A14 N18 FLASH_D4 AE12
FLASH_A15 N17 FLASH_D5 AF12
FLASH_A16 N20 FLASH_D6 AF10
FLASH_A17 M20 FLASH_D7 AE10
Ta b l e 5 : Serial (SPI) Flash Interface Pinout
SPISEL_1 W20 * SPI_SEL# AA7
SPISEL_1 W21 * SPI_CLK AE24
SPISEL_1 AD26 * SPI_MOSI AB15
SPISEL_1 AC25 * SPI_MISO AF24
www.BDTIC.com/XILINX

38 www.xilinx.com Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
Functional Description R
SystemACE Module (SAM) Connector
The Spartan-3A DSP Starter Platform provides a SAM 50-pin connector (J8) for
SystemACE interface that can be used to configure the Spartan-3A DSP FPGA, and
provide storage for A/V media files from removable Compact Flash cards. The Avnet
SystemACE Module (DS-KIT-SYSTEMACE) can be used to perform both of these
functions.
Further information on the Avnet SystemACE Module may be found at:
www.em.avnet.com/systemace. This SystemACE module is not provided as part of this
product.
Figure 4 shows the SystemACE Module connected to the header on the Spartan-3A DSP
board; Table 6 provides the pinout of SAM connector J8. The clock from the SAM
connector (Pin 6) is routed to GCLK1 on Bank 2 of the FPGA.
X-Ref Target - Figure 4
Figure 4: SystemACE Module Interconnections
System ACE
Controller
50-pin Connector
(connectsto a50-pin square post
header on the main board)
CF Connector
JTAG Test Port
(includesVCC and GND)
JTAG Configuration Port
(includesVCC and GND for
stand-alone applications)
46
2
JTAG
Configuration
Port
MPU
Interface
Misc
Signals
Reset
and
Clock
Power
and
Ground
28 10
UG454_04_050908
www.BDTIC.com/XILINX

FPGA Pin
Number
SystemACE
Signal Name
SAM Connector
Pin Number
SystemACE
Signal Name
FPGA Pin
Number
Spartan-3A DSP Starter Platform User Guide www.xilinx.com 39
UG454 (v1.1) January 30, 2009
Functional Description
R
Interfaces
The Spartan-3A DSP FPGA has access to Ethernet and RS232 physical layer transceivers
for communication purposes. Network access is provided by a 10/100/1000 Mb/s
Ethernet PHY, which is connected to the Spartan-3A via a standard GMII interface. The
PHY connects to the outside world with a standard RJ45 connector. Serial port
communication to the FPGA fabric is provided through an RS232 transceiver using a DB9
DCE female connector.
Ta b l e 6 : SAM Interface Signals
— 3.3 V 1 2 3.3 V —
E23 JTAG_TDO 3 4 GND —
D4 JTAG_TMS 5 6 SAM_CLK AA14
G7 JTAG_TDI 7 8 GND —
A2 FPGA_PROGn 9 10 JTAG_TCK A25
—GND1112GND—
V22 SAM_OEn 13 14 FPGA_INITn AA15
AC26 SAM_A0 14 16 SAM_WEn V24
AB23 SAM_A2 17 18 SAM_A1 AB26
— 2.5 V 19 20 SAM_A3 AB24
AA23 SAM_D0 21 22 2.5 V —
U20 SAM_D2 23 24 SAM_D1 V21
AA25 SAM_D4 25 26 SAM_D3 AA24
U18 SAM_D6 27 28 SAM_D5 U19
Y23 SAM_D8 29 30 SAM_D7 Y22
T20 SAM_D10 31 32 SAM_D9 U21
Y25 SAM_D12 33 34 SAM_D11 Y24
T17 SAM_D14 35 36 SAM_D13 T18
V18 SAM_A4 37 38 SAM_D15 W23
AA22 SAM_A6 39 40 SAM_A5 V19
L23 SAM_IRQ 41 42 GND —
V23 Sam_RESETn 43 44 SAM_CEn V25
AB21 FPGA_DONE 45 46 SAM_BRDY P21
AB24 FPGA_CCLK 47 48 BITSTREAM* AF24
— GND 49 50 NC (Key) —
www.BDTIC.com/XILINX

40 www.xilinx.com Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
Functional Description R
Other interfaces consist of two 0.1” 6-pin headers to accept Digilent plug-in modules, a 7-
pin Serial ATA connector ( this is not a serial ATA interface) to connect to an Eridon debug
module, and a 0.1” 2 x 6 header for SPI interface expansion.
National Semiconductor 10/100/1000 Ethernet PHY
The PHY is a National DP83865DVH Gig PHYTER“ V. The DP83865 is a low power
version of the National Gig PHYTER V with a 1.8V core voltage and 2.5V I/O voltage. The
PHY also supports 3.3V I/O, but the 2.5V option is used on the board. The PHY is
connected to a Tyco-AMP RJ-45 jack with integrated magnetics (part number: 1-6605833-1).
The jack also integrates two LEDs and their corresponding resistors as well as several other
passive components. External logic is used to logically OR the three link indicators for 10,
100 and 1000 Mb/s to drive a Link LED on the RJ-45 jack. The external logic is for the
default strap options and may not work if the strap options are changed. Four more LEDs
are provided on the board for status indication. These LEDs indicate Link at 10 Mb/s, Link
at 100 Mb/s, Link at 1000 Mb/s and Full Duplex operation. The PHY clock is generated
from its own 25 MHz crystal (FOX FX325BS).
Figure 5 shows a high-level block diagram of the interface to the DP83865 Tri-mode
Ethernet PHY. The PHY signal connections at the FPGA are listed in Table 7. These signals
are connected to FPGA Bank 3 which is fixed at +1.8V I/O voltage, necessitating voltage
translation between +1.8V and +2.5V to match the PHY I/O voltage requirements.
X-Ref Target - Figure 5
Figure 5: 10/100/1000 Mb/s Ethernet Interface
Spartan
3A DSP
FPGA
National 10/100/1000 PHY
UG454_05_050908
Crystal
25 MHz
LEDs
data_tx[7:0]
clk_tx
data_rx[7:0]
clk_rx
control_rx
clk_to_MACgbe_mclk
control_tx
gtxclk
reset#gbe_rstn
Receive Transmit
10/100/1000 Magnetics
RJ45 Connector
MDIA_P
MDIA_N
MDIA_P
MDIA_N
MDIA_P
MDIA_N
MDIA_P
MDIA_N
www.BDTIC.com/XILINX

Ethernet PHY Signal FPGA Pin Ethernet PHY Signal FPGA Pin
Spartan-3A DSP Starter Platform User Guide www.xilinx.com 41
UG454 (v1.1) January 30, 2009
Functional Description
R
The PHY address is set to 0b00001 by default. PHY address 0b00000 is reserved for a test
mode and should not be used. Three-pad resistor jumpers are used to set the strapping
options. These jumper pads provide the user with the ability to change the settings by
moving the resistors. The dual-function pins that are used for both a strapping option and
to drive an LED have a set of two jumpers per pin. The dual-function pins are indicated by
an asterisk in the table.
The default options as indicated in Table 8 are Auto-Negotiation enabled, Full Duplex
mode, Speed advertised as 10/100/1000 Mb/s, PHY address 0b00001, IEEE Compliant
and Non-compliant support, straight cable in non-MDIX mode, auto-MDIX mode enabled,
Single node (NIC) and CLK_TO_MAC enabled. These and other settings are enabled by
three-pad jumpers with a resistor connecting either pads 1 and 2 or pads 2 and 3.
Ta b l e 7 : Ethernet PHY Interface Signals
ETH_Tx_D J8 ETH_COL Y3
ETH_Tx_D J9 ETH_INT# J1
ETH_Tx_D B2 ETH_Rx_DV D1
ETH_Tx_D B1 ETH_Rx_ER J3
ETH_Tx_D G6 ETH_MCLK N6
ETH_Tx_D H7 ETH_Rx_CLK P1
ETH_Tx_D K9 ETH_Tx_CLK P2
ETH_Tx_D K8 ETH_Rx_D0 C2
ETH_Tx_EN D3 ETH_Rx_D1 G2
ETH_Tx_ER E4 ETH_Rx_D2 G5
ETH_GTX_CLK E3 ETH_Rx_D3 D2
ETH_MDC F4 ETH_Rx_D4 Ab3
ETH_MDIO F5 ETH_Rx_D5 Aa4
ETH_RST# G4 ETH_Rx_D6 Ab4
ETH_CRS G1 ETH_Rx_D7 Y4
www.BDTIC.com/XILINX

Function Jumper
Installation Resistor Mode Enabled
Speed Selection: (Auto-Neg enabled)
Speed1 Speed0 Speed Advertised
1 1 1000BASE-T, 10BASE-T
1 0 1000BASE-T
0 1 1000BASE-T, 100BASE-Tx
0 0 10BASE-T
Default: 1000BASE-T, 100BASE-TX,
10BASE-T
42 www.xilinx.com Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
Functional Description R
Ta b l e 8 : Ethernet PHY Hardware Strapping Options
Auto Negotiation
JT8: Pins 1-2 0 Ohm Auto-negation enabled (default)
JT9: Pins 1-2
JT8: Pins 2-3 0 Ohm Auto-negation disabled
JT9: Pins 2-3
Full/Half Duplex*
JT10: Pins 1-2 0 Ohm Full Duplex (default)
JT10: Pins 1-2
JT10: Pins 2-3 0 Ohm Half Duplex
JT11: Pins 2-3
Speed 1*
JT12: Pins 1-2
JT13: Pins 1-1
(Speed1 – 0)
0 ohm
Speed 0*
JT6: Pins 1-2
JT7: Pins 1-1
(Speed0 – 0)
0 Ohm
PHY address 0*
JT14: Pins 1-2
0 Ohm
PHY Address 0b00001 (default)
JT15: Pins 1-2
JT24: Pins 2-3 PHY Address 0b00000
JT25: Pins 2-3
Non-IEEE
Compliant Mode
JT1: Pins 1-2 1 K
Compliant and non-compliant operation
(default)
JT1: Pins 2-3 Inhibits non-compliant operation
Manual MDIX
Setting
JT39: Pins 1-2 1 K Straight Mode (default)
JT2: Pins 2-3 Cross-over Mode
Auto MDIX
Setting
JT4: Pins 1-2
1 K
Automatic Pair Swap – MDIX (default)
JT4: Pins 2-3 Set to manual preset – Manual MDIX
Setting (JT12)
Multiple Node
Enable
JT3: Pins 1-2 1 K Single node – NIC (default)
JT3: Pins 2-3 Multiple node priority – switch/hub
Clock to MAC
Enable
JT5: Pins 1-2 1 K CLK_TO_MAC output enabled (default)
JT5: Pins 2-3 CLK_TO_MAC output disabled
www.BDTIC.com/XILINX

Spartan-3A DSP Starter Platform User Guide www.xilinx.com 43
UG454 (v1.1) January 30, 2009
Functional Description
R
The auto-MDIX mode provides automatic swapping of the differential pairs. This allows
the PHY to work with either a straight-through cable or crossover cable. Use a CAT-5e or
CAT-6 Ethernet cable when operating at 1000 Mb/s (Gigabit Ethernet). The boundary-
scan Test Access Port (TAP) controller of the DP83865 must be in reset for normal
operation. This active low reset pin of the TAP (TRST) is pulled low through a 1K resistor
on the board.
RS232
The RS232 transceiver is a Texas Instruments MAX3221 device. This transceiver operates
at 3.3V with an internal charge pump to create the RS232 compatible output levels. The
RS232 interface is brought out on DB9 connector P2. This RS232 interface supports only
null-modem serial cables. A male-to-female serial cable should be used to plug J11 into a
standard PC serial port (male DB9). Table 9 shows the FPGA pin-out for the RS232
interface.
Net Name Description FGPA Pin Number
SPI Expansion
A 0.1” 2 x 6 header (J10) provides an expansion of the FPGA SPI interface. In addition to
the SPI signals SPI_SEL#, SPI_CLK, SPI_MOSI and SPI_MISO, four additional SPI select
signals are provides (SPISEL_1, SPISEL_2, SPISEL_3, and SPISEL_4). All SPI select signals
have 4.7K pull-ups, SPI_CLK has a 4.7K pull-down. 3.3V power and Ground are also
provided on J10. Table 10 lists and describes the J10 connections.
FPGA Pin
Number Signal J10 Pin
Number
J10 Pin
Number Signal FPGA Pin
Number
Digilent Headers
Two right-angle, 6 pin (1 x 6 female) Digilent headers (J6, J7) are provided on the Spartan-
3A DSP Starter Platform. Each header provides 3.3V power, Ground, and four I/Os. It has
the appearance of an SPI port, or can be used as 4 general purpose I/Os. Figure 6 shows the
pinout of the Digilent headers; Table 11 provides the FPGA pinout.
Ta b l e 9 : RS232 Signals
FPGA_RS232_Rx Receive data, RD N21
FPGA_RS232_Tx Transmit data, TD P22
Table 10: SPI Connector (J10)
W20 SPISEL_1 2 1 SPI_SEL# AA7
W21 SPISEL_2 4 3 SPI_MOSI Ab15
AD26 SPISEL_3 6 5 SPI_MISO AF24
AC25 SPISEL_4 8 7 SPI_CLK AE24
— GND 10 9 GND —
— 3.3 V 12 11 3.3 V —
www.BDTIC.com/XILINX

44 www.xilinx.com Spartan-3A DSP Starter Platform User Guide
UG454 (v1.1) January 30, 2009
Functional Description R
For Digilent modules, see:
http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral
&Cat=Peripheral.
J6 Signal FPGA Pin J7 Signal FPGA Pin
Debug Connector (This is not a Serial ATA Connector)
A Serial ATA connector (J3) provides a high-speed interface for use as a serial debug port
(not Serial ATA), but may be used as a general-purpose communication interface. Two 3.3V
LVDS differential pairs, nominally one transmit pair (DBG_Tx_p/DBG_Tx_n) and one
receive pair (DBG_Rx_p/DBG_Rx_n), provide this high-speed communication channel.
Common-mode of the transmit pair is set to 1.25V by resistor R11 to 3.3V and resistor R8 to
Ground. 100-ohm differential termination of the receive pair is provided by resistor R10.
Nominal trace impedance is 50-ohms, with 49.9-ohm series resistors placed close to the
FPGA. Table 12 identifies the connection of the J3 signals to the FPGA.
X-Ref Target - Figure 6
Figure 6: Digilent Header Pinout
J6
UG454_06_050908
DIGI2_1 GND +3.3V DIGI2_2 DIGI2_3 DIGI2_4
J7
DIGI1_1 GND +3.3V DIGI1_2 DIGI1_3 DIGI1_4
Table 11: Digilent Header Connections
DIGI2_1 K19 DIGI1_1 L18
DIGI2_2 K18 DIGI1_2 L17
DIGI2_3 F22 DIGI1_3 E24
DIGI2_4 G22 DIGI1_4 F23
Table 12: Debug Connector (J3)
J3 Pin Number Signal Name FPGA Pin
1GND—
2DBG_Tx_n D26
3 DBG_Tx_p E26
www.BDTIC.com/XILINX