Xilinx MicroBlaze User manual

MicroBlaze
Processor Reference
Guide
2016.1
UG984 (v2016.1) April 6, 2016
UG984 (v2016.2) June 8, 2016

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Revision History
The following table shows the revision history for this document.
Date Version Revision
03/20/2013 2013.1 Initial Xilinx release. This User Guide is derived from UG081.
06/19/2013 2013.2 Updated for Vivado 2013.2 release.
10/02/2013 2013.3 Updated for Vivado 2013.3 release.
12/18/2013 2013.4 Updated for Vivado 2013.4 release.
04/02/2014 2014.1 Updated for Vivado 2014.1 release:
• Added v9.3 to MicroBlaze release version code in PVR.
• Clarified availability and behavior of stack protection registers.
• Corrected description of LMB instruction and data bus exception.
• Included description of extended debug features, new in version 9.3:
performance monitoring, program trace and non-intrusive profiling.
• Included definition of Reset Mode signals, new in version 9.3.
• Clarified how the AXI4-Stream TLAST signal is handled.
• Added UltraScale and updated performance and resource utilization for 2014.1.
10/01/2014 2014.3 Updated for Vivado 2014.3 release:
• Corrected semantic description for PCMPEQ and PCMPNE in Table 2.1.
• Added version 9.4 to MicroBlaze release version code in PVR.
• Included description of external program trace, new in version 9.4
04/15/2015 2015.1 Updated for Vivado 2015.1 release:
• Included description of 16 word cache line length, new in version 9.5.
• Added version 9.5 to MicroBlaze release version code in PVR.
• Corrected description of supported endianness and parameter C_ENDIANNESS.
• Corrected description of outstanding reads for instruction and data cache.
• Updated FPGA configuration memory protection document reference [Ref 10].
• Corrected Bus Index Range definitions for Lockstep Comparison in Table 3-13.
• Clarified registers altered for IDIV instruction.
• Corrected PVR assembler mnemonics for MFS instruction.
• Updated performance and resource utilization for 2015.1.
• Added references to training resources.
04/06/2016 2016.1 Updated for Vivado 2016.1 release:
• Included description of address extension, new in version 9.6.
• Included description of pipeline pause functionality, new in version 9.6
• Included description of non-secure AXI access support, new in version 9.6.
• Included description of hibernate and suspend instructions, new in version 9.6.
• Added version 9.6 to MicroBlaze release version code in PVR.
• Corrected references to Table 2-45 and Table 2-46.
• Replaced references to the deprecated Xilinx Microprocessor Debugger (XMD)
with Xilinx System Debugger (XSDB).
• Removed C code function attributes svc_handler and svc_table_handler.
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Table of Contents
Chapter 1: Introduction
Guide Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 2: MicroBlaze Architecture
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Types and Endianness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Pipeline Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Privileged Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Virtual-Memory Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Reset, Interrupts, Exceptions, and Break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Stream Link Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Debug and Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Fault Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Lockstep Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Data Address Extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Chapter 3: MicroBlaze Signal Interface Description
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
MicroBlaze I/O Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
AXI4 and ACE Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Local Memory Bus (LMB) Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Lockstep Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Debug Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Trace Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
MicroBlaze Core Configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
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Chapter 4: MicroBlaze Application Binary Interface
Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Register Usage Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Stack Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Interrupt, Break and Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Chapter 5: MicroBlaze Instruction Set Architecture
Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Appendix A: Performance and Resource Utilization
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Appendix B: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Training Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
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Chapter 1
Introduction
The MicroBlaze™ Processor Reference Guide provides information about the 32-bit soft
processor, MicroBlaze, which is included in the Vivado® release. The document is intended
as a guide to the MicroBlaze hardware architecture.
Guide Contents
This guide contains the following chapters:
•Chapter 2, MicroBlaze Architecture, contains an overview of MicroBlaze features as well
as information on Big-Endian and Little-Endian bit-reversed format, 32-bit general
purpose registers, cache software support, and Fast Simplex Link interfaces.
•Chapter 3, MicroBlaze Signal Interface Description, describes the types of signal
interfaces that can be used to connect MicroBlaze.
•Chapter 4, MicroBlaze Application Binary Interface, describes the Application Binary
Interface important for developing software in assembly language for the soft
processor.
•Chapter 5, MicroBlaze Instruction Set Architecture, provides notation, formats, and
instructions for the Instruction Set Architecture of MicroBlaze.
•Appendix A, Performance and Resource Utilization, contains maximum frequencies and
resource utilization numbers for different configurations.
•Appendix B, Additional Resources and Legal Notices, provides links to documentation
and additional resources.
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Chapter 2
MicroBlaze Architecture
This chapter contains an overview of MicroBlaze™ features and detailed information on
MicroBlaze architecture including Big-Endian or Little-Endian bit-reversed format, 32-bit
general purpose registers, virtual-memory management, cache software support, and
AXI4-Stream interfaces.
Overview
The MicroBlaze™ embedded processor soft core is a reduced instruction set computer
(RISC) optimized for implementation in Xilinx® Field Programmable Gate Arrays (FPGAs).
Figure 2-1 shows a functional block diagram of the MicroBlaze core.
Figure 2-1: MicroBlaze Core Block Diagram
Data-sideInstruction-side
ILMB
bus interface bus interface
Instruction
Buffer
Program
Counter
Register File
32 X 32b
ALU
Instruction
Decode
Bus
IF
Bus
IF
I-Cache
D-Cache
Shift
Barrel Shift
Multiplier
Divider
FPU
Special
Purpose
Registers
Optional MicroBlaze feature
M_AXI_IP
UTLB
ITLB
DTLB
Memory Management Unit (MMU)
M_AXI_IC M_AXI_DC
Branch
Target
Cache
M0_AXIS..
S0_AXIS..
M15_AXIS
S15_AXIS
M_ACE_DC
M_ACE_IC
M_AXI_DP
DLMB
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Chapter 2: MicroBlaze Architecture
Features
The MicroBlaze soft core processor is highly configurable, allowing you to select a specific
set of features required by your design.
The fixed feature set of the processor includes:
• Thirty-two 32-bit general purpose registers
• 32-bit instruction word with three operands and two addressing modes
• Default 32-bit address bus, extensible to 64 bits on the data side
• Single issue pipeline
In addition to these fixed features, the MicroBlaze processor is parameterized to allow
selective enabling of additional functionality. Older (deprecated) versions of MicroBlaze
support a subset of the optional features described in this manual. Only the latest
(preferred) version of MicroBlaze (v9.6) supports all options.
Xilinx recommends that all new designs use the latest preferred version of the MicroBlaze
processor.
Table 2-1, page 7 provides an overview of the configurable features by MicroBlaze versions.
Table 2-1: Configurable Feature Overview by MicroBlaze Version
Feature MicroBlaze versions
v9.1 v9.2 v9.3 v9.4 v9.5 v9.6
Version Status deprecated deprecated deprecated deprecated deprecated preferred
Processor pipeline depth 3/5 3/5 3/5 3/5 3/5 3/5
Local Memory Bus (LMB) data side
interface
option option option option option option
Local Memory Bus (LMB) instruction
side interface
option option option option option option
Hardware barrel shifter option option option option option option
Hardware divider option option option option option option
Hardware debug logic option option option option option option
Stream link interfaces 0-15 AXI 0-15 AXI 0-15 AXI 0-15 AXI 0-15 AXI 0-15 AXI
Machine status set and clear
instructions
option option option option option option
Cache line word length 4, 8 4, 8 4, 8 4, 8 4, 8, 16 4, 8, 16
Hardware exception support option option option option option option
Pattern compare instructions option option option option option option
Floating point unit (FPU) option option option option option option
Disable hardware multiplier1option option option option option option
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Chapter 2: MicroBlaze Architecture
Hardware debug readable ESR and
EAR
Yes Yes Yes Yes Yes Yes
Processor Version Register (PVR) option option option option option option
Area or speed optimized option option option option option option
Hardware multiplier 64-bit result option option option option option option
LUT cache memory option option option option option option
Floating point conversion and square
root instructions
option option option option option option
Memory Management Unit (MMU) option option option option option option
Extended stream instructions option option option option option option
Use Cache Interface for All I-Cache
Memory Accesses
option option option option option option
Use Cache Interface for All D-Cache
Memory Accesses
option option option option option option
Use Write-back Caching Policy for D-
Cache
option option option option option option
Branch Target Cache (BTC) option option option option option option
Streams for I-Cache option option option option option option
Victim handling for I-Cache option option option option option option
Victim handling for D-Cache option option option option option option
AXI4 (M_AXI_DP) data side interface option option option option option option
AXI4 (M_AXI_IP) instruction side
interface
option option option option option option
AXI4 (M_AXI_DC) protocol for D-
Cache
option option option option option option
AXI4 (M_AXI_IC) protocol for I-Cache option option option option option option
AXI4 protocol for stream accesses option option option option option option
Fault tolerant features option option option option option option
Force distributed RAM for cache tags option option option option option option
Configurable cache data widths option option option option option option
Count Leading Zeros instruction option option option option option option
Memory Barrier instruction Yes Yes Yes Yes Yes Yes
Stack overflow and underflow
detection
option option option option option option
Allow stream instructions in user
mode
option option option option option option
Lockstep support option option option option option option
Configurable use of FPGA primitives option option option option option option
Table 2-1: Configurable Feature Overview by MicroBlaze Version
Feature MicroBlaze versions
v9.1 v9.2 v9.3 v9.4 v9.5 v9.6
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Chapter 2: MicroBlaze Architecture
Low-latency interrupt mode option option option option option option
Swap instructions option option option option option option
Sleep mode and sleep instruction Yes Yes Yes Yes Yes Yes
Relocatable base vectors option option option option option option
ACE (M_ACE_DC) protocol for D-
Cache
option option option option option option
ACE (M_ACE_IC) protocol for I-Cache option option option option option option
Extended debug: performance
monitoring, program trace, non-
intrusive profiling
option option option option
Reset mode: enter sleep or debug
halt at reset
option option option option
Extended debug: external program
trace
option option option
Extended data addressing option
Pipeline pause functionality Yes
Hibernate and suspend instructions Yes
Non-secure mode Yes
1. Used for saving DSP48E primitives.
Table 2-1: Configurable Feature Overview by MicroBlaze Version
Feature MicroBlaze versions
v9.1 v9.2 v9.3 v9.4 v9.5 v9.6
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Chapter 2: MicroBlaze Architecture
Data Types and Endianness
MicroBlaze uses Big-Endian or Little-Endian format to represent data, depending on the
selected endianness. The parameter C_ENDIANNESS is fixed to 1 (little-endian).
The hardware supported data types for MicroBlaze are word, half word, and byte. When
using the reversed load and store instructions LHUR, LWR, SHR and SWR, the bytes in the
data are reversed, as indicated by the byte-reversed order.
The bit and byte organization for each type is shown in the following tables.
Table 2-2: Word Data Type
Big-Endian Byte Address nn+1 n+2 n+3
Big-Endian Byte Significance MSByte LSByte
Big-Endian Byte Order nn+1 n+2 n+3
Big-Endian Byte-Reversed Order n+3 n+2 n+1 n
Little-Endian Byte Address n+3 n+2 n+1 n
Little-Endian Byte Significance MSByte LSByte
Little-Endian Byte Order n+3 n+2 n+1 n
Little-Endian Byte-Reversed Order nn+1 n+2 n+3
Bit Label 031
Bit Significance MSBit LSBit
Table 2-3: Half Word Data Type
Big-Endian Byte Address nn+1
Big-Endian Byte Significance MSByte LSByte
Big-Endian Byte Order nn+1
Big-Endian Byte-Reversed Order n+1 n
Little-Endian Byte Address n+1 n
Little-Endian Byte Significance MSByte LSByte
Little-Endian Byte Order n+1 n
Little-Endian Byte-Reversed Order nn+1
Bit Label 0 15
Bit Significance MSBit LSBit
Table 2-4: Byte Data Type
Byte Address n
Bit Label 0 7
Bit Significance MSBit LSBit
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Chapter 2: MicroBlaze Architecture
Instructions
Instruction Summary
All MicroBlaze instructions are 32 bits and are defined as either Type A or Type B. Type A
instructions have up to two source register operands and one destination register operand.
Type B instructions have one source register and a 16-bit immediate operand (which can be
extended to 32 bits by preceding the Type B instruction with an imm instruction). Type B
instructions have a single destination register operand. Instructions are provided in the
following functional categories: arithmetic, logical, branch, load/store, and special.
Table 2-6 lists the MicroBlaze instruction set. Refer to Chapter 5, MicroBlaze Instruction Set
Architecturefor more information on these instructions. Table 2-5 describes the instruction
set nomenclature used in the semantics of each instruction.
Table 2-5: Instruction Set Nomenclature
Symbol Description
Ra R0 - R31, General Purpose Register, source operand a
Rb R0 - R31, General Purpose Register, source operand b
Rd R0 - R31, General Purpose Register, destination operand
SPR[x]Special Purpose Register number x
MSR Machine Status Register = SPR[1]
ESR Exception Status Register = SPR[5]
EAR Exception Address Register = SPR[3]
FSR Floating Point Unit Status Register = SPR[7]
PVRxProcessor Version Register, where xis the register number = SPR[8192 + x]
BTR Branch Target Register = SPR[11]
PC Execute stage Program Counter = SPR[0]
x[y]Bit y of register x
x[y:z]Bit range yto z of register x
xBit inverted value of register x
Imm 16 bit immediate value
Immx x bit immediate value
FSLx4 bit AXI4-Stream port designator, where xis the port number
CCarry flag, MSR[29]
Sa Special Purpose Register, source operand
Sd Special Purpose Register, destination operand
s(x)Sign extend argument xto 32-bit value
*Addr Memory contents at location Addr (data-size aligned)
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Chapter 2: MicroBlaze Architecture
:= Assignment operator
=Equality comparison
!= Inequality comparison
>Greater than comparison
>= Greater than or equal comparison
<Less than comparison
<= Less than or equal comparison
+Arithmetic add
*Arithmetic multiply
/Arithmetic divide
>> xBit shift right xbits
<< xBit shift left xbits
and Logic AND
or Logic OR
xor Logic exclusive OR
op1 if cond else op2 Perform op1 if condition cond is true, else perform op2
&Concatenate. E.g. “0000100 & Imm7” is the concatenation of the fixed field “0000100” and
a 7 bit immediate value.
signed Operation performed on signed integer data type. All arithmetic operations are performed
on signed word operands, unless otherwise specified
unsigned Operation performed on unsigned integer data type
float Operation performed on floating point data type
clz(r) Count leading zeros
Table 2-5: Instruction Set Nomenclature (Cont’d)
Symbol Description
Table 2-6: MicroBlaze Instruction Set Summary
Type A 0-5 6-10 11-15 16-20 21-31 Semantics
Type B 0-5 6-10 11-15 16-31
ADD Rd,Ra,Rb 000000 Rd Ra Rb 00000000000 Rd := Rb + Ra
RSUB Rd,Ra,Rb 000001 Rd Ra Rb 00000000000 Rd := Rb + Ra + 1
ADDC Rd,Ra,Rb 000010 Rd Ra Rb 00000000000 Rd := Rb + Ra + C
RSUBC Rd,Ra,Rb 000011 Rd Ra Rb 00000000000 Rd := Rb + Ra + C
ADDK Rd,Ra,Rb 000100 Rd Ra Rb 00000000000 Rd := Rb + Ra
RSUBK Rd,Ra,Rb 000101 Rd Ra Rb 00000000000 Rd := Rb + Ra + 1
CMP Rd,Ra,Rb 000101 Rd Ra Rb 00000000001 Rd := Rb + Ra + 1
Rd[0] := 0 if (Rb >= Ra) else
Rd[0] := 1
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Chapter 2: MicroBlaze Architecture
CMPU Rd,Ra,Rb 000101 Rd Ra Rb 00000000011 Rd := Rb + Ra + 1 (unsigned)
Rd[0] := 0 if (Rb >= Ra, unsigned) else
Rd[0] := 1
ADDKC Rd,Ra,Rb 000110 Rd Ra Rb 00000000000 Rd := Rb + Ra + C
RSUBKC Rd,Ra,Rb 000111 Rd Ra Rb 00000000000 Rd := Rb + Ra + C
ADDI Rd,Ra,Imm 001000 Rd Ra Imm Rd := s(Imm) + Ra
RSUBI Rd,Ra,Imm 001001 Rd Ra Imm Rd := s(Imm) + Ra + 1
ADDIC Rd,Ra,Imm 001010 Rd Ra Imm Rd := s(Imm) + Ra + C
RSUBIC Rd,Ra,Imm 001011 Rd Ra Imm Rd := s(Imm) + Ra + C
ADDIK Rd,Ra,Imm 001100 Rd Ra Imm Rd := s(Imm) + Ra
RSUBIK Rd,Ra,Imm 001101 Rd Ra Imm Rd := s(Imm) + Ra + 1
ADDIKC Rd,Ra,Imm 001110 Rd Ra Imm Rd := s(Imm) + Ra + C
RSUBIKC Rd,Ra,Imm 001111 Rd Ra Imm Rd := s(Imm) + Ra + C
MUL Rd,Ra,Rb 010000 Rd Ra Rb 00000000000 Rd := Ra * Rb
MULH Rd,Ra,Rb 010000 Rd Ra Rb 00000000001 Rd := (Ra * Rb) >> 32 (signed)
MULHU Rd,Ra,Rb 010000 Rd Ra Rb 00000000011 Rd := (Ra * Rb) >> 32 (unsigned)
MULHSU Rd,Ra,Rb 010000 Rd Ra Rb 00000000010 Rd := (Ra, signed * Rb, unsigned) >> 32
(signed)
BSRL Rd,Ra,Rb 010001 Rd Ra Rb 00000000000 Rd := 0 & (Ra >> Rb)
BSRA Rd,Ra,Rb 010001 Rd Ra Rb 01000000000 Rd := s(Ra >> Rb)
BSLL Rd,Ra,Rb 010001 Rd Ra Rb 10000000000 Rd := (Ra << Rb) & 0
IDIV Rd,Ra,Rb 010010 Rd Ra Rb 00000000000 Rd := Rb/Ra
IDIVU Rd,Ra,Rb 010010 Rd Ra Rb 00000000010 Rd := Rb/Ra, unsigned
TNE AGETD Rd,Rb 010011 Rd 00000 Rb 0N0TAE
00000
Rd := FSL Rb[28:31] (data read)
MSR[FSL] := 1 if (FSL_S_Control = 1)
MSR[C] := not FSL_S_Exists if N= 1
TNA PUTD Ra,Rb 010011 00000 Ra Rb 0N0TA0
00000
FSL Rb[28:31] := Ra (data write)
MSR[C] := FSL_M_Full if N= 1
TNE CAGETD Rd,Rb 010011 Rd 00000 Rb 0N1TAE
00000
Rd := FSL Rb[28:31] (control read)
MSR[FSL] := 1 if (FSL_S_Control = 0)
MSR[C] := not FSL_S_Exists if N= 1
TNCAPUTD Ra,Rb 010011 00000 Ra Rb 0N1TA0
00000
FSL Rb[28:31] := Ra (control write)
MSR[C] := FSL_M_Full if N= 1
FADD Rd,Ra,Rb 010110 Rd Ra Rb 00000000000 Rd := Rb+Ra, float1
FRSUB Rd,Ra,Rb 010110 Rd Ra Rb 00010000000 Rd := Rb-Ra, float1
FMUL Rd,Ra,Rb 010110 Rd Ra Rb 00100000000 Rd := Rb*Ra, float1
FDIV Rd,Ra,Rb 010110 Rd Ra Rb 00110000000 Rd := Rb/Ra, float1
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31 Semantics
Type B 0-5 6-10 11-15 16-31
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FCMP.UN Rd,Ra,Rb 010110 Rd Ra Rb 01000000000 Rd := 1 if (Rb = NaN or Ra = NaN, float1)
else
Rd := 0
FCMP.LT Rd,Ra,Rb 010110 Rd Ra Rb 01000010000 Rd := 1 if (Rb < Ra, float1) else
Rd := 0
FCMP.EQ Rd,Ra,Rb 010110 Rd Ra Rb 01000100000 Rd := 1 if (Rb = Ra, float1) else
Rd := 0
FCMP.LE Rd,Ra,Rb 010110 Rd Ra Rb 01000110000 Rd := 1 if (Rb <= Ra, float1) else
Rd := 0
FCMP.GT Rd,Ra,Rb 010110 Rd Ra Rb 01001000000 Rd := 1 if (Rb > Ra, float1) else
Rd := 0
FCMP.NE Rd,Ra,Rb 010110 Rd Ra Rb 01001010000 Rd := 1 if (Rb != Ra, float1) else
Rd := 0
FCMP.GE Rd,Ra,Rb 010110 Rd Ra Rb 01001100000 Rd := 1 if (Rb >= Ra, float1) else
Rd := 0
FLT Rd,Ra 010110 Rd Ra 0 01010000000 Rd := float (Ra)1
FINT Rd,Ra 010110 Rd Ra 0 01100000000 Rd := int (Ra)1
FSQRT Rd,Ra 010110 Rd Ra 0 01110000000 Rd := sqrt (Ra)1
MULI Rd,Ra,Imm 011000 Rd Ra Imm Rd := Ra * s(Imm)
BSRLI Rd,Ra,Imm 011001 Rd Ra 00000000000 & Imm5 Rd : = 0 & (Ra >> Imm5)
BSRAI Rd,Ra,Imm 011001 Rd Ra 00000010000 & Imm5 Rd := s(Ra >> Imm5)
BSLLI Rd,Ra,Imm 011001 Rd Ra 00000100000 & Imm5 Rd := (Ra << Imm5) & 0
TNE AGET Rd,FSLx 011011 Rd 00000 0N0TAE000000 & FSLx Rd := FSLx (data read, blocking if N= 0)
MSR[FSL] := 1 if (FSLx_S_Control = 1)
MSR[C] := not FSLx_S_Exists if N= 1
TNA PUT Ra,FSLx 011011 00000 Ra 1N0TA0000000 & FSLx FSLx := Ra (data write, blocking if N= 0)
MSR[C] := FSLx_M_Full if N= 1
TNE CAGET Rd,FSLx 011011 Rd 00000 0N1TAE000000 & FSLx Rd := FSLx (control read, blocking if N=
0)
MSR[FSL] := 1 if (FSLx_S_Control = 0)
MSR[C] := not FSLx_S_Exists if N= 1
TNCAPUT Ra,FSLx 011011 00000 Ra 1N1TA0000000 & FSLx FSLx := Ra (control write, blocking if N
= 0)
MSR[C] := FSLx_M_Full if N= 1
OR Rd,Ra,Rb 100000 Rd Ra Rb 00000000000 Rd := Ra or Rb
PCMPBF Rd,Ra,Rb 100000 Rd Ra Rb 10000000000 Rd := 1 if (Rb[0:7] = Ra[0:7]) else
Rd := 2 if (Rb[8:15] = Ra[8:15]) else
Rd := 3 if (Rb[16:23] = Ra[16:23]) else
Rd := 4 if (Rb[24:31] = Ra[24:31]) else
Rd := 0
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31 Semantics
Type B 0-5 6-10 11-15 16-31
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AND Rd,Ra,Rb 100001 Rd Ra Rb 00000000000 Rd := Ra and Rb
XOR Rd,Ra,Rb 100010 Rd Ra Rb 00000000000 Rd := Ra xor Rb
PCMPEQ Rd,Ra,Rb 100010 Rd Ra Rb 10000000000 Rd := 1 if (Rb = Ra) else
Rd := 0
ANDN Rd,Ra,Rb 100011 Rd Ra Rb 00000000000 Rd := Ra and Rb
PCMPNE Rd,Ra,Rb 100011 Rd Ra Rb 10000000000 Rd := 1 if (Rb != Ra) else
Rd := 0
SRA Rd,Ra 100100 Rd Ra 0000000000000001 Rd := s(Ra >> 1)
C := Ra[31]
SRC Rd,Ra 100100 Rd Ra 0000000000100001 Rd := C & (Ra >> 1)
C := Ra[31]
SRL Rd,Ra 100100 Rd Ra 0000000001000001 Rd := 0 & (Ra >> 1)
C := Ra[31]
SEXT8 Rd,Ra 100100 Rd Ra 0000000001100000 Rd := s(Ra[24:31])
SEXT16 Rd,Ra 100100 Rd Ra 0000000001100001 Rd := s(Ra[16:31])
CLZ Rd, Ra 100100 Rd Ra 0000000011100000 Rd = clz(Ra)
SWAPB Rd, Ra 100100 Rd Ra 0000000111100000 Rd = (Ra)[24:31, 16:23, 8:15, 0:7]
SWAPH Rd, Ra 100100 Rd Ra 0000000111100010 Rd = (Ra)[16:31, 0:15]
WIC Ra,Rb 100100 00000 Ra Rb 00001101000 ICache_Line[Ra >> 4].Tag := 0 if
(C_ICACHE_LINE_LEN = 4)
ICache_Line[Ra >> 5].Tag := 0 if
(C_ICACHE_LINE_LEN = 8)
ICache_Line[Ra >> 6].Tag := 0 if
(C_ICACHE_LINE_LEN = 16)
WDC Ra,Rb 100100 00000 Ra Rb 00001100100 Cache line is cleared, discarding stored
data.
DCache_Line[Ra >> 4].Tag := 0 if
(C_DCACHE_LINE_LEN = 4)
DCache_Line[Ra >> 5].Tag := 0 if
(C_DCACHE_LINE_LEN = 8)
DCache_Line[Ra >> 6].Tag := 0 if
(C_DCACHE_LINE_LEN = 16)
WDC.FLUSH Ra,Rb 100100 00000 Ra Rb 00001110100 Cache line is flushed, writing stored
data to memory, and then cleared. Used
when C_DCACHE_USE_WRITEBACK = 1.
WDC.CLEAR Ra,Rb 100100 00000 Ra Rb 00001100110 Cache line with matching address is
cleared, discarding stored data. Used
when C_DCACHE_USE_WRITEBACK = 1.
WDC.CLEAR.EA Ra,Rb 100100 00000 Ra Rb 00011100110 Cache line with matching extended
address Ra & Rb is cleared. Used when
C_DCACHE_USE_WRITEBACK = 1.
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31 Semantics
Type B 0-5 6-10 11-15 16-31
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MTS Sd,Ra 100101 00000 Ra 11 & Sd SPR[Sd] := Ra, where:
· SPR[0x0001] is MSR
· SPR[0x0007] is FSR
· SPR[0x0800] is SLR
· SPR[0x0802] is SHR
· SPR[0x1000] is PID
· SPR[0x1001] is ZPR
· SPR[0x1002] is TLBX
· SPR[0x1003] is TLBLO
· SPR[0x1004] is TLBHI
· SPR[0x1005] is TLBSX
MFS Rd,Sa 100101 Rd 00000 10 & Sa Rd := SPR[Sa], where:
· SPR[0x0000] is PC
· SPR[0x0001] is MSR
· SPR[0x0003] is EAR[31:0]
· SPR[0x0005] is ESR
· SPR[0x0007] is FSR
· SPR[0x000B] is BTR
· SPR[0x000D] is EDR
· SPR[0x0800] is SLR
· SPR[0x0802] is SHR
· SPR[0x1000] is PID
· SPR[0x1001] is ZPR
· SPR[0x1002] is TLBX
· SPR[0x1003] is TLBLO
· SPR[0x1004] is TLBHI
· SPR[0x2000 to 200B] is PVR[0 to 12]
MFSE Rd,Sa 100101 Rd 01000 10 & Sa Rd := SPR[Sa][63:32], where:
· SPR[0x0003] is EAR[63:32]
· SPR[0x2008] is PVR[8][63:32]
· SPR[0x2009] is PVR[9][63:32]
MSRCLR Rd,Imm 100101 Rd 00001 00 & Imm14 Rd := MSR
MSR := MSR and Imm14
MSRSET Rd,Imm 100101 Rd 00000 00 & Imm14 Rd := MSR
MSR := MSR or Imm14
BR Rb 100110 00000 00000 Rb 00000000000 PC := PC + Rb
BRD Rb 100110 00000 10000 Rb 00000000000 PC := PC + Rb
BRLD Rd,Rb 100110 Rd 10100 Rb 00000000000 PC := PC + Rb
Rd := PC
BRA Rb 100110 00000 01000 Rb 00000000000 PC := Rb
BRAD Rb 100110 00000 11000 Rb 00000000000 PC := Rb
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31 Semantics
Type B 0-5 6-10 11-15 16-31
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BRALD Rd,Rb 100110 Rd 11100 Rb 00000000000 PC := Rb
Rd := PC
BRK Rd,Rb 100110 Rd 01100 Rb 00000000000 PC := Rb
Rd := PC
MSR[BIP] := 1
BEQ Ra,Rb 100111 00000 Ra Rb 00000000000 PC := PC + Rb if Ra = 0
BNE Ra,Rb 100111 00001 Ra Rb 00000000000 PC := PC + Rb if Ra != 0
BLT Ra,Rb 100111 00010 Ra Rb 00000000000 PC := PC + Rb if Ra < 0
BLE Ra,Rb 100111 00011 Ra Rb 00000000000 PC := PC + Rb if Ra <= 0
BGT Ra,Rb 100111 00100 Ra Rb 00000000000 PC := PC + Rb if Ra > 0
BGE Ra,Rb 100111 00101 Ra Rb 00000000000 PC := PC + Rb if Ra >= 0
BEQD Ra,Rb 100111 10000 Ra Rb 00000000000 PC := PC + Rb if Ra = 0
BNED Ra,Rb 100111 10001 Ra Rb 00000000000 PC := PC + Rb if Ra != 0
BLTD Ra,Rb 100111 10010 Ra Rb 00000000000 PC := PC + Rb if Ra < 0
BLED Ra,Rb 100111 10011 Ra Rb 00000000000 PC := PC + Rb if Ra <= 0
BGTD Ra,Rb 100111 10100 Ra Rb 00000000000 PC := PC + Rb if Ra > 0
BGED Ra,Rb 100111 10101 Ra Rb 00000000000 PC := PC + Rb if Ra >= 0
ORI Rd,Ra,Imm 101000 Rd Ra Imm Rd := Ra or s(Imm)
ANDI Rd,Ra,Imm 101001 Rd Ra Imm Rd := Ra and s(Imm)
XORI Rd,Ra,Imm 101010 Rd Ra Imm Rd := Ra xor s(Imm)
ANDNI Rd,Ra,Imm 101011 Rd Ra Imm Rd := Ra and s(Imm)
IMM Imm 101100 00000 00000 Imm Imm[0:15] := Imm
RTSD Ra,Imm 101101 10000 Ra Imm PC := Ra + s(Imm)
RTID Ra,Imm 101101 10001 Ra Imm PC := Ra + s(Imm)
MSR[IE] := 1
RTBD Ra,Imm 101101 10010 Ra Imm PC := Ra + s(Imm)
MSR[BIP] := 0
RTED Ra,Imm 101101 10100 Ra Imm PC := Ra + s(Imm)
MSR[EE] := 1, MSR[EIP] := 0
ESR := 0
BRI Imm 101110 00000 00000 Imm PC := PC + s(Imm)
MBAR Imm 101110 Imm 00010 0000000000000100 PC := PC + 4; Wait for memory accesses.
BRID Imm 101110 00000 10000 Imm PC := PC + s(Imm)
BRLID Rd,Imm 101110 Rd 10100 Imm PC := PC + s(Imm)
Rd := PC
BRAI Imm 101110 00000 01000 Imm PC := s(Imm)
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31 Semantics
Type B 0-5 6-10 11-15 16-31
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BRAID Imm 101110 00000 11000 Imm PC := s(Imm)
BRALID Rd,Imm 101110 Rd 11100 Imm PC := s(Imm)
Rd := PC
BRKI Rd,Imm 101110 Rd 01100 Imm PC := s(Imm)
Rd := PC
MSR[BIP] := 1
BEQI Ra,Imm 101111 00000 Ra Imm PC := PC + s(Imm) if Ra = 0
BNEI Ra,Imm 101111 00001 Ra Imm PC := PC + s(Imm) if Ra != 0
BLTI Ra,Imm 101111 00010 Ra Imm PC := PC + s(Imm) if Ra < 0
BLEI Ra,Imm 101111 00011 Ra Imm PC := PC + s(Imm) if Ra <= 0
BGTI Ra,Imm 101111 00100 Ra Imm PC := PC + s(Imm) if Ra > 0
BGEI Ra,Imm 101111 00101 Ra Imm PC := PC + s(Imm) if Ra >= 0
BEQID Ra,Imm 101111 10000 Ra Imm PC := PC + s(Imm) if Ra = 0
BNEID Ra,Imm 101111 10001 Ra Imm PC := PC + s(Imm) if Ra != 0
BLTID Ra,Imm 101111 10010 Ra Imm PC := PC + s(Imm) if Ra < 0
BLEID Ra,Imm 101111 10011 Ra Imm PC := PC + s(Imm) if Ra <= 0
BGTID Ra,Imm 101111 10100 Ra Imm PC := PC + s(Imm) if Ra > 0
BGEID Ra,Imm 101111 10101 Ra Imm PC := PC + s(Imm) if Ra >= 0
LBU Rd,Ra,Rb
LBUR Rd,Ra,Rb
110000 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
Rd[0:23] := 0
Rd[24:31] := *Addr[0:7]
LBUEA Rd,Ra,Rb 110000 Rd Ra Rb 00010000000 Addr := Ra & Rb
Rd[0:23] := 0
Rd[24:31] := *Addr[0:7]
LHU Rd,Ra,Rb
LHUR Rd,Ra,Rb
110001 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
Rd[0:15] := 0
Rd[16:31] := *Addr[0:15]
LHUEA Rd,Ra,Rb 110001 Rd Ra Rb 00010000000 Addr := Ra & Rb
Rd[0:15] := 0
Rd[16:31] := *Addr[0:15]
LW Rd,Ra,Rb
LWR Rd,Ra,Rb
110010 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
Rd := *Addr
LWX Rd,Ra,Rb 110010 Rd Ra Rb 10000000000 Addr := Ra + Rb
Rd := *Addr
Reservation := 1
LWEA Rd,Ra,Rb 110010 Rd Ra Rb 00010000000 Addr := Ra & Rb
Rd := *Addr
SB Rd,Ra,Rb
SBR Rd,Ra,Rb
110100 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
*Addr[0:8] := Rd[24:31]
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31 Semantics
Type B 0-5 6-10 11-15 16-31
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Semaphore Synchronization
The LWX and SWX. instructions are used to implement common semaphore operations,
including test and set, compare and swap, exchange memory, and fetch and add. They are
also used to implement spinlocks.
These instructions are typically used by system programs and are called by application
programs as needed. Generally, a program uses LWX to load a semaphore from memory,
causing the reservation to be set (the processor maintains the reservation internally). The
program can compute a result based on the semaphore value and conditionally store the
result back to the same memory location using the SWX instruction. The conditional store
SBEA Rd,Ra,Rb 110100 Rd Ra Rb 00010000000 Addr := Ra & Rb
*Addr[0:8] := Rd[24:31]
SH Rd,Ra,Rb
SHR Rd,Ra,Rb
110101 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
*Addr[0:16] := Rd[16:31]
SHEA Rd,Ra,Rb 110101 Rd Ra Rb 00010000000 Addr := Ra & Rb
*Addr[0:16] := Rd[16:31]
SW Rd,Ra,Rb
SWR Rd,Ra,Rb
110110 Rd Ra Rb 00000000000
01000000000
Addr := Ra + Rb
*Addr := Rd
SWX Rd,Ra,Rb 110110 Rd Ra Rb 10000000000 Addr := Ra + Rb
*Addr := Rd if Reservation = 1
Reservation := 0
SWEA Rd,Ra,Rb 110110 Rd Ra Rb 00010000000 Addr := Ra & Rb
*Addr := Rd
LBUI Rd,Ra,Imm 111000 Rd Ra Imm Addr := Ra + s(Imm)
Rd[0:23] := 0
Rd[24:31] := *Addr[0:7]
LHUI Rd,Ra,Imm 111001 Rd Ra Imm Addr := Ra + s(Imm)
Rd[0:15] := 0
Rd[16:31] := *Addr[0:15]
LWI Rd,Ra,Imm 111010 Rd Ra Imm Addr := Ra + s(Imm)
Rd := *Addr
SBI Rd,Ra,Imm 111100 Rd Ra Imm Addr := Ra + s(Imm)
*Addr[0:7] := Rd[24:31]
SHI Rd,Ra,Imm 111101 Rd Ra Imm Addr := Ra + s(Imm)
*Addr[0:15] := Rd[16:31]
SWI Rd,Ra,Imm 111110 Rd Ra Imm Addr := Ra + s(Imm)
*Addr := Rd
1. Due to the many different corner cases involved in floating point arithmetic, only the normal behavior is described. A full
description of the behavior can be found in Chapter 5, “MicroBlaze Instruction Set Architecture.”
Table 2-6: MicroBlaze Instruction Set Summary (Cont’d)
Type A 0-5 6-10 11-15 16-20 21-31 Semantics
Type B 0-5 6-10 11-15 16-31
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is performed based on the existence of the reservation established by the preceding LWX
instruction. If the reservation exists when the store is executed, the store is performed and
MSR[C] is cleared to 0. If the reservation does not exist when the store is executed, the
target memory location is not modified and MSR[C] is set to 1.
If the store is successful, the sequence of instructions from the semaphore load to the
semaphore store appear to be executed atomically—no other device modified the
semaphore location between the read and the update. Other devices can read from the
semaphore location during the operation. For a semaphore operation to work properly, the
LWX instruction must be paired with an SWX instruction, and both must specify identical
addresses. The reservation granularity in MicroBlaze is a word. For both instructions, the
address must be word aligned. No unaligned exceptions are generated for these
instructions.
The conditional store is always attempted when a reservation exists, even if the store
address does not match the load address that set the reservation.
Only one reservation can be maintained at a time. The address associated with the
reservation can be changed by executing a subsequent LWX instruction. The conditional
store is performed based upon the reservation established by the last LWX instruction
executed. Executing an SWX instruction always clears a reservation held by the processor,
whether the address matches that established by the LWX or not.
Reset, interrupts, exceptions, and breaks (including the BRK and BRKI instructions) all clear
the reservation.
The following provides general guidelines for using the LWX and SWX instructions:
• The LWX and SWX instructions should be paired and use the same address.
• An unpaired SWX instruction to an arbitrary address can be used to clear any
reservation held by the processor.
• A conditional sequence begins with an LWX instruction. It can be followed by memory
accesses and/or computations on the loaded value. The sequence ends with an SWX
instruction. In most cases, failure of the SWX instruction should cause a branch back to
the LWX for a repeated attempt.
• An LWX instruction can be left unpaired when executing certain synchronization
primitives if the value loaded by the LWX is not zero. An implementation of Test and Set
exemplifies this:
loop: lwx r5,r3,r0 ; load and reserve
bnei r5,next ; branch if not equal to zero
addik r5,r5,1 ; increment value
swx r5,r3,r0 ; try to store non-zero value
addic r5,r0,0 ; check reservation
bnei r5,loop ; loop if reservation lost
next:
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