XMOS XK-XMP-64 User manual

XK-XMP-64 Hardware Manual
(VERSION 1.0)
2010/02/22
Authors:
XMOS LTD.
Copyright © 2010, XMOS Ltd.
All Rights Reserved

XMOS 1/9
1 Introduction
The XK-XMP-64 is 64 core multiprocessor based on the XMOS XS1-G4 event-
driven processor. It comprises 16 XS1-G4, 16 LEDs, JTAG interface (over USB),
two Ethernet interfaces, and two IDC expansion slots. These are outlined in
Figure 1. They comprise:
AXS1-G4 Device (×16)
BGreen User LED (×16)
CPLL Lock LED (×16)
DUSB-2.0 programming interface
EEthernet connector (×2)
FReset Button
GPower Switch
HPower connector (12V, centre positive)
IExtension IDC connector (×2)
The numbers in the diagram are the node numbers for each core, and the nodes
to which the IO devices (Ethernet, IDC connector) are connected. Each XS1-G4
node contains four cores. The Ethernet connectors are connected to nodes 1
and 3, and that the IDC connectors are connected to nodes 0 and 2.
The following sections in this document provide a detailed description of these
components.
2 XS1-G4 [A]
Each XS1-G4 device contains four multithreaded XCore™ processing compo-
nents with tightly integrated support for communication, I/O and timing. The
links of the XS1-G4s are connected to form a hypercube. In addition, some I/Os
are available for Ethernet, lighting a LED or general purpose I/O.
The cores within node nodeNumber are numbered as follows:
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22
6
14
10
3
7
15
11
1
5
13
9
0
4
12
8
B C
A
B C
A
E E
F
G
H
D
II
3 1
10 0
XMOS
Figure 1 Placement of components
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• 4 ×nodeNumber + 0
• 4 ×nodeNumber + 1
• 4 ×nodeNumber + 2
• 4 ×nodeNumber + 3
The nodes are connected in a hypercube network: there are four 400-Mbit links
between node xand node yif and only if there is an integer k≥0 such that
x⊕y= 2k
3 User-configurable LEDs [B]
These leds are green and can be lit by driving a “1” to port 1E on cores 4 ×k:
Core 0, Core 4, Core 8, ..., Core 56, and Core 60.
4 PLL Lock LEDs [C]
These leds are blue and should all be on during normal operation. The LED
indicates that the core is clocked and not in RESET.
5 USB Connector [D]
The USB connector is used to load and debug code on all of the XS1-G4’s
processors. The USB connector provides JTAG control, system reset, and pro-
cessor debug. The XK-XMP-64 has an embedded XTAG2 (the XMOS USB to
JTAG key) with a serial number starting with “XMP”.
6 Ethernet PHYs [E]
The left ethernet PHY is connected to Core 4 (Node 1, Core 0), the right ethernet
PHY is connected to Core 12 (Node 3, Core 0).
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7 Reset Button [F]
The XK-XMP-64 is reset on power up. If a reset is required this button can be
pressed. When downloading code over USB the board is automatically reset.
8 Power Switch [G]
The power switch can be used to switch the power on or off.
9 Power Switch [H]
The board should be powered with a 12V 5A power supply (provided). The core
should be positive. Internally, 1V (core), 1V8 (USB), 3V3 (I/O, links), and 5V
(fans) are generated.
10 I/O Expansion Connectors [I]
Two connectors provide spare I/O to add additional hardware, for example an
Audio codec. The left connector is connected to Cores 40 and 41 (Cores 2 and
3 on Node 10), the right connector is connected to Cores 2 and 3 (Cores 2 and
3 on Node 0)
11 XK-XMP-64 XN File
The XCore ports linked to the hardware features on the XK-XMP-64 are mapped
to generic port identifiers as part of a platform specific XN file, which simplifies
the process of porting a project between platforms.
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11.1 I/O Port-to-Pin Mapping
The tables on the following pages provides a full description of the port-to-pin
mappings. For each core it lists which I/Os are available.
Pin Port Core number
1b 4b 8b 16b 0 2 3 4 8
XnD12 P1E0 PORT LED 0 PORT LED 1 PORT LED 2
XnD24 P1I0 I031 I03
XnD25 P1J0 I032 I04
XnD26 P4E0 P8C0 P16B0 I033 I05 PORT ETH RXD0 1
XnD27 P4E1 P8C1 P16B1 I034 I06 PORT ETH RXD1 1
XnD28 P4F0 P8C2 P16B2 I035 I07 PORT ETH TXD0 1
XnD29 P4F1 P8C3 P16B3 I036 I08 PORT ETH TXD1 1
XnD30 P4F2 P8C4 P16B4 I037 I09 PORT ETH TXD2 1
XnD31 P4F3 P8C5 P16B5 I038 I010 PORT ETH TXD3 1
XnD32 P4E2 P8C6 P16B6 I039 I011 PORT ETH RXD2 1
XnD33 P4E3 P8C7 P16B7 I040 I012 PORT ETH RXD3 1
XnD34 P1K0 I041 I013 PORT ETH TX CLK 1
XnD35 P1L0 I042 I014 PORT ETH TX EN 1
XnD36 P1M0 P8D0 P16B8 I045 I017 PORT ETH RX CLK 1
XnD37 P1N0 P8D1 P16B9 I046 I018 PORT ETH RX DV 1
XnD38 P1O0 P8D2 P16B10 I047 I019 PORT ETH RX ER 1
XnD39 P1P0 P8D3 P16B11 I048 I020 PORT ETH RX MDC 1
XnD40 P8D4 P16B12 I049 I021
XnD41 P8D5 P16B13 I050 I022
XnD42 P8D6 P16B14 I051 I023 PORT ETH NRST 1
XnD43 P8D7 P16B15 I052 I024 PORT ETH MDIO 1
XnD49 P32A0 I053 I025
XnD50 P32A1 I054 I026
XnD51 P32A2 I055 I027
XnD52 P32A3 I056 I028
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Pin Port Core number
1b 4b 8b 16b 12 16 20 24
XnD12 P1E0 PORT LED 3 PORT LED 4 PORT LED 5 PORT LED 6
XnD26 P4E0 P8C0 P16B0 PORT ETH RXD0 3
XnD27 P4E1 P8C1 P16B1 PORT ETH RXD1 3
XnD28 P4F0 P8C2 P16B2 PORT ETH TXD0 3
XnD29 P4F1 P8C3 P16B3 PORT ETH TXD1 3
XnD30 P4F2 P8C4 P16B4 PORT ETH TXD2 3
XnD31 P4F3 P8C5 P16B5 PORT ETH TXD3 3
XnD32 P4E2 P8C6 P16B6 PORT ETH RXD2 3
XnD33 P4E3 P8C7 P16B7 PORT ETH RXD3 3
XnD34 P1K0 PORT ETH TX CLK 3
XnD35 P1L0 PORT ETH TX EN 3
XnD36 P1M0 P8D0 P16B8 PORT ETH RX CLK 3
XnD37 P1N0 P8D1 P16B9 PORT ETH RX DV 3
XnD38 P1O0 P8D2 P16B10 PORT ETH RX ER 3
XnD39 P1P0 P8D3 P16B11 PORT ETH RX MDC 3
XnD42 P8D6 P16B14 PORT ETH NRST 3
XnD43 P8D7 P16B15 PORT ETH MDIO 3
Pin Port Core number
1b 4b 8b 16b 28 32 36 40 41
XnD12 P1E0 PORT LED 7 PORT LED 8 PORT LED 9 PORT LED 10
XnD24 P1I0 I1031 I10 3
XnD25 P1J0 I1032 I10 4
XnD26 P4E0 P8C0 P16B0 I1033 I10 5
XnD27 P4E1 P8C1 P16B1 I1034 I10 6
XnD28 P4F0 P8C2 P16B2 I1035 I10 7
XnD29 P4F1 P8C3 P16B3 I1036 I10 8
XnD30 P4F2 P8C4 P16B4 I1037 I10 9
XnD31 P4F3 P8C5 P16B5 I1038 I10 10
XnD32 P4E2 P8C6 P16B6 I1039 I10 11
XnD33 P4E3 P8C7 P16B7 I1040 I10 12
XnD34 P1K0 I1041 I10 13
XnD35 P1L0 I1042 I10 14
XnD36 P1M0 P8D0 P16B8 I1045 I10 17
XnD37 P1N0 P8D1 P16B9 I1046 I10 18
XnD38 P1O0 P8D2 P16B10 I1047 I10 19
XnD39 P1P0 P8D3 P16B11 I1048 I10 20
XnD40 P8D4 P16B12 I1049 I10 21
XnD41 P8D5 P16B13 I1050 I10 22
XnD42 P8D6 P16B14 I1051 I10 23
XnD43 P8D7 P16B15 I1052 I10 24
XnD49 P32A0 I1053 I10 25
XnD50 P32A1 I1054 I10 26
XnD51 P32A2 I1055 I10 27
XnD52 P32A3 I1056 I10 28
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Pin Port Core number
1b 4b 8b 16b 44 48 52 56 60
XnD12 P1E0 PORT LED 11 PORT LED 12 PORT LED 13 PORT LED 14 PORT LED 15
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12 Related Documents
The following documents provide more information on designing with the XK-
XMP-64:
•XK-XMP-64 Tutorial: provides an introduction to programming software on
the XK-XMP-64 using the XC language.
•The XMOS XS1 Architecture: provides an overview of the XS1 instruction
set architecture.
•XK-XMP-64 Performance Measurements: documents a number of perfor-
mance measurements.
The most up-to-date information on the XK-XMP-64, including board schematics
and product datasheets, is available from:
•http://www.xmos.com/xmp64
13 Document History
Date Release Comment
2010/02/22 1.0 First release.
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XMOS 9/9
XMOS Ltd is the owner or licensee of this design, code, or Information (collec-
tively, the “Information”) and is providing it to you “AS IS” with no warranty of any
kind, express or implied and shall have no liability in relation to its use. XMOS
Ltd makes no representation that the Information, or any particular implementa-
tion thereof, is or will be free from any claims of infringement and again, shall
have no liability in relation to any such claims.
(c) 2010 XMOS Limited - All Rights Reserved
XK-XMP-64 HARDWARE MANUAL (1.0) 2010/02/22