Acromag IOS-571 User manual

IOS-571, IOS-572
MIL-STD-1553A/B Bus Interface Module
USER’S MANUAL
ACROMAG INCORPORATED Tel: [phone]
30765 South Wixom Road Fax: [phone]
P.O. BOX 437
Wixom, MI 48393-7037 U.S.A.
[email protected]
Copyright 2010-2011, Acromag, Inc., Printed in the USA. 8500-909-B11C007
retired

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Table of Contents
RELATED PUBLICATIONS....................................................................................................3
GENERAL INFORMATION....................................................................................................3
MODELS.................................................................................................................................4
Notes (Table 1): ..................................................................................................................4
KEY FEATURES.................................................................................................................4
I/O SERVER MODULE INTERFACE FEATURES.............................................................4
I/O SERVER WINDOWS SOFTWARE...............................................................................5
I/O SERVER Linux SOFTWARE.....................................................................................5
PREPARATION FOR USE.....................................................................................................6
UNPACKING AND INSPECTION.......................................................................................6
INSTALLATION...................................................................................................................6
CONNECTORS...................................................................................................................6
Field I/O Connector (P2) .................................................................................................6
CABLE ................................................................................................................................7
Non-Isolation Considerations..............................................................................................8
PROGRAMMING INFORMATION .........................................................................................8
IDENTIFICATION PROM....................................................................................................8
ADDRESS MAP..................................................................................................................9
I/O SPACE ADDRESS MAP...............................................................................................9
MEMORY SPACE ADDRESS MAP .................................................................................11
Micro ACE access.............................................................................................................11
PROGRAMMING INTERRUPTS......................................................................................13
THEORY OF OPERATION ..................................................................................................13
LOGIC/POWER INTERFACE...........................................................................................13
IOS INTERFACE LOGIC ..................................................................................................13
IOS-57xCONTROL LOGIC...............................................................................................14
TAG CLOCK Input / Output ..............................................................................................14
STATIC MICRO ACE INPUTS..........................................................................................15
REMOTE TERMINAL ADDRESS.....................................................................................15
BUS CONNECTION .........................................................................................................15
DIRECT COUPLING METHOD.....................................................................................15
TRANSFORMER COUPLING METHOD......................................................................15
SERVICE AND REPAIR.......................................................................................................15
PRELIMINARY SERVICE PROCEDURE.........................................................................16
WHERE TO GET HELP....................................................................................................16
SPECIFICATIONS................................................................................................................16
PHYSICAL ........................................................................................................................16
Connectors........................................................................................................................16

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The information contained in this manual is subject to change without notice. Acromag,
Inc. makes no warranty of any kind with regard to this material, including, but not limited to,
the implied warranties of merchantability and fitness for a particular purpose. Further,
Acromag, Inc. assumes no responsibility for any errors that may appear in this manual and
makes no commitment to update, or keep current, the information contained in this manual.
No part of this manual may be copied or reproduced in any form, without the prior written
consent of Acromag, Inc.
IMPORTANT SAFETY CONSIDERATIONS
It is very important for the user to consider the possible adverse effects of power, wiring,
component, sensor, or software failures in designing any type of control or monitoring
system. This is especially important where economic property loss or human life is
involved. It is important that the user employ satisfactory overall system design. It is
agreed between the Buyer and Acromag, that this is the Buyer's responsibility.
RELATED PUBLICATIONS
The following manuals and part specifications provide the necessary information for in
depth understanding of the IOS-57x Series boards. These documents are available on the
Data Device Corporation web site http://www.ddc-web.com/.
BU-6174X/6184X/6186X ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE data sheet
Enhanced Miniature Advanced Communications Engine (Enhanced Mini-ACE®
Series) Users Guide MN-6186X-001
MIL-STD-1553 DESIGNER’S GUIDE Sixth Edition
GENERAL INFORMATION
The I/O Server (IOS) Series IOS-57x modules provide the interface between the IOS and
the MIL-STD-1553A/B bus. The IOS-57x series modules are built upon Data Device
Corporation’s Micro ACE MIL-STD-1553 terminal. The Micro ACE provides Bus Controller
(BC), Remote Terminal (RT), and Bus Monitor (BM) functions. The Micro ACE includes 64K
words of RAM for message queues. IOS-57x modules support both direct and transformer
coupled applications. A synchronization clock input and output is provided. The RT
address lines for each channel are available at the connector to allow setting the RT
address with the wire harness.
The IOS-57x Series consists of two models with one or two dual redundant 1553 channels.
Important Note: The following IOS models are accessories to the IOS Server Models:
IOS-7200, IOS-7200-WIN, IOS-7400, and IOS-7400-WIN; which are cULus Listed. This
equipment is suitable for use in Class I, Division 2, Groups A, B, C, and D or non-
hazardous locations only.

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MODELS
Table 1 IOS-57x Series Models
Model
Number of
Channels
Operating Temperature
Range1
IOS-571
1
-40 to 85 C
IOS-572
2
-40 to 85 C
Notes (Table 1):
1. The maximum operating temperature depends on the transmitter duty cycle, the
1553 bus coupling method, and the heat dissipated by other IOS modules installed
in the I/O Server. The systems engineer must ensure that the ball temperature of
the micro ACE devices does not exceed 85 C. Our testing has shown that the
maximum ball temperature is reached under the following conditions: Two IOS-572
modules installed in an I/O Server, transformer coupled to the 1553 bus, with each
of the channels transmitting at 25% duty cycle, I/O Server ambient 70 C still air.
Four IOS-572 modules may be installed in an I/O Server if all channels are
operating in monitor mode (transmitter duty cycle is 0%).
KEY FEATURES
One or two dual redundant MIL-STD-1553A/B channels
Each channel can be independently programmed for Bus Controller, Remote
Terminal, or Bus Monitor operation
Transformer (long stub) or Direct coupled (short stub) bus connection
64K words RAM per channel
External Time-Tag clock input and output
Software initiated RAM built in self test
RT address input for each channel
VITA 4 compliant
I/O SERVER MODULE INTERFACE FEATURES
Clock Speed –Supports an 8 or 32 MHz bus clock speed.
Local ID - Each IOS module has its own 8-bit ID information which is accessed via data
transfers in the "ID" space.
16-bit & 8-bit I/O –Control and status register Read/Write is performed through 16 bit or 8
bit data transfer cycles in the IOS module I/O space. The u-ACE controllers are located in
memory space and are accessed with 16-bit data transfer cycles.
High Speed - Access times for all data transfer cycles are described in terms of "wait"
states. Wait states are minimized for all read and write operations (see specifications for
detailed information).

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I/O SERVER WINDOWS SOFTWARE
Acromag provides a software product (sold separately) to facilitate the development of
Windows (2000/XP/Vista/7 ) applications. This software (Model IOSSW-API-WIN)
consists of low-level drivers and Windows 32 Dynamic Link Libraries (DLLs) that are
compatible with a number of programming environments including Visual C++™, Visual
Basic .NET® and others. The DLL functions provide a high-level interface to boards
eliminating the need to perform low-level reads/writes of registers, and the writing of
interrupt handlers.
I/O SERVER Linux SOFTWARE
Acromag provides a software product (sold separately) consisting of Linux software. This
software (Model IOSSW-API-LNX) is composed of Linux libraries designed to support
applications accessing I/O Server Modules installed on Acromag I/O Server systems. The
software is implemented as a library of “C” functions which link with existing user code
FPGA
CONTROL
STATUS
ADDRESS
CHANNEL 0
P2
DDC
µACE
1553
BC/RT/MT
P1
BUS
ID ROM
CONTROL
TAG CLOCK IN
INTERRUPT
VECTORS
CONTROL
LOGIC
RT ADDRESS
ADDRESS
& DATA
A
B
CHANNEL 1
DDC
µACE
1553
BC/RT/MT
RT ADDRESS
ADDRESS
& DATA
A
B
TAG CLOCK OUT
Figure 1 IOS-572 Block Diagram
DATA

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PREPARATION FOR USE
UNPACKING AND INSPECTION
Upon receipt of this product, inspect the shipping carton for evidence of mishandling
during transit. If the shipping carton is badly damaged or water stained, request that the
carrier's agent be present when the carton is opened. If the carrier's agent is absent
when the carton is opened and the contents of the carton are damaged, keep the carton
and packing material for the agent's inspection.
For repairs to a product damaged in shipment, refer to the Acromag Service Policy to
obtain return instructions. It is suggested that salvageable shipping cartons and packing
material be saved for future use in the event the product must be shipped.
This board is physically protected with packing material and electrically protected with an
anti-static bag during shipment. However, it is recommended that the board be visually
inspected for evidence of mishandling prior to applying power.
INSTALLATION
Power should be removed from the I/O Server when installing modules, cables, termination
panels, and field wiring.
CONNECTORS
Field I/O Connector (P2)
P2 provides the field I/O interface connections for mating IOS modules to the carrier board.
P2 is a 50-pin female receptacle header which mates to the male connector of the carrier
board. This provides excellent connection integrity and utilizes gold-plating in the mating
area. The field and logic side connectors are keyed to avoid incorrect assembly.
P2 pin assignments are unique to each IOS model (see Table 2) and correspond to the pin
numbers of the field I/O interface connector on the carrier board.

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Table 2 IOS 57x Field I/O Pin Connections (P2)
Pin Description
Number
Pin Description
Number
CH0_RT_ADDR0
1
CH1_RT_ADDR0
26
CH0_RT_ADDR1
2
CH1_RT_ADDR1
27
CH0_RT_ADDR2
3
CH1_RT_ADDR2
28
CH0_RT_ADDR3
4
CH1_RT_ADDR3
29
CH0_RT_ADDR4
5
CH1_RT_ADDR4
30
CH0_RT_PARITY
6
CH1_RT_PARITY
31
GND
7
TAG_CLOCK_OUT
32
TAG_CLOCK_IN
8
GND
33
GND
9
GND
34
GND
10
CH1B_DIRECT_N
35
CH1B_XFMR_N
11
CH1B_DIRECT_P
36
CH1B_XFMR_P
12
GND
37
GND
13
GND
38
GND
14
CH1A_DIRECT_N
39
CH1A_XFMR_N
15
CH1A_DIRECT_P
40
CH1A_XFMR_P
16
GND
41
GND
17
GND
42
GND
18
CH0B_DIRECT_N
43
CH0B_XFMR_N
19
CH0B_DIRECT_P
44
CH0B_XFMR_P
20
GND
45
GND
21
GND
46
GND
22
CH0A_DIRECT_N
47
CH0A_XFMR_N
23
CH0A_DIRECT_P
48
CH0A_XFMR_P
24
Reserved1
49
GND
25
Not connected
50
Note: (Table 2)
1. Reserved for factory programming
CABLE
A cable, model number 5028-570 is available. The cable includes Twin-ax connectors for
each of the four transformer coupled channels: CH0A, CH0B, CH1A, CH1B, and a 15 pin
DSUB connector for access to the remote terminal address lines and TAG clock I/O.
Figure 2 5028-570 Cable

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Table 3 5028-570 Cable 15 Pin DSUB pin assignments
Pin Description
Number
CH0_RT_ADDR0
1
CH0_RT_ADDR1
2
CH0_RT_ADDR2
3
CH0_RT_ADDR3
4
CH0_RT_ADDR4
5
CH0_RT_PARITY
6
GND
7
TAG_CLOCK_IN
8
CH1_RT_ADDR0
9
CH1_RT_ADDR1
10
CH1_RT_ADDR2
11
CH1_RT_ADDR3
12
CH1_RT_ADDR4
13
CH1_RT_PARITY
14
TAG_CLOCK_OUT
15
Non-Isolation Considerations
The board is non-isolated, since there is electrical continuity between the logic and field I/O
grounds. As such, the field I/O connections are not isolated from the system. Care should
be taken in designing installations without isolation to avoid noise pickup and ground loops
caused by multiple ground connections.
PROGRAMMING INFORMATION
This Section provides the specific information necessary to program and operate the board.
IDENTIFICATION PROM
Each IOS module contains identification (ID) information that resides in the ID address
space. This area of memory contains 32 bytes of information at most. Both fixed and
variable information may be present within the ID space. Fixed information includes the
"IPAH" identifier, model number, and manufacturer's identification codes. Variable
information includes unique information required for the module. The IOS-57x ID
information does not contain any variable (e.g. unique calibration) information. ID space
bytes are addressed using only the odd addresses in a 64 byte block (on the “Big Endian”
VMEbus). Even addresses are used on the “Little Endian” PC PCI bus. The IOS-57x ID
space contents are shown in Table 4. Note that the base-address for the IOS module ID
space (see your carrier board instructions) must be added to the addresses shown to
properly access the ID space. Execution of an ID space read requires 1 wait state.

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Table 4 IOS-57x ID ROM
Hex
Offset
From ID
PROM
Base
Address
ASCII
Character
Equivalent
Numeric
Value
(Hex)
Field Description
00
I
49
Format I ID ROM supports 8 or 32 MHz IOS
bus clock frequency
02
P
50
04
A
41
06
H
48
08
A3
Acromag ID Code
0A
IOS Model Code1
52
IOS-571
53
IOS-572
0C
00
Not Used (Revision)
0E
00
Reserved
10
00
Not Used (Driver ID Low Byte)
12
00
Not Used (Driver ID High Byte)
14
0C
Total Number of ID PROM Bytes
16
CRC
8F
IOS-571
EE
IOS-572
18 to 3E
yy
Not Used
Note (Table 4):
1. The model number is represented by a two-digit code within the ID space (the
IOS-571 model is represented by 52H, the IOS-572 is represented by 53H).
ADDRESS MAP
Table 5 IOS-57x Address Map
Description
IOS Address
Space
Access Type
Address Offset from
base
Control Register
I/O
16 bit only
0
Status Register
I/O
16 bit only
2
Channel 0 Interrupt Vector
I/O
8 bit
4
Channel 1 Interrupt Vector
I/O
8 bit
6
ID ROM
ID
8 bit
0x00 –0x16
Channel 0 uACE registers
Memory
16 bit only
0x00000 –0x0003E
Channel 0 uACE RAM
Memory
16 bit only
0x20000 –0x3FFFE
Channel 1 uACE registers
Memory
16 bit only
0x40000 –0x4003E
Channel 1 uACE RAM
Memory
16 bit only
0x60000 –0x7FFFE
I/O SPACE ADDRESS MAP
I/O address space is used to provide access to control registers, a status register, and
interrupt vector registers.

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The I/O space may be as large as 64, 16-bit words (128 bytes) using address lines A1 to
A6, but the IOS-57x uses only a portion of this space. The I/O space address map for the
IOS-57x is shown in Table 5. Note that the base address for the IOS module I/O space
(see your carrier board instructions) must be added to the addresses shown to properly
access the I/O space.
Table 6 Control Register Read / Write I/O base address + 0
Bit
Description
Reset State
15 - 14
IOS bus clock
0
13
Channel 1 Transceiver Inhibit A
0
12
Channel 1 Transceiver Inhibit B
0
11
Channel 1 Master Clear
0
10
Channel 1 Built In Self Test Enable
0
9
Channel 1 Remote Terminal Address Latch
0
8
Channel 1 Interrupt Enable
0
7
Tag Clock Source
0
6
Not used
0
5
Channel 0 Transceiver Inhibit A
0
4
Channel 0 Transceiver Inhibit B
0
3
Channel 0 Master Clear
0
2
Channel 0 Built In Self Test Enable
0
1
Channel 0 Remote Terminal Address Latch
0
0
Channel 0 Interrupt Enable
0
IOS bus clock: A phase locked loop is used to generate the module clock from the IOS
bus clock. The IOS bus clock must remain constant after setting the appropriate bits in this
register. The module clock is not enabled until the IOS bus clock frequency is specified by
writing the following bit pattern:
00 –module clock disabled
01 –IOS bus clock 8 MHz, enable module clock
10 –IOS bus clock 32 MHz, enable module clock
11 –module clock disabled
Transceiver Inhibit A:
0 - transceiver enable
1 –transceiver disabled
Transceiver Inhibit B:
0 - transceiver enable
1 –transceiver disabled
Master Clear: is a write only bit, always reads as 0
0 –normal operation
1 –hardware reset
Built In Self Test Enable:
0 –disables both the power up and user initiated built in self test
1 –built in self test will be enabled after hardware reset
Remote Terminal Address Latch: controls the μ-ACE's internal RT address latch. (see μ-
ACE hardware manual for further description)
Interrupt enable:
0 –interrupts disabled
1 –interrupts enabled

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Tag Clock Source:
0 –internal (FPGA 100 KHz clock)
1 –external (P2 connector)
Table 7 Status Register Read I/O base address + 2
Bit
Description
15
Module Clock Ready
14
Not used
13
Not used
12
Not used
11
Not used
10
Not used
9
Not used
8
Channel 1 Interrupt Pending
7
Not used
6
Not used
5
Not used
4
Not used
3
Not used
2
Not used
1
Not used
0
Channel 0 Interrupt Pending
Module Clock Ready –Indicates the status of the phase locked loop that generates the 16
MHz module clock from the IOS bus clock:
0 - not ready
1 - ready
Interrupt Pending
0 –no interrupts pending
1 –interrupt pending
Channel 0 interrupt is connected to IRQ0
Channel 1 interrupt is connected to IRQ1
MEMORY SPACE ADDRESS MAP
This board is addressable in memory space to access the Micro ACE 1553 controllers.
The IOS-571 uses the lower 256K bytes of this memory space to access channel 0
registers and memory. The IOS-572 uses the lower 512K bytes of this memory space to
access channels 0 and 1 registers and memory.
Micro ACE access
The address space for each Micro ACE is divided into two regions: register and memory.
The 32 Micro ACE registers are located at IOS memory space base address + (channel *
0x40000) + (register address * 2). The Micro ACE also includes 64 K 16 bit words of
memory. The memory region is located at IOS memory space base address + (channel *
0x40000) + 0x20000 + memory address. The Micro ACE is a 16 bit device and should be
accessed in 16 bit mode. See Table 8 for a brief overview of the Micro ACE registers and
their addresses in IOS memory space. See the Enhanced Mini-ACE® Series Users Guide
for a detailed description of the registers and their functions.

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Table 8 Micro ACE Register descriptions
Mem base +
Address (Hex)
Description
CHANNEL 0
00000
Interrupt Mask Register #1 (RD/WR)
00002
Configuration Register #1 (RD/WR)
00004
Configuration Register #2 (RD/WR)
00006
Start/Reset Register (WR)
00006
Non-Enhanced BC/RT Command Stack Pointer / Enhanced BC
Instruction List Pointer Register (RD)
00008
BC Control Word /RT Subaddress Control Word Register (RD/WR)
0000A
Time Tag Register (RD/WR)
0000C
Interrupt Status Register #1 (RD)
0000E
Configuration Register #3 (RD/WR)
00010
Configuration Register #4 (RD/WR)
00012
Configuration Register #5 (RD/WR)
00014
RT / Monitor Data Stack Address Register (RD)
00016
BC Frame Time Remaining Register (RD)
00018
BC Time Remaining to Next Message Register (RD)
0001A
Non-Enhanced BC Frame Time / Enhanced BC Initial Instruction Pointer
/ RT Last Command / MT Trigger Word Register(RD/WR)
0001C
RT Status Word Register (RD)
0001E
RT BIT Word Register (RD)
00020
Test Mode Register 0
00022
Test Mode Register 1
00024
Test Mode Register 2
00026
Test Mode Register 3
00028
Test Mode Register 4
0002A
Test Mode Register 5
0002C
Test Mode Register 6
0002E
Test Mode Register 7
00030
Configuration Register #6 (RD/WR)
00032
Configuration Register #7 (RD/WR)
00034
RESERVED
00036
BC Condition Code Register (RD)
00036
BC General Purpose Flag Register (WR)
00038
BIT Test Status Register (RD)
0003A
Interrupt Mask Register #2 (RD/WR)
0003C
Interrupt Status Register #2 (RD)
0003E
BC General Purpose Queue Pointer /RT-MT Interrupt Status Queue
Pointer Register (RD/WR)
20000
3FFFE
Channel 0 RAM first word
Channel 0 RAM last word

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Mem base +
Address (Hex)
Description
CHANNEL 1
40000
Interrupt Mask Register #1 (RD/WR)
40002
Configuration Register #1 (RD/WR)
40004
Configuration Register #2 (RD/WR)
repeat of Channel 0 register descriptions
4003E
BC General Purpose Queue Pointer /RT-MT Interrupt Status Queue
Pointer Register (RD/WR)
60000
7FFFE
Channel 1 RAM first word
Channel 1 RAM last word
PROGRAMMING INTERRUPTS
Interrupts generated by the IOS-57x modules use interrupt request lines INTREQ0*
(Interrupt Request 0) for 1553 channel 0 and INTREQ1* (Interrupt Request 1) for 1553
channel 1.
The IOS-57x Interrupt Vector register can be used as a pointer to an interrupt handling
routine. The vector is an 8-bit value and can be used to point to any one of 256 possible
locations to access the interrupt handling routine.
To enable 1553 channels to generate interrupts set the appropriate interrupt enable bit in
the IOS I/O space Control Register for each 1553 channel. Set bit 3 in the Micro ACE
Configuration Register #2 to select LEVEL type interrupt signaling for each channel. This
will enable the FPGA to pass the Micro ACE interrupt signal through to the IOS bus
INTREQx interrupt. See the Enhanced Mini-ACE® Series Users Guide for details on
configuring the many Micro ACE interrupt options.
The INTREQ0* or INTREQ1* line is released when the INTERRUPT STATUS
REGISTER(s) for the appropriate channel are read. See the Enhanced Mini-ACE® Series
Users Guide for details on AUTO CLEAR options for the pending interrupts.
THEORY OF OPERATION
This section contains information regarding the hardware of the IOS-57x series of modules.
A description of the functions of the circuitry used on the board is also provided. Refer to
Figure 1, IOS-572 block diagram as you review this material.
LOGIC/POWER INTERFACE
The logic interface to the carrier board is made through connector P1 (refer to Error!
Reference source not found.). The P1 interface also provides +5V power to the module.
Note that the DMA control, ERROR , and STROBE signals are not used.
A Field Programmable Gate-Array (FPGA) installed on the IOS Module provides an
interface to the carrier board. The interface to the carrier board allows complete control of
all IOS-57x functions.
IOS INTERFACE LOGIC
IOS interface logic of the IOS-57x is included in the FPGA. This logic includes: address
decoding, I/O and ID read/write control circuitry, and ID PROM implementation.

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Address decoding of eighteen of the IOS address signals A (1:18) is implemented in the
FPGA, in conjunction with the IOS select signals, to identify access to the IOS modules
MEM, INT, ID or I/O spaces. In addition, the byte strobes BS0 and BS1 are decoded to
identify low byte, high byte, or double byte data transfers.
The carrier to IOS module interface implements access to MEM, INT, ID and I/O space via
16 or 8-bit data transfers. Read only access to ID space provides the identification for the
module (as given in Table 1). Read and write access to the I/O space provides a means to
control the IOS-57x and monitor status. Reads and writes to MEM space provide access to
the Micro ACE 1553 controllers.
The timing for access to the various address spaces is shown in Table 9.
Table 9 Access Times
Address Space
Wait States
Read
Write
INT
1
0
ID
1
N/A
I/O
1
0
MEM (8 MHz IOS clock)
3
3
MEM (32 MHz IOS
clock)
8
8
IOS-57xCONTROL LOGIC
All logic to provide access to the Micro ACE 1553 controllers is imbedded in the module’s
FPGA. Once the IOS-57x FPGA has been configured, the control logic provides the
following functions:
Source of the 16 MHz clock to the Micro ACE.
Issues interrupt requests to the carrier.
Controls the Micro ACE master clear (reset) signal
Source of the 100 KHz tag clock output signal used to synchronize the IOS-57x
with external devices
Accepts an external TTL level tag clock input signal to synchronize the IOS-57x
with external devices
Provides mode control (inhibit) to each of the Micro ACE dual redundant
transceivers.
TAG CLOCK Input / Output
The TAG clock for each 1553 channel can be selected from three possible sources:
Micro ACE internal time tag clock, selectable 2µs, 4µs, 8µs, 16µs, 32µs, 64µs
resolution.
FPGA generated 100 KHz clock, provides 10 µs resolution. This clock is also an
output on the P2 connector.
External (P2 connector) tag clock input.
To select the Micro ACE internal time tag clock: write bits TTR2:0 in configuration register
#2 for each 1553 channel with the appropriate pattern for the resolution desired.
To select the FPGA generated 100 KHz clock as the Micro ACE time tag clock: write bits
TTR2:0 in configuration register #2 with the bit pattern “111”. Write the tag clock source
(bit 7) of the IOS I/O space control register with the value 0.

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To select the external time tag clock input as the Micro ACE time tag clock: write bits
TTR2:0 in configuration register #2 with the bit pattern “111”. Write the tag clock source
(bit 7) of the IOS I/O space control register with the value 1.
Note: the selection of tag clock source in the IOS I/O space control register will affect both
1553 channels of an IOS-572 module.
STATIC MICRO ACE INPUTS
The SUBSYSTEM/EXT_TRIG Micro ACE input signal is permanently connected to logic 1
in the FPGA. The functions controlled by this static input signal have alternate methods of
control through host writes to Micro ACE registers. The subsystem flag bit can be set by
the host writing to bit 8 of Configuration Register #1 in RT mode. In BC mode, a frame can
be started by writing bit 1 of the Start/Reset Register with the value 1.
REMOTE TERMINAL ADDRESS
The RT address and parity signals for each of the 1553 channels are available at the P2
connector. Each of the signals has an adjacent ground signal on the connector for
convenient programming of the RT address through an attached wire harness. Each of the
address lines and parity bit has a pull up resistor on it. An unconnected input results in that
bit reading as logic 1. Grounding the input causes the bit to read as logic 0. The RT
address parity is odd, so the sum of the RT address input bits and the RT parity bit must be
odd. The RT address may be latched in the Micro ACE. The RT address latch signal is
controlled by the IOS I/O control register. Bit 9 controls the RT address latch signal for
channel 1, bit 1 controls the RT address latch signal for channel 0.
See section 6.29 RT Address Inputs of the Enhanced Mini-ACE® Series Users Guide for a
complete description of the options available for setting the RT address.
BUS CONNECTION
The IOS-57x modules may be connected to the1553 bus using either of two methods:
direct coupled (short stub) or transformer coupled (long stub). Both of these connection
methods are provided for both of the dual redundant (A and B) channels of each of the
1553 channels (0 and 1).
DIRECT COUPLING METHOD
Using the direct coupling method the IOS-57x module may be connected to the
1553 bus without any additional components. The transformer and isolation
resistors are included on the IOS-57x. The stub length may not exceed 1 foot.
The distance the signals travel across a carrier board must be subtracted from the
1 foot maximum length.
TRANSFORMER COUPLING METHOD
Using the transformer coupling method, stub lengths may be up to 20 feet. With
this method the IOS-57x does not connect directly to the 1553 bus. The IOS-57x
must connect to the bus through a bus coupler.
Transformer coupling provides improved thermal performance when compared with direct
coupling since the heat dissipated in the isolation resistors is located outside of the I/O
Server.
SERVICE AND REPAIR
Surface-Mounted Technology (SMT) boards are generally difficult to repair. It is highly
recommended that a non-functioning board be returned to Acromag for repair. The board
can be easily damaged unless special SMT repair and service tools are used. Further,

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Acromag, Inc. Tel:[phone] Fax:[phone] Email:[e-mail] www.acromag.com
Acromag has automated test equipment that thoroughly checks the performance of each
board. When a board is first produced and when any repair is made, it is tested, placed in a
burn-in room at elevated temperature, and retested before shipment.
Please refer to Acromag's Service Policy Bulletin or contact Acromag for complete details
on how to obtain parts and repair.
PRELIMINARY SERVICE PROCEDURE
Before beginning repair, be sure that all of the procedures in Section 2, Preparation for
Use, have been followed. Also, refer to the documentation of your carrier/CPU board to
verify that it is correctly configured. Replacement of the module with one that is known to
work correctly is a good technique to isolate a faulty module.
Acromag’s Applications Engineers can provide further technical assistance if required.
When needed, complete repair services are also available from Acromag.
WHERE TO GET HELP
If you continue to have problems, your next step should be to visit the Acromag worldwide
web site at http://www.acromag.com. Our web site contains the most up-to-date product
and software information.
Go to the “Support” tab to access:
Application Notes
Frequently Asked Questions (FAQ’s)
Product Knowledge Base
Tutorials
Software Updates/Drivers
An email question can also be submitted from within the Knowledge Base or directly from
the “Contact Us” tab.
Acromag’s application engineers can also be contacted directly for technical assistance via
telephone or FAX through the numbers listed at the bottom of this page. If needed,
complete repair services are also available.
SPECIFICATIONS
PHYSICAL
Physical Configuration
Length 3.880 in. (98.5 mm)
Width 1.780 in. (45.2 mm)
Board Thickness 0.062 in. (1.59 mm)
Max Component Height 0.290 in. (7.37 mm)
Connectors
IOS Logic Interface: 50-pin female receptacle header (AMP 173279-3 or equivalent).
Field I/O: 50-pin female receptacle header (AMP 173279-3 or equivalent).
Operating Temperature: -40 to 85 C.
Relative Humidity: 5-95% Non-Condensing.
Storage Temperature: -55 C to +125 C.
CAUTION: POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING
BOARDS

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Non-Isolated: Logic and field commons have a direct electrical connection.
Resistance to RFI: Complies with IEC 6100-4-3: 2006 (80MHz to 1000 MHz, 10
Volts/meter, No digital upset allowed)
Conducted R F Immunity (CRFI):
Complies with EN61000-4-6 (3V/rms, 150kHz to 80MHz) and
European Norm EN50082-1 with no digital upsets.
Surge Immunity: Not required for signal I/O per European Norm EN50082-1.
Electric Fast Transient Immunity EFT:
Complies IEC 6100-4-4: 2007
Electrostatic Discharge (ESD) Immunity:
Complies with IEC 61000-4-2: 2001, (8KV enclosure port air
discharge) Level 3, (4KV enclosure port contact discharge) Level
2, (2KV I/O terminal contact discharge).
Radiated Emissions: Meets or exceeds CISPR 16-2-3 for class B equipment.
Shielded cable with I/O connections in a shielded enclosure is
required to meet compliance.
Electrical/Mechanical Interface:
I/O Space: 16-bit and 8-bit
ID Space: 16 and 8-bit; Supports Type 1, 32 bytes per IOS (consecutive
even byte addresses). IPAH is used to indicate 32MHz
operation (8MHz operation is also supported).
Memory Space: 16-bit and 8-bit.
Interrupts: The INTREQ0 and INTREQ1 signals are used to request
interrupts provided by the Micro ACE.
DMA: Not implemented.

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Table 10 Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CHx_RT_ADDRx, CHx_RT_PARITY
VIL
low-level input
voltage
0.6
V
VIH
high-level input
voltage
2.0
3.3
V
IIL
low level current
VIL = 0 V
-330
µA
TAG_CLK_IN
VIL
low-level input
voltage
0.8
V
VIH
high-level input
voltage
2.0
3.3
V
IIN
maximum
leakage current
0 <= VIN <= 3.3 V
+/- 1
uA
TAG_CLK_OUT
VOL
low-level output
voltage
IOL = 50 µA
0.1
V
VOH
high-level output
voltage
IOH = -2 mA
2.9
V
output frequency
100
kHz
Power Requirements
+5V
Model IOS-571
0.3
0.6
A
Model IOS-572
0.6
1.2
A
+12V
not used
0
A
-12V
not used
0
A