ADLINK Technology Express-BD74 User manual

Leading EDGE COMPUTING
Express-BD74
User’s Manual
COM Express Basic Size Type 7 Module with up to 16-core
Intel® Xeon® D Processor and Four SODIMM sockets
Manual Rev.: 1.1
Revision Date: May 25, 2020
Part Number: 50-1J098-1010

ii Preface
Preface
Copyright
Copyright © 2019, 2020 ADLINK Technology, Inc. This document contains proprietary information protected by
copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other
means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and
function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer
be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use
the product or documentation, even if advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with
the European Union's Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic
Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to
ensure that our products, manufacturing processes, components, and raw materials have as little impact on the
environment as possible. When products are at their end of life, our customers are encouraged to dispose of them
in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or
registered trademarks of their respective companies.
Revision History
Revision Description Date By
1.0 Initial release 2019-09-30 JC
1.1 Update specifications and mechanical info; add SODIMM keep-out info 2020-05-25 JC

Express-BD74
Preface iii
Table of Contents
Preface................................................................................................................................ii
List of Figures ....................................................................................................................v
List of Tables.....................................................................................................................vi
1. Introduction................................................................................................................1
2. Specifications............................................................................................................3
2.1. Core System ...............................................................................................................3
2.2. Expansion Busses ......................................................................................................3
2.3. 10Gigabit Ethernet......................................................................................................4
2.4. Gigabit Ethernet..........................................................................................................4
2.5. Network Controller Sideband Interface (NC-SI)..........................................................4
2.6. Multi I/O and Storage..................................................................................................4
2.7. Serial I/O on Module ...................................................................................................5
2.8. Trusted Platform Module (TPM) .................................................................................5
2.9. SEMA Board Controller ..............................................................................................5
2.10. Debug......................................................................................................................5
2.11. Power Specifications ...............................................................................................6
2.12. Operating Temperatures .........................................................................................6
2.13. Environmental .........................................................................................................6
2.14. Specification Compliance ........................................................................................6
2.15. Operating Systems..................................................................................................6
2.16. Functional Diagram .................................................................................................7
2.17. Mechanical Drawing ................................................................................................8
3. Pinouts and Signal Descriptions..............................................................................9
3.1. AB/CD Pin Definitions.................................................................................................9
3.2. Signal Description Terminology ................................................................................12
3.3. AB Signal Descriptions .............................................................................................13
3.4. CD Signal Descriptions.............................................................................................20
4. Connectors, LEDs and Switches............................................................................25
4.1. Connector, Switch and LED Locations .....................................................................25
4.2. 40-pin Debug Connector...........................................................................................27
4.3. Status LEDs..............................................................................................................28
4.4. Fan Connector ..........................................................................................................29
4.5. BIOS Setup Defaults Reset Button...........................................................................30
4.6. Switch Settings .........................................................................................................31

iv Preface
4.7. PCIe x16-to-two-x8 Adapter Card.............................................................................32
4.8. PCIe x8-to-two-x4 Adapter Card...............................................................................32
5. Smart Embedded Management Agent (SEMA) .....................................................33
5.1. Board Specific SEMA Functions...............................................................................34
6. System Resources ..................................................................................................37
6.1. System Memory Map................................................................................................37
6.2. Direct Memory Access Channels..............................................................................39
6.3. Fixed I/O Address Range Map .................................................................................39
6.4. Variable I/O Address Range Map .............................................................................41
6.5. APIC Interrupt Mapping ............................................................................................42
6.6. PCI Configuration Space Map ..................................................................................43
6.7. PCI Interrupt Routing Map ........................................................................................44
6.8. SMBus Address Table ..............................................................................................44
7. BIOS Setup...............................................................................................................45
7.1. Menu Structure .........................................................................................................45
7.2. Main ..........................................................................................................................46
7.3. Advanced..................................................................................................................48
7.4. Chipset......................................................................................................................63
7.5. Security.....................................................................................................................78
7.6. Boot ..........................................................................................................................79
7.7. Save & Exit ...............................................................................................................80
8. BIOS Checkpoints, Beep Codes.............................................................................81
8.1. Status Code Ranges.................................................................................................82
8.2. Standard Status Codes.............................................................................................82
8.3. OEM-Reserved Checkpoint Ranges......................................................................... 89
9. Mechanical Information...........................................................................................91
9.1. Board-to-Board Connectors......................................................................................91
9.2. Thermal Solution.......................................................................................................92
9.3. Mounting Methods ....................................................................................................95
9.4. Standoff Types..........................................................................................................96
Safety Instructions...........................................................................................................97
Getting Service.................................................................................................................98

Express-BD74
Preface v
List of Figures
Figure 1: Express-BD74 Functional Block Diagram.................................................................................7
Figure 2: Express-BD74 Mechanical Drawing..........................................................................................8
Figure 3: Express-BD74 Connector, Switch and LED Locations .......................................................... 25
Figure 4: Express-BD74 and the DB40 Debug Module ........................................................................ 26
Figure 5: Express-BD74 Switch Locations ............................................................................................ 31
Figure 6: COM Express Mounting Methods ..........................................................................................95
Figure 7: COM Express Standoff Types................................................................................................ 96

vi Preface
List of Tables
Table 1: Express-BD74 AB/CD Pin Definitions ........................................................................................9
Table 2: 40-pin Debug Connector Pin Definition ................................................................................... 27
Table 3: Express-BD74 LED Descriptions ............................................................................................ 28
Table 5: Fan Connector Pin Definition .................................................................................................. 29
Table 6: BIOS Select and Mode Configuration Switch Settings............................................................ 31
Table 7: SEMA Onboard Voltage Monitor ............................................................................................. 34
Table 8: SEMA BMC Status .................................................................................................................. 34
Table 9: SEMA Exception Codes .......................................................................................................... 35
Table 10: SEMA BMC Flags.................................................................................................................. 36

Express-BD74
Introduction 1
1. Introduction
The Express-BD74 is a COM Express® COM.0 R3.0 Basic Size Type 7 module supporting the 64-bit Intel® Xeon®
processor D (formerly “Broadwell-DE”) system-on-chip (SoC) with up to 4 SO-DIMMs to boost system performance.
The Express-BD74 is specifically designed for customers who need excellent computing performance with
balanced power consumption and multiple 10G Ethernet connectivity in a long product life solution.
The Express-BD74 features Intel® Virtualization Technology (including VT-x, VT-d, EPT), Intel® Hyper-Threading
Technology (up to 16 cores, 32 threads), Intel® Trusted Execution Technology, Intel® AES-NI Technology, and
4 SO-DIMMs to provide a maximum of 128GB DDR4 ECC (or non-ECC) memory capacity and dual-channel
memory design at 1866/2133/2400 MHz (dependent on SoC SKU) for excellent overall performance.
An integrated Intel® 10G Ethernet controller supports two 10GBASE-KR interfaces, relevant sideband signals and
NC-SI. The Express-BD74 is designed to serve customers with optimized computing capability per watt and high
speed connectivity requirements who want to outsource the custom core logic of their systems for reduced
development time.
Input/output features include 24 PCIe Gen3 lanes, up to 8 PCIe Gen2 lanes, a single onboard Gigabit Ethernet port,
USB 3.0/2.0 ports, and SATA 6 Gb/s ports. Support is provided for SMBus and I2C. The module is equipped with
SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as remote console, hardware monitor,
and watchdog timer.

2 Introduction
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Express-BD74
Specifications 3
2. Specifications
2.1. Core System
CPU Intel® Xeon® processor D, Pentium® D processor (formerly “Broadwell-DE”)
•Intel® Xeon® D1539 1.6/1.9 GHz 35W (8C, up to 2133MHz) (eTEMP)
•Intel® Xeon® D1559 1.5/1.8 GHz 45W (12C, up to 2133MHz) (eTEMP)
•Intel® Xeon® D1548 2.0/2.3 GHz 45W (8C, up to 2400MHz)
•Intel® Xeon® D1577 1.3/1.6 GHz 45W (16C, up to 2400MHz)
Note: D1577 are supported by project basis. Please contact local sales.
Supporting: Intel® VT (including VT-x, VT-d, VT-x with Extended Page Tables), Intel® HT
Technology, Intel® SSE4.2, Intel® 64 Architecture, Intel® Turbo Boost Technology 2.0,
Intel® AVX2, Intel® TSX-NI, Intel® Platform Protection Technology with Intel® TXT and
Execute Disable Bit, Intel® Data Protection Technology with Intel® Secure Key and Intel®
AES-NI
Note: Availability of features may vary between processor SKUs.
Cache 24MB for D1577, 18MB for D1559, 12MB for D1548/D1539
Memory Dual channel ECC (or non-ECC) 1866/2133/2400 MHz DDR4 memory up to 128GB in
four SODIMM sockets (two on top, two on bottom)
Note: Supported memory frequencies may vary between processor SKUs.
Embedded BIOS AMI UEFI with CMOS backup in 16MB SPI BIOS
Chipset Integrated in SoC
2.2. Expansion Busses
PCI Express 16 PCI Express Lanes Gen3 (CD):
Lanes 16-31 (four controllers, can be configured to 1 x16, 2 x8 or 4 x4/x2/x1)
8 PCI Express Lanes Gen3 (AB):
Lanes 8-15 (two controllers, can be configured to 1 x8 or 2 x4/x2/x1)
Up to 8 PCI Express Lanes Gen2 (AB/CD):
Lanes 0-7 (two controllers defined by PICMG, can be configured to x4, x2, x1)
Notes:
•PCIe lane 7 is supported by build option, in place of GbE
•Although Broadwell-DE platform supports eight roots on Lanes 0-7, the PICMG COM.0
R3.0 specification for Lanes 0-7 states: “Type7 module may support eight x1 root hubs.
It is expected that future generation products may limit the number of available root
hubs.”
Other •LPC bus
•SMBus (system)
•I2C (user)

4 Specifications
2.3. 10Gigabit Ethernet
Integrated on Processor Intel® 10G Ethernet Controller
10GbE Feature Support •Two 10GBASE-KR (on CD connector)
•Sideband signals (on CD connector) for 10GbE
•10G_INT
•10G_PHY_MDIO_SDA and 10G_PHY_MDC_SCL (manage/control signals
between MAC and PHY)
•10G_PHY_CAP (PHY mode capability pin, used to indicate whether the PHY on
carrier board needs I2C or MDIO signals from module)
•10G_PHY_RST (PHY reset signal, only for Optical PHY)
•10G_LED_SDA and 10G_LED_SCL (LED signals carried through dedicated I2C
bus; additional strapping signal through I2C bus; LED signals programmable for
indicating ACT, LINK, Speed)
•10G_SFP_SDA and 10G_SFP_SCL (dedicated for Optical PHY use, connect to
external SFP module)
•10G_SDP (Software-Definable Pin for general purpose)
2.4. Gigabit Ethernet
Intel Controller Intel® i210 Ethernet Controller
Interface 10/100/1000 Mbit/s connection
2.5. Network Controller Sideband Interface (NC-SI)
zNC-SI (on AB connector): manageability interface, connecting to IPMI BMC located on carrier board
•Routing from Intel® i210 Ethernet Controller to row AB connector by default
•Build option to support routing from 10GbE controller to row AB connector
2.6. Multi I/O and Storage
I/O Hub Integrated on SoC
USB 4x USB 3.0/2.0 (USB 0,1,2,3)
SATA* 2x SATA 6Gb/s (SATA 0,1)
GPIO 4 GPO and 4 GPI
*Note: For SATA 6Gb/s compatibility, it is strongly recommended to use a SATA redriver on the carrier board.

Express-BD74
Specifications 5
2.7. Serial I/O on Module
zChipset: Nuvoton NCT5104D
Note: two UART ports native from SoC instead of NCT5104D supported by build option
zPorts: 2x UARTs Rx/Tx only
zConsole Redirection: COM 1 or COM 2 selectable in BIOS
COM Port Description IRQ Address Console redirection support
COM 1 Supported by module (SER0, A98/A99), via NCT5104D 10 0x240 Yes
COM 2 Supported by module (SER1, A101/A102), via NCT5104D 11 0x248 Yes
COM 3 Supported by Super I/O (W83627DHG) on carrier board 4 0x3F8 Yes
COM 4 Supported by Super I/O (W83627DHG) on carrier board 3 0x2F8 Yes
2.8. Trusted Platform Module (TPM)
zChipset: Infineon
zType: TPM 2.0
2.9. SEMA Board Controller
zType: ADLINK Smart Embedded Management Agent (SEMA)
zFunctions:
•Voltage/Current monitoring
•Power sequence debug support
•AT/ATX mode control
•Logistics and forensic information
•Flat panel control
•General purpose I2C
•Failsafe BIOS (dual BIOS) (build opt.)
•Watchdog timer and fan control
2.10. Debug
z40-pin flat cable connector to be used with DB-40 debug module
Supports: BIOS POST code LED, BMC access, SPI BIOS flashing, power testpoints, debug LEDs

6 Specifications
2.11. Power Specifications
Power Modes AT and ATX mode (AT mode startup controlled by SEMA Board Controller)
Standard Voltage Input ATX @ 12V±5%,/ 5Vsb ±5% or AT @ 12V ±5%
Wide Voltage Input ATX @ 8.5-20V, 5Vsb ±5% or AT @ 8.5-20V
Power Management ACPI 5.0 compliant, Smart Battery support
Power States Supports C0, C1, C1E, C3, C6, S0, S4, S5, S5 ECO mode
(Wake-on-USB S4, WOL S4/S5)
ECO Mode Supports deep S5 for 5Vsb power saving
2.12. Operating Temperatures
Standard Operating
Temperature 0°C to +60°C (Wide Voltage Input)
Storage: -20°C to +80°C
Extreme Rugged Operating
Temperature (optional) -40°C to +85°C (Standard Voltage Input, dependent on SoC SKU, build option support)
Storage: -40°C to +85°C
2.13. Environmental
Humidity Operating: 5-90% RH, non-condensing
Storage: 5-95% RH (and operating with conformal coating)
Shock and Vibration IEC 60068-2-64 and IEC-60068-2-27
MIL-STD-202F, Method 213B, Table 213-I, Condition A and Method 214A, Table 214-I,
Condition D
HALT Thermal Stress, Vibration Stress, Thermal Shock and Combined Test
2.14. Specification Compliance
zPICMG COM.0: Rev 3.0 Type 7, Basic size 125 x 95 mm
2.15. Operating Systems
Standard Support •Windows Server 2012 R2 (64-bit)
•Windows 7 (64-bit)
•Windows 10 (64-bit)
•Linux (64-bit)
Extended Support (BSP) •Linux (64-bit)

Express-BD74
Specifications 7
2.16. Functional Diagram
SODIMM 4
4‐32 GB ECC/non‐ECC DDR4
SODIMM 3
4‐32 GB ECC/non‐ECC DDR4
AB
Intel® Xeon® D
“Broadwell‐DE”
LM73
Sensor
TPM 2.0
GP I2C
CD
SPI 0
BIOS
LPC bus
16 PCIe lanes (Gen3)
(port 16‐31)
SPI
Debug
header
2x SATA 6Gb/s
(port 0/1)
4 x USB 2.0
(port 0/1/2/3)
4x USB 3.0 upgrade
(port 0/1/2/3)
UART0/1
SPI 1
BIOS
1 PCIe lane (Gen2)
(port 6)
SPI_CS#
1x10GKR
1x 10G KR
6 PCIe lanes (Gen2)
(port 0‐5)
New
SEMA
BMC
GPIO
PCA9535
SODIMM 2/4
Up to 2400 MHz
4‐32 GB ECC/non‐ECC DDR4
SODIMM 1/3
Up to 2400 MHz
4‐32 GB ECC/non‐ECC DDR4
4x GPO, 4x GPI
SMBus
LPC to UART
NCT5014D
GbE
Controller
1 PCIe lane (Gen2)
(port 7)
Note: Memory frequency dependent on SoC SKU
SMBus
NC‐SI
10G Sideband Signals
8 PCIe lanes (Gen3)
(port 8‐15)
Figure 1: Express-BD74 Functional Block Diagram

8 Specifications
2.17. Mechanical Drawing
0 4
80
121
125
71.15
31.66
0
4
91
68.58
28.33
95
Top
Vie
w
2
9.2 μ0.258 μ0.25
Front
Vie
w
0
4
68.5
8
91
95
18
6
28.3
3
0 4
80
16.5
74.2
121
87.0
125
8.35
87.2
5
31.655
71.152
Bottom Side RAM
Module Keepout
Bottom
Vie
w
All dimensions are shown in millimeters. Tolerances should be ± 0.25mm, unless otherwise noted.
The tolerances on the module connector locating peg holes (dimensions [16.50, 6.00] and [16.50, 18.00])
should be ± 0.10mm.
Figure 2: Express-BD74 Mechanical Drawing

Express-BD74
Pinouts and Signal Descriptions 9
3. Pinouts and Signal Descriptions
3.1. AB/CD Pin Definitions
The Express-BD74 is a Type 7 module supporting up to 32 PCIe lanes and 10G Ethernet on the CD connector and
NC-SI on the AB connector. In the table below, all standard pins of the COM Express specification are described,
including those not supported on the Express-BD74. Signals not supported on the Express-BD74 module are
crossed out.
Table 1: Express-BD74 AB/CD Pin Definitions
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A1 GND (fixed) B1 GND (fixed) C1 GND (fixed) D1 GND (fixed)
A2 GBE0_MDI3- B2 GBE0_ACT# C2 GND D2 GND
A3 GBE0_MDI3+ B3 LPC_FRAME#
/ESPI_CS0# C3 USB_SSRX0- D3 USB_SSTX0-
A4 GBE0_LINK100# B4 LPC_AD0
/ESPI_IO_0 C4 USB_SSRX0+ D4 USB_SSTX0+
A5 GBE0_LINK1000# B5 LPC_AD1
/ESPI_IO_1 C5 GND D5 GND
A6 GBE0_MDI2- B6 LPC_AD2
/ESPI_IO_2 C6 USB_SSRX1- D6 USB_SSTX1-
A7 GBE0_MDI2+ B7 LPC_AD3
/ESPI_IO_3 C7 USB_SSRX1+ D7 USB_SSTX1+
A8 GBE0_LINK# B8 LPC_DRQ0#
/ESPI_ALERT0# C8 GND D8 GND
A9 GBE0_MDI1- B9 LPC_DRQ1#
/ESPI_ALERT1# C9 USB_SSRX2- D9 USB_SSTX2-
A10 GBE0_MDI1+ B10 LPC_CLK
/ESPI_CK C10 USB_SSRX2+ D10 USB_SSTX2+
A11 GND (fixed) B11 GND (fixed) C11 GND (fixed) D11 GND (fixed)
A12 GBE0_MDI0- B12 PWRBTN# C12 USB_SSRX3- D12 USB_SSTX3-
A13 GBE0_MDI0+ B13 SMB_CK C13 USB_SSRX3+ D13 USB_SSTX3+
A14 GBE0_CTREF B14 SMB_DAT C14 GND D14 GND
A15 SUS_S3# B15 SMB_ALERT# C15 10G_PHY_MDC_SCL3 D15 10G_PHY_MDIO_SDA3
A16 SATA0_TX+ B16 SATA1_TX+ C16 10G_PHY_MDC_SCL2 D16 10G_PHY_MDIO_SDA2
A17 SATA0_TX- B17 SATA1_TX- C17 10G_SDP2 D17 10G_SDP3
A18 SUS_S4# B18 SUS_STAT#
/ESPI_RESET# C18 GND D18 GND
A19 SATA0_RX+ B19 SATA1_RX+ C19 PCIE_RX6+ D19 PCIE_TX6+
A20 SATA0_RX- B20 SATA1_RX- C20 PCIE_RX6- D20 PCIE_TX6-
A21 GND (fixed) B21 GND (fixed) C21 GND (fixed) D21 GND (fixed)
A22 PCIE_TX15+ B22 PCIE_RX15+ C22 PCIE_RX7+ D22 PCIE_TX7+
A23 PCIE_TX15- B23 PCIE_RX15- C23 PCIE_RX7- D23 PCIE_TX7-
A24 SUS_S5# B24 PWR_OK C24 10G_INT2 D24 10G_INT3
A25 PCIE_TX14+ B25 PCIE_RX14+ C25 GND D25 GND
A26 PCIE_TX14- B26 PCIE_RX14- C26 10G_KR_RX3+ D26 10G_KR_TX3+
A27 BATLOW# B27 WDT C27 10G_KR_RX3- D27 10G_KR_TX3-
A28 (S)ATA_ACT# B28 RSVD C28 GND D28 GND
A29 RSVD B29 RSVD C29 10G_KR_RX2+ D29 10G_KR_TX2+
A30 RSVD B30 RSVD C30 10G_KR_RX2- D30 10G_KR_TX2-
A31 GND (fixed) B31 GND (fixed) C31 GND (fixed) D31 GND (fixed)
A32 RSVD B32 SPKR C32 10G_SFP_SDA3 D32 10G_SFP_SCL3
A33 RSVD B33 I2C_CK C33 10G_SFP_SDA2 D33 10G_SFP_SCL2
A34 BIOS_DIS0#
/ESPI_SAFS B34 I2C_DAT C34 10G_PHY_RST_23 D34 10G_PHY_CAP_23
A35 THRMTRIP# B35 THRM# C35 10G_PHY_RST_01 D35 10G_PHY_CAP_01

10 Pinouts and Signal Descriptions
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A36 PCIE_TX13+ B36 PCIE_RX13+ C36 10G_LED_SDA D36 RSVD
A37 PCIE_TX13- B37 PCIE_RX13- C37 10G_LED_SCL D37 RSVD
A38 GND B38 GND C38 10G_SFP_SDA1 D38 10G_SFP_SCL1
A39 PCIE_TX12+ B39 PCIE_RX12+ C39 10G_SFP_SDA0 D39 10G_SFP_SCL0
A40 PCIE_TX12- B40 PCIE_RX12- C40 10G_SDP0 D40 10G_SDP1
A41 GND (fixed) B41 GND (fixed) C41 GND (fixed) D41 GND (fixed)
A42 USB2- B42 USB3- C42 10G_KR_RX1+ D42 10G_KR_TX1+
A43 USB2+ B43 USB3+ C43 10G_KR_RX1- D43 10G_KR_TX1-
A44 USB_2_3_OC# B44 USB_0_1_OC# C44 GND D44 GND
A45 USB0- B45 USB1- C45 10G_PHY_MDC_SCL1 D45 10G_PHY_MDIO_SDA1
A46 USB0+ B46 USB1+ C46 10G_PHY_MDC_SCL0 D46 10G_PHY_MDIO_SDA0
A47 VCC_RTC B47 ESPI_EN C47 10G_INT0 D47 10G_INT1
A48 RSVD B48 USB0_HOST_PRSNT C48 GND D48 GND
A49 GBE0_SDP B49 SYS_RESET# C49 10G_KR_RX0+ D49 10G_KR_TX0+
A50 LPC_SERIRQ
/ESPI_CS1# B50 CB_RESET# C50 10G_KR_RX0- D50 10G_KR_TX0-
A51 GND (fixed) B51 GND (fixed) C51 GND (fixed) D51 GND (fixed)
A52 PCIE_TX5+ B52 PCIE_RX5+ C52 PCIE_RX16+ D52 PCIE_TX16+
A53 PCIE_TX5- B53 PCIE_RX5- C53 PCIE_RX16- D53 PCIE_TX16-
A54 GPI0 B54 GPO1 C54 TYPE0# D54 RSVD
A55 PCIE_TX4+ B55 PCIE_RX4+ C55 PCIE_RX17+ D55 PCIE_TX17+
A56 PCIE_TX4- B56 PCIE_RX4- C56 PCIE_RX17- D56 PCIE_TX17-
A57 GND B57 GPO2 C57 TYPE1# D57 TYPE2#
A58 PCIE_TX3+ B58 PCIE_RX3+ C58 PCIE_RX18+ D58 PCIE_TX18+
A59 PCIE_TX3- B59 PCIE_RX3- C59 PCIE_RX18- D59 PCIE_TX18-
A60 GND (fixed) B60 GND (fixed) C60 GND (fixed) D60 GND (fixed)
A61 PCIE_TX2+ B61 PCIE_RX2+ C61 PCIE_RX19+ D61 PCIE_TX19+
A62 PCIE_TX2- B62 PCIE_RX2- C62 PCIE_RX19- D62 PCIE_TX19-
A63 GPI1 B63 GPO3 C63 RSVD D63 RSVD
A64 PCIE_TX1+ B64 PCIE_RX1+ C64 RSVD D64 RSVD
A65 PCIE_TX1- B65 PCIE_RX1- C65 PCIE_RX20+ D65 PCIE_TX20+
A66 GND B66 WAKE0# C66 PCIE_RX20- D66 PCIE_TX20-
A67 GPI2 B67 WAKE1# C67 RSVD D67 GND
A68 PCIE_TX0+ B68 PCIE_RX0+ C68 PCIE_RX21+ D68 PCIE_TX21+
A69 PCIE_TX0- B69 PCIE_RX0- C69 PCIE_RX21- D69 PCIE_TX21-
A70 GND (fixed) B70 GND (fixed) C70 GND (fixed) D70 GND (fixed)
A71 PCIE_TX8+ B71 PCIE_RX8+ C71 PCIE_RX22+ D71 PCIE_TX22+
A72 PCIE_TX8- B72 PCIE_RX8- C72 PCIE_RX22- D72 PCIE_TX22-
A73 GND B73 GND C73 GND D73 GND
A74 PCIE_TX9+ B74 PCIE_RX9+ C74 PCIE_RX23+ D74 PCIE_TX23+
A75 PCIE_TX9- B75 PCIE_RX9- C75 PCIE_RX23- D75 PCIE_TX23-
A76 GND B76 GND C76 GND D76 GND
A77 PCIE_TX10+ B77 PCIE_RX10+ C77 RSVD D77 RSVD
A78 PCIE_TX10- B78 PCIE_RX10- C78 PCIE_RX24+ D78 PCIE_TX24+
A79 GND B79 GND C79 PCIE_RX24- D79 PCIE_TX24-

Express-BD74
Pinouts and Signal Descriptions 11
Row A Row B Row C Row D
Pin Name Pin Name Pin Name Pin Name
A80 GND (fixed) B80 GND (fixed) C80 GND (fixed) D80 GND (fixed)
A81 PCIE_TX11+ B81 PCIE_RX11+ C81 PCIE_RX25+ D81 PCIE_TX25
A82 PCIE_TX11- B82 PCIE_RX11- C82 PCIE_RX25- D82 PCIE_TX25-
A83 GND B83 GND C83 RSVD D83 RSVD
A84 NCSI_TX_EN B84 VCC_5V_SBY C84 GND D84 GND
A85 GPI3 B85 VCC_5V_SBY C85 PCIE_RX26+ D85 PCIE_TX26+
A86 RSVD B86 VCC_5V_SBY C86 PCIE_RX26- D86 PCIE_TX26-
A87 RSVD B87 VCC_5V_SBY C87 GND D87 GND
A88 PCIE0_CK_REF+ B88 BIOS_DIS1# C88 PCIE_RX27+ D88 PCIE_TX27+
A89 PCIE0_CK_REF- B89 NSCI_RX_ER C89 PCIE_RX27- D89 PCIE_TX27-
A90 GND (fixed) B90 GND (fixed) C90 GND (fixed) D90 GND (fixed)
A91 SPI_POWER B91 NCSI_CLK_IN C91 PCIE_RX28+ D91 PCIE_TX28+
A92 SPI_MISO B92 NCSI_RXD1 C92 PCIE_RX28- D92 PCIE_TX28-
A93 GPO0 B93 NCSI_RXD0 C93 GND D93 GND
A94 SPI_CLK B94 NCSI_CRS_DV C94 PCIE_RX29+ D94 PCIE_TX29+
A95 SPI_MOSI B95 NCSI_TXD1 C95 PCIE_RX29- D95 PCIE_TX29-
A96 TPM_PP B96 NCSI_TXD0 C96 GND D96 GND
A97 TYPE10# B97 SPI_CS# C97 RSVD D97 RSVD
A98 SER0_TX / CAN_TX B98 NCSI_ARB_IN C98 PCIE_RX30+ D98 PCIE_TX30+
A99 SER0_RX / CAN_RX B99 NCSI_ARB_OUT C99 PCIE_RX30- D99 PCIE_TX30-
A100 GND (fixed) B100 GND (fixed) C100 GND (fixed) D100 GND (fixed)
A101 SER1_TX B101 FAN_PWMOUT C101 PCIE_RX31+ D101 PCIE_TX31+
A102 SER1_RX B102 FAN_TACHIN C102 PCIE_RX31- D102 PCIE_TX31-
A103 LID# B103 SLEEP# C103 GND D103 GND
A104 VCC_12V B104 VCC_12V C104 VCC_12V D104 VCC_12V
A105 VCC_12V B105 VCC_12V C105 VCC_12V D105 VCC_12V
A106 VCC_12V B106 VCC_12V C106 VCC_12V D106 VCC_12V
A107 VCC_12V B107 VCC_12V C107 VCC_12V D107 VCC_12V
A108 VCC_12V B108 VCC_12V C108 VCC_12V D108 VCC_12V
A109 VCC_12V B109 VCC_12V C109 VCC_12V D109 VCC_12V
A110 GND (fixed) B110 GND (fixed) C110 GND (fixed) D110 GND (fixed)
Note: LPC and eSPI are muxed in the standard COM Express specification. The Express-BD74 only supports the
LPC bus.

12 Pinouts and Signal Descriptions
3.2. Signal Description Terminology
The following terms are used in the COM Express AB/CD Signal Descriptions below.
I Input to the Module
O Output from the Module
I/O Bi-directional input/output signal
OD Open drain output
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
P Power Input/Output
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module

Express-BD74
Pinouts and Signal Descriptions 13
3.3. AB Signal Descriptions
3.3.1. Network Controller Sideband Interface (NC-SI)
Signal Pin Description I/O PU/PD Comment
NCSI_CLK_IN B91
Clock reference for receive, transmit
and control interface
I 3.3VSB PD 10k
NCSI_RXD[1:0] B92
B93
Receive Data (from NC to BMC) O 3.3VSB PU 10k
3.3VSB
PU 10k that aligns with LAN chip
specification
NCSI_TXD[1:0] B95
B96
Transmit Data (from BMC to NC) I 3.3VSB PU 10k
3.3VSB
NCSI_CRS_DV B94
Carrier Sense/Receive Data valid to
MC, indicating that the transmitted
data from NC to BMC is valid
O 3.3VSB PD 10k PU 10k that aligns with LAN chip
specification
NCSI_TX_EN A84 Transmit enable I 3.3VSB PD 10k
NCSI_RX_ER B89 Receive error O 3.3VSB
NCSI_ARB_IN B98
Network Controller hardware
arbitration input
I 3.3VSB Left floating on module, that
aligns with LAN chip specification
NCSI_ARB_OUT B99 Network Controller hardware
arbitration output
O 3.3VSB
3.3.2. Gigabit Ethernet
Gigabit Ethernet Pin Description I/O PU/PD Comment
GBE0_MDI0+
GBE0_MDI0-
GBE0_MDI1+
GBE0_MDI1-
GBE0_MDI2+
GBE0_MDI2-
GBE0_MDI3+
GBE0_MDI3-
A13
A12
A10
A9
A7
A6
A3
A2
Gigabit Ethernet Controller 0: Media Dependent Interface
Differential Pairs 0, 1, 2, 3. The MDI can operate in 1000,
100, and 10Mbit/sec modes. Some pairs are unused in
some modes according to the following:
1000BASE-T 100BASE-TX 10BASE-T
MDI[0]+/- B1_DA+/- TX+/- TX+/-
MDI[1]+/- B1_DB+/- RX+/- RX+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
I/O
Analog
Twisted pair
signals for
external
transformer.
GBE0_ACT# B2 Gigabit Ethernet Controller 0 activity indicator, active low. O 3.3VSB Shares same
source as A8
GBE0_LINK# A8 Gigabit Ethernet Controller 0 link indicator, active low. O 3.3VSB Shares same
as B2
GBE0_LINK100# A4 Gigabit Ethernet Controller 0 100Mbit/sec link indicator,
active low.
O 3.3VSB
GBE0_LINK1000# A5 Gigabit Ethernet Controller 0 1000Mbit/sec link indicator,
active low.
O 3.3VSB
GBE0_CTREF A14 Reference voltage for Carrier Board Ethernet channel 1
and 2 magnetics center tap. The reference voltage is
determined by the requirements of the Module PHY and
may be as low as 0V and as high as 3.3V. The reference
voltage output shall be current limited on the Module. In
the case in which the reference is shorted to ground, the
current shall be 250 mA or less.
GND min
3.3V max
NC pin
GBE0_SDP A49 Gigabit Ethernet Controller 0 Software-Definable Pins.
Can also be used for IEEE1588 support such as a 1pps
signal.
I/O
3.3VSB
PU 10k
3.3VSB
PU 10k that
aligns with LAN
chip specification

14 Pinouts and Signal Descriptions
3.3.3. SATA
Signal Pin Description I/O PU/PD Comment
SATA0_TX+
SATA0_TX-
A16
A17
Serial ATA channel 0, Transmit
Output differential pair.
O SATA AC coupled on Module
SATA0_RX+
SATA0_RX-
A19
A20
Serial ATA channel 0, Receive Input
differential pair.
I SATA AC coupled on Module
SATA1_TX+
SATA1_TX-
B16
B17
Serial ATA channel 1, Transmit
Output differential pair.
O SATA AC coupled on Module
SATA1_RX+
SATA1_RX-
B19
B20
Serial ATA channel 1, Receive Input
differential pair.
I SATA AC coupled on Module
(S)ATA_ACT# A28 ATA (parallel and serial) or SAS
activity indicator, active low.
O 3.3V PU 4.7K
3.3V
3.3.4. PCI Express
Signal Pin Description I/O PU/PD Comment
PCIE_TX0+
PCIE_TX0-
A68
A69
PCI Express channel 0, Transmit
Output differential pair.
O PCIE AC coupled on Module
PCIE_RX0+
PCIE_RX0-
B68
B69
PCI Express channel 0, Receive
Input differential pair.
I PCIE AC coupled off Module
PCIE_TX1+
PCIE_TX1-
A64
A65
PCI Express channel 1, Transmit
Output differential pair.
O PCIE AC coupled on Module
PCIE_RX1+
PCIE_RX1-
B64
B65
PCI Express channel 1, Receive
Input differential pair.
I PCIE AC coupled off Module
PCIE_TX2+
PCIE_TX2-
A61
A62
PCI Express channel 2, Transmit
Output differential pair.
O PCIE AC coupled on Module
PCIE_RX2+
PCIE_RX2-
B61
B62
PCI Express channel 2, Receive
Input differential pair.
I PCIE AC coupled off Module
PCIE_TX3+
PCIE_TX3-
A58
A59
PCI Express channel 3, Transmit
Output differential pair.
O PCIE AC coupled on Module
PCIE_RX3+
PCIE_RX3-
B58
B59
PCI Express channel 3, Receive
Input differential pair.
I PCIE AC coupled off Module
PCIE_TX4+
PCIE_TX4-
A55
A56
PCI Express channel 4, Transmit
Output differential pair.
O PCIE AC coupled on Module
PCIE_RX4+
PCIE_RX4-
B55
B56
PCI Express channel 4, Receive
Input differential pair.
I PCIE AC coupled off Module
PCIE_TX5+
PCIE_TX5-
A52
A53
PCI Express channel 5, Transmit
Output differential pair.
O PCIE AC coupled on Module
PCIE_RX5+
PCIE_RX5-
B52
B53
PCI Express channel 5, Receive
Input differential pair.
I PCIE AC coupled off Module
PCIE_TX8+
PCIE_TX8-
A71
A72
PCI Express channel 8, Transmit
Output differential pair.
O PCIE AC coupled on Module
PCIE_RX8+
PCIE_RX8-
B71
B72
PCI Express channel 8, Receive
Input differential pair.
I PCIE AC coupled off Module
PCIE_TX9+
PCIE_TX9-
A74
A75
PCI Express channel 9, Transmit
Output differential pair.
O PCIE AC coupled on Module
PCIE_RX9+
PCIE_RX9-
B74
B75
PCI Express channel 9, Receive
Input differential pair.
I PCIE AC coupled off Module