ADLINK Technology VPX3-TL Series User manual

Manual Rev.: 1.1
Revision Date: October 19, 2023
Part No: 50M-31129-1010
VPX3-TL Series
SOSA-aligned Rugged 3U VPX Processor Blade
with Intel®Xeon®W11865MRE
User’s Manual

ii Revision History
Revision History
Revision Release Date Description of Change(s)
1.0 2023-07-05 Initial release
1.1 2023-10-19 Update storage specifications

Preface iii
VPX3-TL
Preface
Copyright © 2023 ADLINK Technology, Inc.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, spe-
cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsi-
bility to global environmental preservation
through compliance with the European Union's
Restriction of Hazardous Substances (RoHS)
directive and Waste Electrical and Electronic
Equipment (WEEE) directive. Environmental
protection is a top priority for ADLINK. We have
enforced measures to ensure that our products,
manufacturing processes, components, and raw
materials have as little impact on the environment as possible.
When products are at their end of life, our customers are encour-
aged to dispose of them in accordance with the product disposal
and/or recovery programs prescribed by their nation or company.
Battery Labels (for products with battery)
ᑜ㔚ᳰ⺧࿁ᡴ

iv Preface
California Proposition 65 Warning
WARNING: This product can expose you to chemicals
including acrylamide, arsenic, benzene, cadmium,
Tris(1,3-dichloro-2-propyl)phosphate (TDCPP), 1,4-Diox-
ane, formaldehyde, lead, DEHP, styrene, DINP, BBP, PVC, and
vinyl materials, which are known to the State of California to cause
cancer, and acrylamide, benzene, cadmium, lead, mercury,
phthalates, toluene, DEHP, DIDP, DnHP, DBP, BBP, PVC, and
vinyl materials, which are known to the State of California to cause
birth defects or other reproductive harm. For more information go
to www.P65Warnings.ca.gov.
Trademarks
Product names mentioned herein are used for identification pur-
poses only and may be trademarks and/or registered trademarks
of their respective companies.
Conventions
Take note of the following conventions used throughout this
manual to make sure that users perform certain tasks and
instructions properly.
NOTE:
NOTE:
Additional information, aids, and tips that help users perform
tasks.
CAUTION:
Information to prevent minor physical injury, component dam-
age, data loss, and/or program corruption when trying to com-
plete a task.
WARNING:
Information to prevent serious physical injury, component
damage, data loss, and/or program corruption when trying to
complete a specific task.

Table of Contents v
VPX3-TL
Table of Contents
Revision History...................................................................... ii
Preface .................................................................................... iii
List of Figures ....................................................................... vii
List of Tables.......................................................................... ix
1 Introduction ........................................................................ 1
1.1 Overview.............................................................................. 1
1.2 Features............................................................................... 2
1.3 Block Diagrams.................................................................... 3
1.4 Model Number Decoder - Processor Blade......................... 4
1.5 Package Contents ............................................................... 5
2 Specifications..................................................................... 7
2.1 VPX3-TL Blade Specifications............................................. 7
2.2 VPX3-TL-RL1 RTM Specifications ...................................... 9
2.3 Power Consumption .......................................................... 10
3 Functional Description .................................................... 11
3.1 Processors......................................................................... 11
3.2 Intel® Turbo Boost Technology......................................... 13
3.3 Chipset............................................................................... 13
3.4 USB ................................................................................... 14
3.5 SPI BIOS ........................................................................... 14
3.6 System Management Bus.................................................. 14
3.7 Real Time Clock ................................................................ 14
3.8 Serial ATA Controller......................................................... 14
3.9 PCI Express Interface........................................................ 14
3.10 Intel ® Gigibit Ethernet Controller I225-IT.......................... 15
3.11 Ethernet for 10GbE............................................................ 15
3.12 Graphics ............................................................................ 15

vi Table of Contents
3.13 GPIO Expander PCA9554................................................. 15
3.14 UART NCT5104D.............................................................. 15
3.15 TPM ................................................................................... 16
3.16 Embedded Controller......................................................... 16
3.17 XMC Site............................................................................ 16
4 VPX3-TL Board Interfaces................................................ 17
4.1 VPX3-TL Board Layout...................................................... 17
4.2 VPX3-TL Mechanical Dimensions ..................................... 19
4.3 VPX3-TL Connector Pin Assignments............................... 20
4.4 Status LEDs....................................................................... 26
5 VPX3-TL-RL1 RTM ............................................................ 27
5.1 Connector Allocation.......................................................... 27
5.2 VPX3-TL-RL1 Block Diagram............................................ 28
5.3 VPX3-TL-RL1 RTM Board Layout ..................................... 29
5.4 VPX3-TL-RL1 RTM Connector Pin Assignments .............. 30
6 Getting Started .................................................................. 35
6.1 Installing the VPX3-TL to the Chassis ............................... 35
6.2 Installing the VPX3-TL-RL1 RTM to the Chassis............... 35
6.3 Driver Installation............................................................... 36
7 Utilities ............................................................................... 41
7.1 SEMA................................................................................. 41
7.2 Watchdog Timer................................................................. 41
8 BIOS Setup ........................................................................ 43
8.1 Starting the BIOS............................................................... 43
8.2 Setup Menus...................................................................... 45
Important Safety Instructions............................................... 47
Getting Service ...................................................................... 49

List of Figures vii
VPX3-TL
List of Figures
Figure 1-1: VPX3-TL Functional Block Diagram................................3
Figure 4-1: VPX3-TL Top Side Layout.............................................17
Figure 4-2: VPX3-TL Bottom Side Layout........................................17
Figure 4-3: VPX3-TL Conduction-Cooled Mechanical Dimensions .19
Figure 4-4: VPX3-TL Front View......................................................26
Figure 5-1: VPX3-TL-RL1 RTM Functional Block Diagram..............28
Figure 5-2: VPX3-TL-RL1 RTM Board Layout.................................29

viii List of Figures
This page intentionally left blank.

List of Tables ix
VPX3-TL
List of Tables
Table 1-1: VPX3-TL SKU Table........................................................4
Table 2-1: VPX3-TL Blade Specifications.........................................7
Table 2-2: VPX3-TL-RL1 RTM Specifications ..................................9
Table 4-1: VPX3-TL Board Layout Legend.....................................18
Table 5-1: VPX3-TL-RL1 RTM Board Layout Legend....................29

x List of Tables
This page intentionally left blank.

Introduction 1
VPX3-TL
1 Introduction
1.1 Overview
The VPX3-TL Series is a 3U VPX processor blade based on the
Intel® Xeon® W11865MRE Processor (formerly "Tiger Lake-H"),
supporting up to 64GB DDR4-2666 soldered ECC memory, 2x
10GBASE-KR or 2x 1GBASE-KX, one XMC expansion slot with
PCIe x8 Gen3 to P1 & P2 rear I/O, USB 3.0 and SATA 6GB/s; as
well as a high performance NVMe/SATA M.2 slot for storage
expansion up to 1TB (by BOM option). The SOSA-aligned design
offers embedded computing capabilities that are easily reconfigu-
rable and upgradable, highly cost-effective, and quick to develop
and deploy.
The VPX3-TL Series with work station grade Intel® processor
brings high-bandwidth, high-powered computing and artificial intel-
ligence to demanding applications that expose hardware to
extreme temperatures, vibration, and operating conditions.
Interoperability between different systems - including Command,
Control, Communications, Computers, Intelligence, Surveillance
and Reconnaissance (C4ISR), electronic warfare (EW), signals
intelligence (SIGINT), cognitive radio and radar - is critical. The
SOSA standard is one of several standards that fall broadly within
the MOSA initiative. SOSA centers on key interfaces and open
standards, based on the VPX standard (VITA 46/48/65), and aims
to develop a common, modular hardware architecture across
next-generation, mission-critical applications.

2 Introduction
1.2 Features
XIntel® Xeon® W11865MRE Processor (formerly “Tiger
Lake-H”); up to 8 cores with 45 watt TDP
XSOSA-aligned and VITA 46/47/48/65 compliant for quick
deployment
X32GB DDR4-2666 soldered ECC SDRAM (roadmap to 64GB)
XSupports NVMe and SATA SSD up to 1TB (by BOM option)
XOne XMC expansion slot with PCIe x8 Gen3
XEthernet connectivity: 1x 2.5GBASE-T to P2; 2x
10GBASE-KR to P1; optional 2x 1GBASE-KX to P1
X1x DisplayPort to P2, supports DP++ with resolution up to
8K/60Hz

Introduction 3
VPX3-TL
1.3 Block Diagrams
Figure 1-1: VPX3-TL Functional Block Diagram
3.3V
3.3V
UARTA
(COM5)
P0
EC
IT5121
IPMC
IPMB
SIO
NCT5104D
UARTB
(COM2)
UARTD
(COM4)
LPC
UARTC
(COM3)
BIOS1
BIOS2
SPI
TPM
MUX
FLEXI/O[6:9]
FLEXI/O[26:29]
PCIex4 Gen3
PCIex4 Gen3
IT5121
EC
TCP0
GPIO[2:4]
RS232
RS232/422/485
ISL41334
USB 2.0 x2
Tranceiver
DMI[0:7]
Intel®Xeon®
WͲ11000E
2.5GBASEͲT
SATA 6Gb/s
PCIe3.0orSATA6Gb/s
Maintenanceport(COM1)
Intel®RM590E
Chipset
USB2[1:2]
FLEXI/O[0]
M.22242
MKey
DisplayPort
eSPI
DDR4ChB
DDR4320016GBMaxwECC
P2
DMI
XMC
J15
eSPI
DDR4ChA
DDR4320016GBMaxwECC
P1
FLEXI/O[14:21]
FLEXIO[22]
ECE1200
eSPItoLPC
SPI0
PCIex4 Gen3
PCIex4 Gen3
10GBASEͲKR x2
Intel ®I225
PCIex1 Gen3
FLEXIO[10:13]
2.5GLAN
UART0
Intel®X710ͲBM2
DP_CONFIG
10GLAN
GPIO1
X12d
XMC
J16
X16s XMC
J16
USB 3.2Gen1x1
FLEXI/O[24]
FLEXI/O[30:33]
Reserved Circuit
IPMC
IPMC
PCIE16[8:11]
PCIE16[12:15]
PCIE16[0:7]
X8d
PCIex4 Gen3
PCIex4 Gen3

4 Introduction
1.4 Model Number Decoder - Processor Blade
(A) CPU Code
ZW11865MRE = Intel® Xeon® W11865MRE Processor,
8 cores, 45W TDP
(B) Memory Size Code
ZM32 = 32GB DDR4-2666 ECC soldered SDRAM
(C) PCI Express interface code
ZXMC1.0 = XMC 1.0 interface, 2x PCIe x4 Gen3 to P1
ZXMC2.0 = XMC 2.0 interface, 2x PCIe x4 Gen3 to P1
ZP16 = 2x PCIe x4 Gen3 to P1 + 2x PCIe x4 Gen3 to P1
(D) Ruggedized Level Code
ZR2 = Conduction Cooled version supporting -40°C to
+85°C at card edge
VPX3-TL SKU Table
Function XMC1.0 XMC2.0 P16
XMC
1.0 connector for
expansion
X16s+X8d to P2 and
X12d to P1
2.0 connector for
expansion
X16s+X8d to P2 and
X12d to P1
N/A
PCIe 2x PCIe x4 Gen3 to P1 2x PCIe x4 Gen3 to P1 2x PCIe x4 Gen3 to P1
2x PCIe x4 Gen3 to P2
Table 1-1: VPX3-TL SKU Table
(D)
(A) (B) (C)
VPX3-TL/W11865MRE/M32/XMC1.0-R2

Introduction 5
VPX3-TL
1.5 Package Contents
The VPX3-TL is packaged with the following components. If any of
the items on the contents list are missing or damaged, retain the
shipping carton and packing material and contact the dealer for
inspection. Please obtain authorization before returning any prod-
uct to ADLINK. The packing contents of the VPX3-TL are
non-standard configurations and may vary depending on customer
requests.
Processor Blade
XVPX3-TL
ZCPU and memory specifications will differ depending on
options selected
ZThermal module is assembled on the board
Rear Transition Module (optional)
XVPX3-TL-RL1 RTM
Test Backplane (optional)
XtBP-VPX3-TL test backplane
NOTE:
NOTE:
The contents of non-standard VPX3-TL configurations may vary
depending on the customer requirements.
CAUTION:
This product must be protected from static discharge and physi-
cal shock. Never remove any of the components except at a
static-free workstation. Use the anti-static bag shipped with the
product when putting the board on a surface. Wear an anti-static
wrist strap properly grounded on one of the system's ESD ground
jacks when installing or servicing system components.

6 Introduction
This page intentionally left blank.

Specifications 7
VPX3-TL
2 Specifications
2.1 VPX3-TL Blade Specifications
VITA
Standards
• VITA 46, 47, 48, 65 compliant
• SOSA aligned
Module Profile • MOD3-PAY-1F1F2U1TU1T1U1T-16.2.15-2
Slot Profile • SLT3-PAY-1F1F2U1TU1T1U1T- 14.2.16
Processor • Intel® Xeon® W11865MRE, up to 8 cores, 45W TDP
Chipset • Intel® RM590E Chipset
Memory • 32GB DDR4 soldered with ECC (roadmap to 64GB)
USB • 2x USB 2.0 to P2
• 1x USB 3.2 Gen1 to P2
• Supports USB 3.0 power to P1/G7 (supply 0.9A) with over
current protection
• Supports USB 2.0 power to P2/G9 (supply 0.5A) with over
current protection
XMC • 1x PCIe x8 to J15
• Rear I/O (X16s + X8d) to P2 and X12d to P1 from J16
Gigabit
Ethernet
• 1x 2.5GBASE-T to P2 supporting PXE and Wake on LAN
(WOL)
PCI Express • 2x PCIe x4 co-layout with XMC X8d+X16s on P2
(PCIe NT function not supported)
Storage • 1x M2. 2242 onboard (M-Key), supports NVMe and SATA
• 1x SATA 6Gb/s to P2
• M.2 devices supporting spec S1, S2, S3, D1, D2, D3, D4
• M.2 capacity up to 1TB
Graphics • 1x DisplayPort to P2
• Resolution up to 8K/60Hz
• Supports passive DP to HDMI dongle with BIOS selection
GPIO • 1x GPIO to P1
• 3x GPIO to P2
• Supports +3.3V (default) or +5V GPIO (BOM option)
• GPI with edge trigger or level trigger interrupt
Table 2-1: VPX3-TL Blade Specifications

8 Specifications
Note: Specifications are subject to change without prior notice.
Serial COM1:
• 2-wire TX/RX on P1 supporting TIA-232 & LVCOMS
(3.3V) mode selected by BIOS option
COM2:
• 1x RS-232/422/485 to P2 (RS232, 2-wire)
• Max. data rate for RS232/422/485 is 115200bps
• RS485 mode supports auto flow control
• RS232/422/485 mode selected by BIOS option
COM3:
• 1x RS-232 to P2 (2-wire, available when COM2 is set
RS232
TPM • Discrete TPM 2.0 chip
• Supports Intel Secure Boot (UEFI)
LEDs • Power and SATA Activity LEDs on front panel
• Reserved LED (for customer definition)
• Embedded Controller Status LED on front panel
Reset Button • On front panel
Watchdog
Timer
• Provided by SEMA
Environmental Operating Temp. -40°C to +85°C at wedge locks (VITA47.0,
ECC4-CC4)
Storage Temp: -55°C to +105°C
Vibration:
• Random: 12Grms, 5Hz to 2000Hz (VITA47.0, ECC4-V3)
• Sinusoidal: 5g, 20Hz to 2000Hz
Shock: 40g, 11 ms (VITA47.0, ECC4-OS2)
Relative Humidity: 95% non-condensing
Altitude: 60,000 ft. (operating)
EMC • CE (EN555032 / EN55035) ; FCC Part 15B Class A
Table 2-1: VPX3-TL Blade Specifications

Specifications 9
VPX3-TL
2.2 VPX3-TL-RL1 RTM Specifications
Note: Specifications are subject to change without prior notice.
Ethernet • 2x 10GBASE-KR via RP1
• 1x 2.5GBASE-T via RP1
Graphics • 1x DisplayPort signal via RP1
SATA • 1x SATA 6Gb/s via RP1 (7-pin vertical SATA connector)
USB • 1x USB 3.0 (backwards compatible) via RP1
Serial • Serial Port 1: RS232 (2T2R) via RP1 (DB-9 connector)
• Serial Port 2: RS232 (2T2R) via RP2 (2x5 pin header)
GPIO • 1 bit GPIO signal via RP1, 3 bits GPIO signals via RP2
PCIe • 1x PCIe x4 via RP0
• 2x PCIe x4 via RP1
• 2x PCIe x4 via RP2
XMC • X12D via RP1
• X8D via RP2
• X16S via RP2
JTAG • JTAG via RP0 (2x5 pin header)
Reset • Reset via RP0
SMBus • SMBus signal via RP0
Power • Power terminal for +12V, +5V, +3.3V, GND
Table 2-2: VPX3-TL-RL1 RTM Specifications

10 Specifications
2.3 Power Consumption
This section provides information on the power consumption of the
VPX3-TL when using the Intel® Xeon® W-11865MRE processor
with Dual Channel 16GB DDR4-2666 soldered memory. The
VPX3-TL is powered by 12V. Windows 10 idle mode power con-
sumption was measured running BurnInTest at 100% loading.
Windows 10 Max Loading power consumption was measured run-
ning Intel TAT test at 100% loading.
Processor Xeon® W-11865MRE (2.6 GHz)
Windows Idle mode, EIST Enabled
12V (A) 2.55
Power Cons. (W) 32.48
Windows Idle mode, EIST Disabled
12V (A) 2.53
Power Cons. (W) 32.17
Windows Max Loading mode, EIST Enabled
Package Power reading (TAT) 49.86
Package Temperature reading (TAT) 88
CPU DTS reading (TAT) 87
CPU frequency reading (TAT) 2867
12V (A) 6.64
Power Cons. (W) 81.83
Windows Max Loading mode, EIST Disabled
Package Power reading (TAT) 45.72
Package Temperature reading (TAT) 83
CPU DTS reading (TAT) 82
CPU frequency reading (TAT) 2600
12V (A) 6.28
Power Cons. (W) 77.26