Advantech AIW-357 DK-G1P User manual

AIW-357 DK-G1P
User Manual

Applicability Type
AIW PN
MPN
Description
AIW-357 DK-G1P
XS5G03-GBO
MediaTek T700 NR SUB6/LTE FDD/LTE
TDD/WCDMA M.2 3052 module B key, W/O SIM
holder; w/o voice function; Only PCIe
communication interface, for USA, Europe, Japan
and Taiwan region

3
Revision History
Version
Date
Description
V1.0
2023-06-07
First issue
V1.1
2023-07-10
Section 2.10 edit LED Signal picture
V1.2
2023-08-23
1. Add Section 2.1 pin map schematic
2. Add Section 5.1 Product picture
3. Add Section 2.6.1~2.6.3 USIM N.C./ N.O. description

4
1 Overall Description
1.1 Function Overview
Features
Description
Dimensions
(L × W × H): 52 mm × 30 mm × 2.4 mm (Max)
Weight
8.7g
Voltage
3.135V ~3.63V, typical 3.3V
Operating Temperature
-30 ~ 70℃
Operating Humidity
less than 85% R.H.
Storage Temperature
-40 ~ 85℃
Storage Humidity
less than 60% R.H.
Extend Temperature
-30 ~ 80℃
Table 1-1 Features
Note:
Thermal solutions are necessary to be put on module, so that module can work smoothly
in operating temperature range. For example, thermal pad, heat sink, fan.
1.2 Product Specification and Frequency Bands
AIW-357 DK-G1P is standard version with GPS function.
Cellular
Item
AIW-357 DK-G1P
5G NR
Standard
3GPP Release 15
SA Bands
n1/2/3/5/7/8/20/25/28/30/38/40/41/48/66/71/ 77/78/79
NSA Bands
n1/2/3/5/8/20/28/38/41/66/71/77/78/79
Sub-6 CA
FDD/TDD+FDD/TDD DL CA*
DL 4x4 MIMO
n1/2/3/7/25/30/38/40/ 41/48/66/77/78/79
UL 2x2 MIMO
n41/77/78/79

5
Model
AIW-357 DK-G1P
4G LTE
LTE Category
Cat 12
LTE Bands
B1/2/3/4/5/7/8/12/13/14/17/18/19/20/25/26/
28/29/30/32/34/38/39/40/41/42/43/46/48/66/71
DL CA
4x4 MIMO, 3CC
UL CA
2CC
3G
UMTS/
WCDMA
Bands
B1/2/4/5/8
GPS
UL 2x2 MIMO
GPS/GLONASS/BeiDou/ Galileo
Frequency Band
L1
Table 1-2 Product Specification and Frequency Bands
1.3 Circuit Block Diagram
The circuit block diagram is shown in Figure 1-1.
The major functional units are listed below:
Power Management
Baseband Controller
MCP (4Gb LPDDR4X+4Gb Nand Flash)
RF Circuit
eSIM (option)

6
Figure 1-1 Circuit block diagram of the module

7
1.4 Application Interface
Features
Description
External Power Supply:
DC 3.3V Typical
PCIe Interface:
PCIE3.0 1L × 1
Audio Interface:
I2S x 1
I2C Interface:
I2C × 1
USIM Interface:
USIM × 1, eSIM x 1 (optional)
RF Ipex4 connector:
RF Ipex4 connector × 4
Table 1-3 Application Interface
2 Description of the Application Interfaces
2.1 M.2 Key B Interface

8
Pin No.
AIW-357 DK-G1P M.2 module uses standard key B interface
Pin No.
74
+3.3V
CONFIG_2 (GND)
75
72
+3.3V
VIO_CFG
73
70
+3.3V
GND
71
68
NC
CONFIG_1 (GND)
69
66
SIM Detect (I) (1.8V)
RESET# (I) (1.8V)
67
64
COEX1 (IO) (1.8V)
ANTCTL3 (O) (1.8V)
65
62
COEX2 (IO) (1.8V)
ANTCTL2 (O) (1.8V)
63
60
COEX3 (IO) (1.8V)
ANTCTL1 (O) (1.8V)
61
58
MIPI2_D_SDATA (IO) (1.8V)
ANTCTL0 (O) (1.8V)
59
56
MIPI2_D_SCLK (O) (1.8V)
GND
57
54
PEWAKE# (IO) (3.3/1.8V)
REFCLKP
55
52
CLKREQ# (IO) (3.3/1.8V)
REFCLKN
53
50
PERST# (IO) (3.3/1.8V)
GND
51
48
NC
PERp0
49
46
NC
PERn0
47
44
I2C_IRQ# (I) (1.8V)
GND
45
42
I2C_SDA (IO) (1.8V)
PETp0
43
40
I2C_SCL (O) (1.8V)
PETn0
41
38
NC
GND
39
36
USIM1_PWR (O)
NC
37
34
USIM1_DATA (IO)
NC
35
32
USIM1_CLK (O)
GND
33
30
USIM1_RESET (O)
NC
31
28
I2S0_LRCK (IO) (1.8V)
NC
29
26
W_DISABLE2# (I) (3.3/1.8V)
GND
27
24
I2S0_DO (O) (1.8V)
DPR (I) (1.8V)
25
22
I2S0_DI (I) (1.8V)
WOWWAN# (IO) (1.8V)
23
20
I2S0_BCK (IO) (1.8V)
CONFIG_0 (GND)
21
Notch
Notch

9
Notch
Notch
Notch
Notch
Notch
Notch
10
LED1# (O) (3.3V)
GND
11
8
W_DISABLE1# (I) (3.3/1.8V)
NC
9
6
FULL_CARD_POWER_OFF# (I)
(3.3/1.8V)
NC
7
4
+3.3V
GND
5
2
+3.3V
GND
3
CONFIG_3 (NC)
1
Figure 2-1 AIW-357 DK-G1P Pin Map

10
Pin
Pin Name
Description
Voltage
Type
1
CONFIG_3
Setting vale: NC
NC
DO
The interface of AIW-357 DK-G1P
module is configured as the WWAN –
PCIe Gen3,
2
+3.3V
Power supply for Module
3.135-3.63V
PI
3
GND
Module ground pin
4
+3.3V
Power supply for Module
3.135-3.63V
PI
5
GND
Module ground pin
6
FULL_CARD
Pull high to 1.4V~module input
3.3/ 1.8V
DI
_POWER_OFF#
voltage to enable power of the module
7
NC
No connection pin
8
W_DISABLE1#
The pin use for WWAN disable,
3.3/ 1.8V
DI
active low
9
NC
No connection pin
AIO
10
LED1#
Open drain, active low signal.
3.3V
DO
The signal is used to allow the add-in
card to provide status indicators
via LED devices that will be provided
by the system.
11
GND
Module ground pin
12
Notch
Notch
13
Notch
Notch
14
Notch
Notch
15
Notch
Notch
16
Notch
Notch
17
Notch
Notch
18
Notch
Notch
19
Notch
Notch

11
Pin
Pin Name
Description
Voltage
Type
20
I2S0_BCK
I2S interface
1.8V
DIO
21
CONFIG_0
Setting vale: GND
0V
DO
The interface of AIW-357 DK-G1P
module is configured as the WWAN –
PCIe Gen3, USB3.1 Gen1
22
I2S0_DI
I2S interface
1.8V
DI
23
WOWWAN#
Used to wake the platform by the WWAN
1.8V
DIO
device
24
I2S0_DO
I2S interface
1.8V
DO
25
DPR
This signal is an input directly to the
1.8V
DI
WWAN module from a suitable SAR
sensor. The specific implementation
will be determined by the module
vendor and their customer
26
W_DISABLE2#
The pin use for GNSS disable, active low,
3.3V/ 1.8V
DI
reserved
27
GND
Module ground pin
28
I2S0_LRCK
I2S interface
1.8V
DIO
29
NC
No connection pin
30
USIM1_RESET
USIM1 card reset pin
1.8V/ 3V
DO
31
NC
No connection pin
32
USIM1_CLK
USIM1 card clock pin
1.8/3V
DO
33
GND
Module ground pin
34
USIM1_DATA
USIM1 card data pin
1.8/3V
DIO
35
NC
No connection pin
36
USIM1_PWR
USIM1 Power Supply
1.8/3V
PO
37
NC
No connection pin

12
Pin
Pin Name
Description
Voltage
Type
38
NC
No connection pin
39
GND
Module ground pin
40
I2C_SCL
I2C clock
1.8V
DO
41
PETn0
PCIE interface
1.8V
AO
42
I2C_SDA
I2C data
1.8V
DIO
43
PETp0
PCIE interface
1.8V
AO
44
I2C_IRQ#
I2C interrupt request
1.8V
I
45
GND
Module ground pin
46
NC
No connection pin
47
PERn0
PCIE interface
1.8V
AIO
48
NC
No connection pin
49
PERp0
PCIE interface
1.8V
AIO
50
PERST#
PCIE interface, active low
3.3/1.8V
IO
51
GND
Module ground pin
52
CLKREQ#
PCIE interface
3.3/1.8V
DIO
53
REFCLKN
PCIE interface
1.8V
AO
54
PEWALE#
PCIE interface, active low
3.3/1.8V
DO
55
REFCLKP
PCIE interface
1.8V
AO
56
MIPI2_D_SCLK
MIPI interface for antenna tuner
1.8V
DO
57
GND
Module ground pin
58
MIPI2_D_SDATA
MIPI interface for antenna tuner
1.8V
DO
59
ANTCTL0
Antenna tuning interface
1.8V
DO
60
COEX3
Connsys Co-Ex interface
1.8V
DIO

13
Pin
Pin Name
Description
Voltage
Type
61
ANTCTL1
Antenna tuning interface
1.8V
DO
62
COEX2
Connsys Co-Ex interface
1.8V
DIO
63
ANTCTL2
Antenna tuning interface
1.8V
DO
64
COEX1
Connsys Co-Ex interface
1.8V
DIO
65
ANTCTL3
Antenna tuning interface
1.8V
DO
66
SIM Detect
USIM1 card detect pin
1.8V
DI
67
RESET#
Module reset input pin
1.8V
DI
68
NC
No connection pin
69
CONFIG_1
Setting vale: GND
0V
DO
The interface of AIW-357 DK-G1P
module is configured as the WWAN –
PCIe Gen3, USB3.1 Gen1
70
+3.3V
Power supply for Module
3.135-3.63V
PI
71
GND
Module ground pin
72
+3.3V
Power supply for Module
3.135-3.63V
PI
73
VIO_CFG
Setting vale: NC
0V/NC
DO
NC (PCIE SIDEBAND 1.8V TOLERANT
3.3V) GND (PCIE SIDEBAND 3.3V)
74
+3.3V
Power supply for Module
3.135-3.63V
PI
75
CONFIG_2
Setting vale: GND
0V
DO
The interface of AIW-357 DK-G1P
module is configured as the WWAN –
PCIe Gen3, USB3.1 Gen1
Table 2-1 Definitions of the pins on the M.2 interface

14
Note:
Pindicates power pins; PI indicates input power pins; PO indicates output power pins; AI
indicates pins for analog signal input; AO indicates pins for analog signal output; AIO
indicates pins analog bidirectional, DI indicates pins for digital signal input; DO indicates
pins for digital signal output; DIO indicates pins digital bidirectional.

15
2.2 Power Interface
+3.3V pins (pin 2,4,70,72,74) are the power supply for the module
The recommended +3.3V power supply circuit is shown in the figure blow:
Figure 2-2 power supply recommend circuit
When power source voltage lower than 3.135V, the module may shutdown or restart.
The +3.3V power supply range of the module is from 3.135 V to 3.63 V.
The voltage must not be lower than 3.135V, and the voltage ripple should be less than
100 mV.

16
The following figure shows the voltage drop during Tx burst transmission
Figure 2-3 power voltage lower than 3.135V
The power consumption data of AIW-357 DK-G1P module under 3.3V power supply is
2.26A (Max.).
Input power (V)
Current avg (A)
Current max (A)
Condition
3.3
0.50
2.26
DC 7A_n78A
Table 2-2 Definitions of the un-used pins
USIM1_PWR pin is external USIM card power supply, which can provide 1.8 V or 3.0V power
for the USIM card.

17
2.3 Control Signal Interface
Pin 6 FULL_CARD_POWER_OFF#
FULL_CARD_POWER_OFF# Pin Function: When module off, pull high this pin then
the Module booting
FULL_CARD_POWER_OFF# =0→1: PMIC inside the module sequence power on
FULL_CARD_POWER_OFF# =1 →0: PMIC inside the module sequence power off
FULL_CARD_POWER_OFF# Pin Spec.
VIH: ≥ 1.4V
VIL: ≤ 0.7V
De-bounce time: ≤0.31ms
Recommend FULL_CARD_POWER_OFF#=1.8V.
Figure 2-4 Control Signal Interface of PIN 6

18
Pin 67 RESET#
RESET# Function: The RESET# pin is hardware reset pin used to reset the system
of module.
Active Low
PU current: 5uA
VIH: 1.45V
VIL: 0.3V
De-bounce time: ≤0.25ms
Layout notice
RESET# need to keep far from noise trace. If it is possible, please adding “GND”
shielding to avoid noise coupled.
Figure 2-5 Control Signal Interface of PIN 67

19
2.3.1. M.2 Module Timing Note
2.3.1.1. Normal Boot
Figure 2-6 Normal boot module timing
2.3.1.2. Reboot (Power off Power on)
Figure 2-7 Reboot module timing

20
2.4 PCIE Interface
The blow table is PCIe interface pin definition:
Pin
Pin Name
Pad Type
Description
Type. (V)
41
PETn0
AO
PCIE Tx -
43
PETp0
AO
PCIE Tx +
47
PERn0
AI
PCIE Rx-
49
PERp0
AI
PCIE Rx+
53
REFCLKN
AI
PCIE Reference Clock -
55
REFCLKP
AI
PCIE Reference Clock +
50
PERST#
DI
PCIe Reset is a functional reset to the card
3.3/1.8V
as defined by the PCI Express Base
specification.
52
CLKREQ#
DIO
PCIe Clock Request is a reference clock
3.3/1.8V
request signal as defined by the PCI Express
Base Specification. This signal is also used by
L1 PM Substates. Open Drain with pull up on
Platform. Active Low.
54
PEWAKE#
DIO
PCIe WAKE#. Open Drain with pull up on
3.3/1.8V
Platform. Active Low when used as
PEWAKE#. When the Adapter supports
wakeup, this signal is used to request
that the system return from a sleep/suspend
state to service a function initiated wake event.
When the Adapter supports OBFF
mechanism, the PEWAKE# signal is used
for OBFF signaling.
Table 2-2 Definitions PCIe interface