AKM AKD4128A-A User manual

[AKD4128A-A]
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GENERAL DESCRIPTION
The AKD4128A-A is an evaluation board for AK4128A, the digital sample rate converter. The
AKD4128A-A has the digital audio interface and can achieve the interface with digital audio system via
optical or coaxial connector.
Ordering guide
AKD4128A-A --- AK4128A Evaluation Board
FUNCTION
•DIR/DIT with optical or coaxial input/output
•10pin Header for AKM AD/DA evaluation board
O pt In AK4114
(
DIR
)
10pin
Header
＋5VGND
OptOutAK4114
(
DIT
)
10pin
Header
AK4128A
COAX Regulator
COAX
O pt In AK4114
(
DIR
)
10pin
Header
COAX
O pt In AK4114
(
DIR
)
10pin
Header
COAX
O pt In AK4114
(
DIR
)
10pin
Header
COAX
DVDDAVDD
Regulator
Regulator
D3.3V-1 D3.3V-2
10pin
Header
(
I2
C)
Figure 1. AKD4128A-A Block Diagram
*Circuit diagram and PCB layout are attached at the end of this manual.
AK4128A-A Evaluation Board Rev.0
AKD4128A-A

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Operation sequence
1) Set up the power supply lines.
Name of
jack Color of jack Typ Voltage Used for Open / Connect Default Setting
+5V Orange +5V
Regulator T1,T2,T3:
AVDD and DVDD of
AK4128A, AK4114, Digital
Logic
Should be always connected
When default setting. +5V
AVDD Red +3.3V AVDD of AK4128A
Should be always connected
when AVDD of AK4128A is not
supplied from regulator T1.
In this case “JP1” is set to “AVDD”
side.
Open
DVDD Red +3.3V DVDD of AK4128A
Should be always connected
when DVDD of AK4128A is not
supplied from regulator T1.
In this case “JP2” is set to
“DVDD” side.
Open
D3.3V-1 Red +3.3V AK4114, Digital Logic
Should be always connected
when AK4114 and Digital Logic is
not supplied from regulator T2.
In this case “JP3” is set to
“D3.3V-1” side.
Open
D3.3V-2 Red +3.3V AK4114, Digital Logic
Should be always connected
when AK4114 and Digital Logic is
not supplied from regulator T3.
In this case “JP4” is set to
“D3.3V-2” side.
Open
GND Black 0V Ground Should be always connected GND
Table 1. Set up the power supply lines
Each supply line should be distributed from the power supply unit.

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2) Set up the jumper pin of power supply unit.
(1).Setup the AVDD of AK4128A.
a).When using AVDD jack. b).When using Regulator.
AVDD-SEL
JP1
AVDD REG
3
AVDD-SEL
JP1
AVDD REG
3
(2).Setup the DVDD of AK4128A.
a).When using DVDD jack. b).When using Regulator.
DVDD-SEL
JP2
REG DVDD
3
DVDD-SEL
JP2
REG DVDD
3
(3).Setup the D3.3V-1(AK4114 and Digital Logic).
a).When using D3.3V-1 jack. b).When using Regulator.
D3.3V-1 SEL
JP3
D3.3V-1 REG
3
D3.3V-1 SEL
JP3
D3.3V-1 REG
3
(4). Setup the D3.3V-2(AK4114 and Digital Logic).
a).When using D3.3V-2 jack. b).When using Regulator.
D3.3V-2 SEL
JP4
REG D3.3V-2
3
D3.3V-2 SEL
JP4
REG D3.3V-2
3

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3) Set up the evaluation mode, jumper pins. (See the followings.)
(1). Setting for Input port
(1)-1. When using DIR function of AK4114 (U2,U3,U4 and U5)
(1)-2. When using all clocks are fed through the 10pin port
(2). Setting for Output port
(2)-1. When using DIT function of AK4114 (U6)
(2)-2. When using all clocks are fed through the 10pin port(PORT5).
(3). Other jumper pins setup.
4) Power on.
The AK4128A should be reset once bringing SW2 (PDN) “L” upon power-up.

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Set up the evaluation mode, jumper pins.
(1). Setting for Input port
(1)-1. When using DIR function of AK4114 (U2,U3,U4 and U5)
When using J1-4(COAX) and PORT6-9(OPT), nothing should be connected to PORT1-4.
(1)-1-1. Setup the RX.
(a) Select to Optical jack (Default) (b) Select to BNC jack
INPUTx SEL
BNC OPT
3INPUTx SEL
BNC OPT
3
*"x" contains a number (1 - 4).
(1)-1-2. Setup the IBICK1-4, ILRCK1-4 and SDTI1-4.
When using J1-4(COAX) and PORT6-9(OPT), nothing should be connected to PORT1-4.
IBICKx SDTIxILRCKx
IMCLK-SEL
JP27
EXT
DSP1
DIR
2 ６
５
*"x" contains a number (1 - 4).

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(1)-1-3. Setup the SDTI1, SDTI2, SDTI3 and SDTI4.
Select to input signal for SDTI1, SDTI2, SDTI3 and SDTI4 of AK4128A(U1).
(a). When using “Synchronous Mode” (INAS pin = “L”). (Default)
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5 6
2
5 6
2
5 6
2
5 6
(b).When using “Asynchronous Mode” (INAS pin = “H”).
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5 6
2
5 6
2
5 6
2
5 6
(c). Connect to GND.
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5 6
2
5 6
2
5 6
2
5 6

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(1)-2. When using all clocks are fed through the 10pin port
(1)-2-1. Setup the RX.
When using PORT1-4, nothing should be connected to J1-4 (COAX) and PORT6-9 (OPT).
(1)-2-2. Setup the IBICK1-4, ILRCK1-4 and SDTI1-4.
When using PORT1-4, nothing should be connected to J1-4 (COAX) and PORT6-9 (OPT).
IBICKx SDTIxILRCKx
IMCLK-SEL
JP27
EXT
DSP1
DIR
2 ６
５
*"x" contains a number (1 - 4).
(1)-2-3. Setup the SDTI1, SDTI2, SDTI3 and SDTI4.
Select to input signal for SDTI1, SDTI2, SDTI3 and SDTI4 of AK4128A(U1).
(a). When using “Synchronous Mode” (INAS pin = “L”). (Default)
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5 6
2
5 6
2
5 6
2
5 6
(b).When using “Asynchronous Mode” (INAS pin = “H”).
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5 6
2
5 6
2
5 6
2
5 6
(c). Connect to GND.
SDTI1-SEL
JP5
A
synchronous
Synchronous
GND
SDTI2-SEL
JP6
A
synchronous
Synchronous
GND
SDTI3-SEL
JP7
A
synchronous
Synchronous
GND
SDTI4-SEL
JP8
A
synchronous
Synchronous
GND
2
5 6
2
5 6
2
5 6
2
5 6

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(2). Setting for Output port
(2)-1. When using DIT function of AK4114 (U6)
(2)-1-1. Setup the TX.
(a) Select to Optical jack (Default) (b) Select to BNC jack
OUTPUT SEL
JP44
3
BNC OPT
OUTPUT SEL
JP44
BNC OPT
3
(2)-1-2. Setup the TXI.
Select to input signal for XTI/OMCLK pin of AK4128A(U1) and XTI pin of AK4114(U6).
(a) When using X’Tal(X1). In this case, X’Tal(X2) is “open”.
JP5
2
EXT-CLK
DIT-OMCKO SEL
JP51
3
2 4
AK4128
EX
T
JP45
DIT-OMCLK SEL
DIT
DSP5
EXT
2
5 6
JP53
SEL3
3
GND
OMCLK
JP20
MCKO
(b) When using X’Tal(X2). In this case, X’Tal(X1) is “open”.
JP5
2
EXT-CLK
DIT-OMCKO SEL
JP51
3
2 4
AK4128
EXT
JP45
DIT-OMCLK SEL
DIT
DSP5
EXT
2
5 6
JP53
SEL3
3
GND
OMCLK
JP20
MCKO
(c) When using J8(EXT-CLK). In this case, X’Tal(X1 and X2) is “open”.
JP5
2
EXT-CLK
DIT-OMCKO SEL
JP51
3
2 4
AK4128
EXT
JP45
DIT-OMCLK SEL
DIT
DSP5
EXT
2
5 6
JP53
SEL3
3
GND
OMCLK
JP20
MCKO

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(2)-1-3. Setup the OBICK, OLRCK and SDTO.
(2)-1-3-1.When using OBICK, OLRCK of AK4114(U6), and SDTO of AK4128A(U1).
JP48
OBICK JP49 SDTO
JP50
OLRCK
JP46
DIT-OBICK SEL JP47 DIT-OLRCK SEL
DIT-Slave
DIT-Master DIT-Slave DIT-Master
2
3 4
2
3 4
JP18
AK4128-OBICK SEL JP19 AK4128-OLRCK SEL
A
K4128-Slave
A
K4128-Master
A
K4128-Slave
A
K4128-Master
2
3 4
2
3 4
(2)-1-3-2.When using OBICK, OLRCK and SDTO of AK4128A(U1).
JP48
OBICK JP49 SDTO
JP50
OLRCK
JP46
DIT-OBICK SEL JP47 DIT-OLRCK SEL
DIT-Slave
DIT-Master DIT-Slave DIT-Master
2
3 4
2
3 4
JP18
AK4128-OBICK SEL JP19 AK4128-OLRCK SEL
A
K4128-Slave
A
K4128-Master
A
K4128-Slave
A
K4128-Master
2
3 4
2
3 4

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(2)-1-4. Selection of SDTO1, SDTO2, SDTO3 and SDTO4.
(a) Select to SDTO1(b)Select to SDTO2 (c)Select to SDTO3 (d)Select to SDTO4
SDTO-SEL
JP17
2
3
4
2
７ ８
SDTO
1
SDTO-SEL
JP17
2
3
4
2
７ ８
SDTO
1
SDTO-SEL
JP17
2
3
4
2
７ ８
SDTO
1
SDTO-SEL
JP17
2
3
4
2
７ ８
SDTO
1
(2)-2. When using all clocks are fed through the 10pin port(PORT5).
(2)-2-1.Setup TX.
As Optical connector:PORT10(OPT) and BNC connector:J5(COAX) are not used, please don’t
connect anything.
(2)-2-2. Setup the OBICK, OLRCK and SDTO.
(2)-2-2-1. When using OBICK and OLRCK of 10pin port, and SDTO of AK4128A(U1).
JP48
OBICK JP49 SDTO
JP50
OLRCK
JP46
DIT-OBICK SEL JP47 DIT-OLRCK SEL
DIT-Slave
DIT-Master DIT-Slave DIT-Master
2
3 4
2
3 4
JP18
AK4128-OBICK SEL JP19 AK4128-OLRCK SEL
A
K4128-Slave
A
K4128-Master
A
K4128-Slave
A
K4128-Master
2
3 4
2
3 4

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(2)-2-2-2. When using OBICK, OLRCK and SDTO of AK4128A(U1).
JP48
OBICK JP49 SDTO
JP50
OLRCK
JP46
DIT-OBICK SEL JP47 DIT-OLRCK SEL
DIT-Slave
DIT-Master DIT-Slave DIT-Master
2
3 4
2
3 4
JP18
AK4128-OBICK SEL JP19 AK4128-OLRCK SEL
A
K4128-Slave
A
K4128-Master
A
K4128-Slave
A
K4128-Master
2
3 4
2
3 4
(2)-2-2-3. Selection of SDTO1, SDTO2, SDTO3 and SDTO4.
(a) Select to SDTO1 (b)Select to SDTO2 (c)Select to SDTO3 (d)Select to SDTO4
SDTO-SEL
JP17
2
3
4
2
７ ８
SDTO
1
SDTO-SEL
JP17
2
3
4
2
７ ８
SDTO
1
SDTO-SEL
JP17
2
3
4
2
７ ８
SDTO
1
SDTO-SEL
JP17
2
3
4
2
７ ８
SDTO
1

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(3). Other jumper pins setup.
[ JP9 (SEL1) ]：The selection of input signal to IMCLK pin.
IMCLK ：Connect to MCLK signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP10 (ILRCK2-SEL) ]：The selection of input signal to ILRCK2 pin.
ILRCK2：Connect to LRCK2 signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP11 (ILRCK3-SEL) ]：The selection of input signal to ILRCK3 pin.
ILRCK3：Connect to LRCK3 signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP12 (IBICK3-SEL) ]：The selection of input signal to IBICK3 pin.
IBICK3：Connect to BICK3 signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP13 (ILRCK4-SEL) ]：The selection of input signal to ILRCK4 pin.
ILRCK4：Connect to LRCK4 signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP14 (IBICK4-SEL) ]：The selection of input signal to IBICK4 pin.
IBICK4 ：Connect to BICK4 signal of DIR or 10 pin PORT. (Default)
GND ：Connect to GND
[ JP15 (SEL2) ]：The selection of input signal to INAS pin.
INAS ：Connect to INAS signal (Default)
GND ：Connect to GND
[ JP16 (UNLOCK) ]：The selection of connection to UNLOCK pin and LE1.
OPEN ：Unconnection.
SHORT ：Connection. (Default)
[ JP21 (TST0) ]：The selection of connection to TST0 pin and SW17(TST0).
OPEN ：Unconnection.
SHORT ：Connection. (Default)
[ JP22 (TST1) ]：The selection of connection to TST1 pin and SW3(TST1).
OPEN ：Unconnection.
SHORT ：Connection. (Default)
[ JP23 (TST2) ]：The selection of connection to TST2 pin and SW3(TST2).
OPEN ：Unconnection.
SHORT ：Connection. (Default)
[ JP24 (SEL4) ]：The selection of input signal to SDA pin.
SDA ：Connect to SDA signal of 10 pin PORT(PORT11). (Default)
GND ：Connect to GND
[ JP25 (TST3) ]：The selection of connection to TST3 pin and SW17(TST3).
OPEN ：Unconnection.
SHORT ：Connection. (Default)

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[ JP31 (EXT-CLK) ]：The selection of J7(EXT-CLK) connector.
OPEN ：J7(EXT-CLK) connector is use.
SHORT ：J7(EXT-CLK) connector is not use. (Default)
* If “JP31(EXT-CLK)” is set to “OPEN”, JP27 is set to “EXT”.

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Setup the DIP SW.
(1). Setup the AK4128A(U1).
(1)-1. SW3 setting
Upper-side is “H” and lower-side is “L”.
SW3
No. Name ON (“H”) OFF (“L”) Default
1 IDIF2 L
2 IDIF1 H
3 IDIF0
Audio Interface Format Setting for Input PORT
Refer to Table 3 L
4 SPB Serial Control Mode Parallel Control Mode L
5 TST1 L
6 TST2
TEST Pin
Fixed to ”L” L
7 SMSEMI Semi-auto Mode Manual Mode L
8 CAD0 Chip Address 0 bit=”1” Chip Address 0 bit=”0” L
Table 2. SW3 Setting
Mode IDIF2
pin
IDIF1
pin
IDIF0
pin SDTI1-4 Format IBICK
Freq
0 L L L 16bit, LSB justified ≥32FSI
1 L L H 20bit, LSB justified ≥40FSI
2 L H L 24bit, MSB justified ≥48FSI (Default)
3 L H H 24/16bit, I2S Compatible ≥48FSI or
32FSI
4 H L L 24bit, LSB justified ≥48FSI
5 H L H
6 H H H Reserved
Table 3. AK4128A Audio Interface Format Setting for Input PORT

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(1)-2. SW3 setting
Upper-side is “H” and lower-side is “L”.
SW4
No. Name ON (“H”) OFF (“L”) Default
1 OBIT1 H
2 OBIT0
Output PORT Audio Interface Format Setting 2
Refer to Table 6 H
3 TDM TDM mode Stereo mode L
4 CM2 H
5 CM1 L
6 CM0
Clock Select or Mode Select pin for Output PORT
Refer to Table 7 L
7 ODIF1 H
8 ODIF0
Output PORT Audio Interface Format Setting 1
Refer to Table 5 L
Table4. SW4 Setting
Mode TDM
pin
ODIF1
pin
ODIF0
pin SDTO1-4 Format
0 L L LSB justified
1 L H (Reserved)
2 H L MSB justified (Default)
3
L
H H I2S Compatible
4 L L
5 L H
(Reserved)
6 H L
TDM256 mode
24bit MSB justified
7
H
H H TDM256 mode
24bit I2S Compatible
Table 5. Output PORT Audio Interface Format Setting 1
OBICK Frequency
Mode TDM
pin
Master / Slave
setting
OBIT1
pin
OBIT0
pin
SDTO
1-4 OLRCK OBICK MSB
justified,
I2S
LSB
justified
0 L L 16bit
≥32FSO
1 L H 18bit
≥36FSO
2 H L 20bit
≥40FSO
3
Slave
(CM2-0 =
“HLL” or
“HHL”) H H 24bit
Input Input
≥48FSO
64FSO
(Default)
4 L L 16bit
5 L H 18bit
6 H L 20bit
7
L
Master
(Not CM2-0 =
“HLL”/“HHL”) H H 24bit
Output Output 64FSO
8
9
10
11
Slave
(CM2-0 =
“HLL” or
“HHL”)
* *
TDM256
mode
24bit
Input Input 256FSO
12
13
14
15
H
Master
(Not CM2-0 =
“HLL”/“HHL”)
* *
TDM256
mode
24bit
Output Output 256FSO
Table 6. Output PORT Audio Interface Format Setting 2

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Mode CM2
pin
CM1
pin
CM0
pin
Master /
Slave
OMCLK/XTI
Input
MCKO
Output FSO
0 L L L Master 256FSO 256FSO
8k ∼108kHz
1 L L H Master 384FSO 384FSO
8k ∼96kHz
2 L H L Master 512FSO 512FSO
8k ∼54kHz
3 L H H Master 768FSO 768FSO
8k ∼48kHz
4 H L L Slave
In External Clock
Mode,
1.024MHz~36.864MHz.
In X’tal Mode, X’tal
oscillation frequency.
OMCLK
Input Clock 8k ∼216kHz (Default)
5 H L H Master 128FSO 128FSO
8k ∼216kHz
6 H H L
7 H H H
Slave
(Bypass) Not used. (note) IMCLK
Input Clock 8k ∼216kHz
Table 7. Output PORT Master/Slave/Bypass Mode Control Setting
(1)-3. SW5 setting
Upper-side is “H” and lower-side is “L”.
SW4
No. Name ON (“H”) OFF (“L”) Default
1 INAS Asynchronous mode Synchronous mode L
2 DITHER Dither ON Dither OFF L
3 SMT1 L
4 SMT0
Soft Mute Timer Setting
Refer to Table 9 L
5 DEM0 H
6 DEM1
De-emphasis Filter Setting
Refer to Table 10 L
7 PM2 H
8 PM1
Channel Mode Setting
Refer to Table 11 L
Table 8. SW5 Setting
SMT1pin SMT0 pin Period FSO=48kHz FSO=96kHz FSO=192kHz
L L 1024/fso 21.3ms 10.7ms 5.3ms (Default)
L H 2048/fso 42.7ms 21.3ms 10.7ms
H L 4096/fso 85.3ms 42.7ms 21.3ms
H H 8192/fso 170.7ms 85.3ms 42.7ms
Table 9. Soft Mute Cycle Setting
DEM1pin DEM0 pin Mode(SDTI1-4)
L L 44.1kHz
L H OFF (Default)
H L 48kHz
H H 32kHz
Table 10. De-emphasis Filter Setting

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PM2
pin
PM1
pin
PDN
pin Mode X’tal Oscillator XTI pin XTO pin MCKO pin
L L L Pull down to
VSS2-5
L L H
6-channel
mode Power-down
Input
Hi-z
L H L Pull down to
VSS2-5
L H H
4-channel
mode Power-down
Input
Hi-z
Hi-z
H L L Power-down Pull down to
VSS2-5 Hi-z L
H L H
8-channel
mode Normal
operation Input Output
Normal
operation (Default)
H H L - - - -
H H H
Not
available - - - -
Table 11. Channel Mode Setting
(1)-4. SW17 setting
Upper-side is “H” and lower-side is “L”.
SW17
No. Name ON (“H”) OFF (“L”) Default
1 TST3 L
2 TST0
TEST Pin
Fixed to ”L” L
Table 12. SW17 Setting

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(2). Setup the AK4114 (U2,U3,U4,U5,U6)
(2)-1. SW6(U2), SW7(U3), SW8(U4), SW9(U5) setting.
Upper-side is “H” and lower-side is “L”.
SW6
No. Name ON (“H”) OFF (“L”) Default
1 DIR1-OCKS1 H
2 DIR1-OCKS0
Master Clock Frequency Setting
Refer to Table 17 L
3 DIR1-DIF0 24bit, I2S Compatible 24bit, Left justified L
Table 13. SW6 Setting
SW7
No. Name ON (“H”) OFF (“L”) Default
1 DIR2-OCKS1 H
2 DIR2-OCKS0
Master Clock Frequency Setting
Refer to Table 17 L
3 DIR2-DIF0 24bit, I2S Compatible 24bit, Left justified L
Table 14. SW7 Setting
SW8
No. Name ON (“H”) OFF (“L”) Default
1 DIR3-OCKS1 H
2 DIR3-OCKS0
Master Clock Frequency Setting
Refer to Table 17 L
3 DIR3-DIF0 24bit, I2S Compatible 24bit, Left justified L
Table 15. SW8 Setting
SW9
No. Name ON (“H”) OFF (“L”) Default
1 DIR4-OCKS1 H
2 DIR4-OCKS0
Master Clock Frequency Setting
Refer to Table 17 L
3 DIR4-DIF0 24bit, I2S Compatible 24bit, Left justified L
Table 16. SW9 Setting
Mode OCKS1 pin OCKS0 pin MCKO1 fs (max)
0 L L 256fs 96 kHz
1 L H 256fs 96 kHz
2 H L 512fs 48 kHz (Default)
3 H H 128fs 192 kHz
Table 17. Master Clock Frequency Setting

[AKD4128A-A]
[KM104301] 2010/09
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(2)-2. SW16(U6) setting.
Upper-side is “H” and lower-side is “L”.
SW16
No. Name ON (“H”) OFF (“L”) Default
1 DIT-OCKS1 H
2 DIT-OCKS0
Master Clock Frequency Setting
Refer to Table 19 L
3 DIT-DIF2 H
4 DIT-DIF1 L
5 DIT-DIF0
Audio Interface Format Setting
Refer to Table 20 L
Table 18. Master Clock Frequency Setting
Mode OCKS1 pin OCKS0 pin MCKO1 fs (max)
0 L L 256fs 96 kHz
1 L H 256fs 96 kHz
2 H L 512fs 48 kHz (Default)
3 H H 128fs 192 kHz
Table 19. Master Clock Frequency Setting
LRCK BICK
Mode DIF2
pin
DIF1
pin
DIF0
pin DAUX Format I/O I/O
0 L L L 24bit, Left justified H/L O 64fs O
1 L L H 24bit, Left justified H/L O 64fs O
2 L H L 24bit, Left justified H/L O 64fs O
3 L H H 24bit, Left justified H/L O 64fs O
4 H L L 24bit, Left justified H/L O 64fs O (Default)
5 H L H 24bit, I2S Compatible L/H O 64fs O
6 H H L 24bit, Left justified H/L I 64-128fs I
7 H H H 24bit, I2S Compatible L/H I 64-128fs I
Table 20. Audio Interface format Setting

[AKD4128A-A]
[KM104301] 2010/09
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The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (AK4128-SMUTE) ：Soft mute of AK4128A.
When using Soft mute function, SW1 is “H”.
[SW2] (AK4128-PDN) ：Resets the AK4128A. Keep “H” during normal operation.
The AK4128A should be resets once bringing “L” upon power-up.
[SW10] (DIR1-PDN) ：Resets the AK4114 (U2). Keep “H” during normal operation.
The AK4114 (U2) should be resets once bringing “L” upon power-up.
Keep “L” when AK4114 (U2) is not used.
[SW11] (DIR2-PDN) ：Resets the AK4114 (U3). Keep “H” during normal operation.
The AK4114 (U3) should be resets once bringing “L” upon power-up.
Keep “L” when AK4114 (U3) is not used.
[SW12] (DIR3-PDN) ：Resets the AK4114 (U4). Keep “H” during normal operation.
The AK4114 (U4) should be resets once bringing “L” upon power-up.
Keep “L” when AK4114 (U4) is not used.
[SW13] (DIR4-PDN) ：Resets the AK4114 (U5). Keep “H” during normal operation.
The AK4114 (U5) should be resets once bringing “L” upon power-up.
Keep “L” when AK4114 (U5) is not used.
[SW14] (DIT-PDN) ：Resets the AK4114 (U6). Keep “H” during normal operation.
The AK4114 (U6) should be resets once bringing “L” upon power-up.
Keep “L” when AK4114 (U6) is not used.
Indication for LED
[LE1] (UNLOCK) ：Monitor UNLOCK pin of the AK4128A (U1).
LED turns on when PDN pin = “L”.