AKM AKD4133-A User manual
[AKD4133-A]
< KM119500> 2016/11
GENERAL DESCRIPTION
The AKD4133-A is the evaluation board for the AK4133, 2ch digital sample rate converter.
This board has the optical connectors to interface with other digital audio equipments and serial
interfaces for AKM AD/DA evaluation boards. The AKD4133-A achieves quick evaluation of AK4133.
Ordering guide
AKD4133-A ---Evaluation board for AK4133
FUNCTION
Optical fiber connectors (for Digital Audio Interface. input x 1, output x 1.)
10pin Header (for AKM AD/DA evaluation board. input x 1, output x 1.)
On board X’tal Oscillator (input x 1, output x 1.)
Figure 1. AKD4133-A Block Diagram
*Circuit schematics are attached at the end of this manual.
AK4133 Evaluation Board Rev.0
AKD4133-A
- 1-
[AKD4133-A]
< KM119500> 2016/11
Evaluation Board Diagram
Board Diagram
J604
SW400
U100
U200
SW401
T602
T601
J600
J601
J602
J603
PORT200
PORT300
T600
SW200
SW500
J400
J300
J200
U300
SW300
SW402
SW403
Figure 2. AKD4133-A Board Diagram
Description
(1) U100 ( AK4133 )
2channels input/output Digital Sample Rate Converter (SRC).
(2) J200, J300 ( BNC Connector for Digital Input/Output )
J200 BNC connector : Digital Input optical signal to AK4118A(U200).
J300 BNC connector : Digital Output optical signal from AK4118A(U300).
(3) PORT200, PORT300 ( Optical Connector )
PORT200 : Digital Input optical signal to AK4118A(U200).
PORT300 : Digital Output optical signal from AK4118A(U300).
(4) J600, J601, J602, J603, J604 ( Power supply )
J600 (DVSS) : GND
J601 (+5V) : +5V Power Supply
J602 (DVDD) : + 3.3V/+1.8V Power Supply
J603 (VDD18) : +1.8V Power Supply
J604 (D33V) : +3.3V Power Supply
(5) U200, U300 ( AK4118A )
AK4118A has DIR, DIT and X’tal oscillator.
Transports input data to AK4133 when working in master mode, and output data from AK4133
when working in slave mode.
(6) J400 (BNC Connector)
Input external clock source.
(7) SW200, SW300 ( Dip-switch )
DIP type switch. Sets clock and audio format of AK4118A.
DIF[2 : 0] used to set audio interface format and OCKS[1 : 0] used to master clock frequency.
(8) SW500 ( Dip-switch )
DIP type switch. Sets clock and audio format and filter of AK4133.
- 2-
[AKD4133-A]
< KM119500> 2016/11
(9) SW400 ( Toggle switch )
Toggle type-switch PDN for AK4133.
“H” : PDN = High
“L” : PDN = Low
(10) SW401, SW403 ( Toggle switch )
Toggle type-switch PDN for AK4118A.
“H” : PDN = High
“L” : PDN = Low
(11) SW402 ( Toggle switch )
Toggle type-switch SMUTE for AK4133.
“H” : SMUTE = High
“L” : SMUTE = Low
(12) T600, T601, T602 ( regulator )
Regulator for AK4133, AK4118A, Logic Circuit.
T600 : Regulated DVDD (3.3V) from +5V.
T601 : Regulated DVDD, DV18 (1.8V) from +5V.
T602 : Regulated D33V (3.3V) from +5V.
- 3-
[AKD4133-A]
< KM119500> 2016/11
Evaluation Board Manual
Operation sequence
[1] Power supply line settings
[2] Jumped pins settings
[3] DIP switches settings
[4] Toggle switches settings
- 4-
[AKD4133-A]
< KM119500> 2016/11
[1] Power supply line settings
(1-1) Power supply settings : Used the regulator (T600,T601,T602) <Default>
Set up the power supplied lines :
* Each supply line should be distributed from the power supply unit.
Name
Color
Setting (Typ)
Function
Comments
Default Settings
J600
DVSS
Black
0V
Ground
Should always be connected
0V
J601
+5V
Red
+5V
Regulator power supply
Should always be connected
+5V
J602
DVDD
Yellow
+3.3V/+1.8V
AK4133 DVDD, Logic IC
power supply
+3.3V regulator is used,
JP601=+3.3V short and
JP600=REG short by default.
When jack is used, JP601=DVDD
short.
When 1.8V regulator is used,
JP600=+1.8V short and
JP601=DV18 short.
OPEN :
(JP600=+3.3V
short and
JP601=REG
short)
J603
DV18
Yellow
+1.8V
AK4133 DV18
+1.8V regulator is used,
JP602=REG short by default.
When jack is used, JP602=DV18
short.
OPEN :
(JP602= open)
J604
D33V
Yellow
+3.3V
AK4118A 3.3V VDD,
Logic IC power supply
+3.3V regulator is used,
JP603=REG short by default.
When jack is used,
JP603=D33V short.
OPEN :
(JP603=REG
short)
Table 1-1. Power supply line setting (default : used the regulator)
(1-2) About jumper for power supply :
The roles of the jumper for each power supply supplied from the regulator are as follows.
Connection of the jumper for power supply :
Name
Function
Comments
Default Settings
JP600
DVDD-VSEL1
Select regulator power supply
3.3V or 1.8V for DVDD.
DVDD for AK4133 and Logic IC :
JP600=3.3V short : 3.3V regulator is used by default.
JP600=1.8V short : 1.8V regulator is used.
+3.3V :
JP600=+3.3V short
JP601
DVDD-VSEL2
Select regulator power supply
or jack for DVDD.
DVDD for AK4133 and Logic IC :
JP601=REG short : 3.3V regulator is used by default.
JP601=DVDD short : Jack is used.
REG :
JP601=REG short
JP602
DV18-VSEL
Select regulator power supply
or jack for DV18.
DV18 for AK4133 :
JP602=REG short : 1.8V regulator is used.
JP602=DV18 short : Jack is used.
REG :
JP602=REG short
JP603
D33V-VSEL
Select regulator power supply
or jack for D33V.
D33V for Logic IC :
JP603=REG short : 3.3V regulator is used by default.
JP603=D33V short : Jack is used.
REG :
JP603=REG short
JP100
DVDD-SEL
short
No use.
JP100=short
JP101
DV18-SEL
Select External power supply
or LDO power supply of
AK4133 for DV18.
DV18 selector for AK4133 :
JP101=open and JP602=short : LDO of AK4133 is
used by default.
JP101=short and JP602=short : External Power supply
is used.
+1.8V :
JP101=short
JP602=short
Table 1-2. Jumper for power supply
- 5-
[AKD4133-A]
< KM119500> 2016/11
[2] Jumper pins and Port pins settings
No
Names
Default
Functions
1
JP100
DVDD-SEL
Short
No use.
2
JP101
DV18-SEL
Short
Select Short / Open DV18.
Open : DV18 pin of AK4133 open.
Short : DV18 pin of AK4133 connect 1.8Vcourse. (default)
3
JP200
RXDATA-SEL
OPT
Select OPT/COAX input for RX data.(DIR : AK4118A)
OPT : Optical input
COAX : COAX(BNC) input. (default)
4
JP300
MCLK-T-SEL
2-3pin short
Select Tx MCLK.
1-2pin : External MCLK input select.
2-3pin : X’tal Oscillator use select. (default)
5
JP301
XTO
Short
Select Tx MCLK.
Open : External MCLK input select.
Short : X’tal Oscillator select. (default)
6
JP302
TXDATA-SEL
OPT
Select OPT/COAX output for TX data. (DIT : AK4118A)
OPT : Optical output
COAX : COAX(BNC) output
7
JP400
BICK-R-SEL
DIR
Select Rx BICK.
DIR : BICK-4118A-R(DIR) (default)
PORT400 : PORT400-IBICK
8
JP401
BICK-R-PHASE
THR
Select polarity (non-inverted output / inverted output) of BICK－R-SEL
outputs.
THR : Non-inverted output. (default)
INV : Inverted output.
9
JP404
LRCK-R-SEL
DIR
Select Rx LRCK.
DIR : LRCK-4118A-R(DIR) (default)
PORT400 : PORT400-ILRCK
10
JP406
SDTI-R-SEL
DIR
Select Rx LRCK.
DIR : SDTO-4118A-R(DIR) (default)
PORT400 : PORT400-SDTI
11
JP402
BICK-T-SEL
DIT
Select Tx BICK.
DIT : BICK-4118A-T(DIT) (default)
PORT401 : PORT401-OBICK
12
JP403
BICK-T-PHASE
THR
Select polarity (non-inverted output / inverted output) of BICK-T-SEL
outputs.
THR : Non-inverted output. (default)
INV : Inverted output.
13
JP405
LRCK-T-SEL
DIT
Select Tx LRCK.
DIT : LRCK-4118A-T(DIT) (default)
PORT401 : PORT401-OLRCK
14
JP407
No use.
15
JP408
MCLK-T-SEL
GND
Select Tx DATA.
DIT : MCLK-4118A-T(DIT) (default)
PORT401 : PORT401-OMCLK
EXT : External MCLK input
GND : DVSS short
16
PORT400
RX-PORT
Open
Open : No input (default)
Short : Rx Data/Clock input
- 6-
[AKD4133-A]
< KM119500> 2016/11
No
Names
Default
Functions
17
PORT401
TX-PORT
Open
Open : No input (default)
Short : Tx Data/Clock input
18
JP500
19
JP501
Table 2-1. Jumper pin setting
- 7-
[AKD4133-A]
< KM119500> 2016/11
[3] DIP switches settings
(3-1). Setting for SW200 / SW300
(Sets AK4118A (U200 / U300) audio format and master clock setting)
No.
Switch Name
Function
default
1
DIF2
Set-up of DIF2 pin.
H
2
DIF1
Set-up of DIF1 pin.
L
3
DIF0
Set-up of DIF0 pin.
H
4
OCKS1
Set-up of OCKS1 pin.
L
5
OCKS0
Set-up of OCKS0 pin.
L
Table 3-1. SW200 / SW300 Setting
Mode
DIF2 pin
DIF1 pin
DIF0 pin
DAUX
SDTO
LRCK
BICK
I/O
I/O
0
0
0
0
24bit, Left
justified
16bit, Right
justified
H/L
O
64fs
O
1
0
0
1
24bit, Left
justified
18bit, Right
justified
H/L
O
64fs
O
2
0
1
0
24bit, Left
justified
20bit, Right
justified
H/L
O
64fs
O
3
0
1
1
24bit, Left
justified
24bit, Right
justified
H/L
O
64fs
O
4
1
0
0
24bit, Left
justified
24bit, Left
justified
H/L
O
64fs
O
5
1
0
1
24bit, I2S
24bit, I2S
L/H
O
64fs
O
default
6
1
1
0
24bit, Left
justified
24bit, Left
justified
H/L
I
64-128fs
I
7
1
1
1
24bit, I2S
24bit, I2S
L/H
I
64-128fs
I
Table 3-2. Audio format (AK4118A)
OCKS1 pin
OCKS0 pin
(X’tal)
MCKO1
MCKO2
fs (max)
0
0
256fs
256fs
256fs
96 kHz
default
0
1
256fs
256fs
128fs
96 kHz
1
0
512fs
512fs
256fs
48 kHz
1
1
128fs
128fs
64fs
192 kHz
Table 3-3. Master Clock Frequency Select (AK4118A)
(3-2). Setting for SW500 (AK4133 (U100) )
No.
Switch Name
Function
default
1
SD
Digital Filter select setting.
L
2
CM0
Clock select or Mode setting 0.
H
3
CM1
Clock select or Mode setting 1.
L
4
TEST
TEST pin setting.
L
5
SEL33
No use.
L
6
VSEL
Digital Power select
L : DV18 is Output
H : DV18 is Power supply
L
7
ODIF
Audio Interface Format for Output PORT.
H
8
IDIF
Digital Input Format setting.
H
Table 3-4. SW500 Setting (AK4133)
- 8-
[AKD4133-A]
< KM119500> 2016/11
[4] Toggle switches settings
Up=”H”, Down=”L”
[SW400] ( Power Down (PDN) for AK4133) :
Power Down (PDN) Switch for AK4133
Reset AK4133 (U100) once by brining SW400 to “L” once upon power-up.
Keep “H”when AK4133 is in use; keep “L”when AK4133 is not in use.
[SW401] ( Power Down (PDN) for AK4118A-Rx) :
Power Down (PDN) Switch for AK4118A-Rx
Reset AK4118A (U200) once by brining SW401 to “L” once upon power-up.
Keep “H”when AK4118A is in use; keep “L”when AK4118A is not in use.
[SW402] ( Soft Mute (SMUTE) for AK4133) :
Soft Mute (SMUTE) Switch for AK4133
When this switch is changed to “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
[SW403] ( Power Down (PDN) for AK4118A-Tx) :
Power Down (PDN) Switch for AK4118A-Tx
Reset AK4118A (U300) once by brining SW402 to “L” once upon power-up.
Keep “H” when AK4118A is in use; keep “L” when AK4118A is not in use.
- 9-
[AKD4133-A]
< KM119500> 2016/11
Measurement Results
[Measurement condition]
Measurement unit : Audio Precision SYS-2722 (No.00095)
Power Supply : DVDD=3.3V (VSEL=L)
Band width : 20Hz FSO/2
Resolution (Bit) : 24bit
XTI Input : Use X’Tal (X300)
Output PORT : Slave Mode
Temperature : Room
[Measurement Result]
SRC Characteristics
SDTO
Unit
Lch
Rch
THD+N (Input = 1kHz, 0dBFS)
FSO/FSI = 48kHz/48kHz
111.8
111.9
dB
FSO/FSI = 44.1kHz/48kHz
106.7
106.7
dB
FSO/FSI = 48kHz/192kHz
111.0
111.1
dB
Worst Case (FSO/FSI = 44.1kHz/96kHz)
105.4
105.4
dB
Dynamic Range (Input = 1kHz, 60dBFS)
FSO/FSI = 48kHz/48kHz
112.2
112.2
dB
FSO/FSI = 48kHz/44.1kHz
112.6
112.6
dB
FSO/FSI = 48kHz/192kHz
111.7
111.7
dB
Worst Case (FSO/FSI = 44.1kHz/192kHz)
111.8
111.8
dB
Dynamic Range (Input = 1kHz, 60dBFS, A-weighted)
FSO/FSI = 48kHz/48kHz
115.1
115.2
dB
- 10-
[AKD4133-A]
< KM119500>2016/11
[Plots]
Figure 5-1. FFT Plot (Input = 0dBFS)
Figure 5-2. FFT Plot (Input = -60dBFS)
-180
+0
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-180
+0
-160
-140
-120
-100
-80
-60
-40
-20
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
AK4133 FFT
FSO/FSI=44.1kHz/48kHz, 1kHz/0dBFS Input
AK4133 FFT
FSO/FSI=44.1kHz/48kHz, 1kHz/ -60dBFS Input
- 11-
[AKD4133-A]
< KM119500>2016/11
Figure 5-3. THD+N vs. Input Frequency (Input = 0dBFS)
Figure 5-4. THD+N vs. Input Frequency (Input = -60dBFS)
-120
-90
-117.5
-115
-112.5
-110
-107.5
-105
-102.5
-100
-97.5
-95
-92.5
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
-120
-100
-118
-116
-114
-112
-110
-108
-106
-104
-102
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
AK4133 THD+N vs. Input Frequency
FSO/FSI=44.1kHz/48kHz, 0dBFS Input
AK4133 THD+N vs. Input Frequency
FSO/FSI=44.1kHz/48kHz, -60dBFS Input
- 12-
[AKD4133-A]
< KM119500>2016/11
Figure5-5. Frequency Response (FSO=44.1kHz)
Figure5-6. Frequency Response (FSO=48kHz)
-10
+1
-9
-8
-7
-6
-5
-4
-3
-2
-1
-0
d
B
F
S
2k 22k4k 6k 8k 10k 12k 14k 16k 18k 20k
Hz
-10
+1
-9
-8
-7
-6
-5
-4
-3
-2
-1
-0
d
B
F
S
2.5k 22.5k5k 7.5k 10k 12.5k 15k 17.5k 20k
Hz
TTTTTT
FSI=96k
Hz
FSI=48k
Hz
FSI=44.1k
Hz
FSI=96k
Hz
FSI=48k
Hz
AK4133 Frequency Response
FSI=44.1kHz/48kHz/96kHz/192kHz
FSO=44.1kHz, 0dBFS Input
AK4133 Frequency Response
FSI=48kHz/96kHz/192kHz
FSO=48kHz, 0dBFS Input
FS I: B lu e=4 8kH z/R ed=9 6kH z /G ree n= 192kHz
FSI : Yellow=44.1kHz/Blue =48kHz/Re d=96kHz/Green=192kHz
FSI=192
kHz
FSI=192
kHz
- 13-
[AKD4133-A]
< KM119500>2016/11
REVISION HISTORY
Date
(YY/MM/DD)
Manual
Revision
Board
Revision
Reason
Page
Contents
16/11/18
KM119500
0
First edition
-
- 14-
[AKD4133-A]
< KM119500>2016/11
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation ( “ A K M ” ) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or
application of AKM product stipulated in this document (“Product”), please make inquiries the
sales office of AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations
with respect to the accuracy or completeness of the information contained in this document nor
grants any license to any intellectual property rights or any other rights of AKM or any third
party with respect to the information in this document. You are fully responsible for use of
such information contained in this document in your product design or applications. AKM
ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES
ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR
APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of
which may cause loss of human life, bodily injury, serious property damage or serious public
impact, including but not limited to, equipment used in nuclear facilities, equipment used in
the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and
other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless
specifically agreed by AKM in writing.
3. Though AKM works continually to improve the P r od u c t’ s qua l it y a nd r eli a b il ity, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations
in which a malfunction or failure of the Product could cause loss of human life, bodily injury
or damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the
design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological
weapons or missile technology products (mass destruction weapons). When exporting the
Products or related technology or any information contained in this document, you should
comply with the applicable export control laws and regulations and follow the procedures
required by such laws and regulations. The Products and related technology may not be used
for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including
without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses
occurring as a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features
set forth in this document shall immediately void any warranty granted by AKM for the Product
and shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, withou t
prior written consent of AKM.
- 15-
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
DV18
Cap Dip open + 1pin Socket (PDN Cap)
CM0
CM1
DVSS
OMCLK
OLRCK
OBICK
SDTO
SD
ODIF
SMUTE
ILRCK
IBICK
SDTI
IDIF
SRCEN
TEST
DVDD
PDN
VSEL
DVSS
DVSS
CM0
CM1
DV18
OMCLK
SDTO
OBICK
OLRCK
SD
ODIF
SRCEN ILRCK
IBICK
SDTI
IDIF
TEST
SMUTE
DVDD
PDN
VSEL
SEL33
Title
Size Document Number Rev
Date: Sheet of
<AK4133>
<0>
<AKD4133-A>
A3
1 6
Friday, July 24, 2015
Title
Size Document Number Rev
Date: Sheet of
<AK4133>
<0>
<AKD4133-A>
A3
1 6
Friday, July 24, 2015
Title
Size Document Number Rev
Date: Sheet of
<AK4133>
<0>
<AKD4133-A>
A3
1 6
Friday, July 24, 2015
C102
0.1u
CN101
6pin_2
7
8
9
10
11
12
TP118
TP102
TP101
R104 0
TP106
TP103
R110 0
C103
0.1u
JP101
DV18-SEL
R115
0
TP100
TP112
R114
0
R109 0
R102
0
CN103
6pin_4
19
20
21
22
23
24
R105 0
CN102
6pin_3
13
14
15
16
17
18
TP116
U100
AK4133VN
SD
1
SMUTE
2
CM0
3
CM1
4
TEST
5
ILRCK 6
IBICK 7
SDTI 8
OMCLK 9
OLRCK 10
OBICK 11
SDTO 12
DV18 13
DVSS 14
DVDD 15
VSEL
16
PDN
17
ODIF
18
IDIF
19
SRCE_N
20
TP104
TP111
R101
0
R112 0
R100
0
TP108
+
C100
10u
R118
0
TP120
TP113
R103
0
JP100
DVDD-SEL
C104 open
TP105
TP107
TP114
R108 0
R113 0
R107 0
TP110
TP115
TP117
R111 0
R106 0
R116
0
TP109
TP119
CN100
6pin_1
1
2
3
4
5
6
+
C101
10u
R117
0
- 16-
5
5
4
4
3
3
2
2
1
1
E E
D D
C C
B B
A A
OCKS0
H
L
DIF2
DIF1
DIF0
OCKS1
X200 Frequency Check -> 12.288MHz
+ 1pin Socket (AK4118 Xtal)
OPT
COAX
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
OCKS0-R
OCKS0-R
SDTO-4118A-R
OCKS1-R
LRCK-4118A-R
D33V
D33V
D33V
OCKS1-R
D33V
D33V
INT0-R
PDN-R
BICK-4118A-R
Title
Size Document Number Rev
Date: Sheet of
<AK4118A-DIR>
<0>
<AKD4133-A>
A3
2 6
Tuesday, October 21, 2014
Title
Size Document Number Rev
Date: Sheet of
<AK4118A-DIR>
<0>
<AKD4133-A>
A3
2 6
Tuesday, October 21, 2014
Title
Size Document Number Rev
Date: Sheet of
<AK4118A-DIR>
<0>
<AKD4133-A>
A3
2 6
Tuesday, October 21, 2014
JP200
RXDATA-SEL
U200
AK4118A
IPS0/RX4
1
NC
2
DIF0/RX5
3
TEST2
4
DIF1/RX6
5
VSS1
6
DIF2/RX7
7
IPS1/IIC
8
P/SN
9
XTL0
10
XTL1
11
TVDD
13
NC/GP1
14
TX0/GP2
15
TX1/GP3
16
BOUT/GP4
17
COUT/GP5
18
UOUT/GP6
19
VOUT/GP7
20
DVDD
21
VSS2
22
MCKO1
23
BICK 26
MCKO2 27
DAUX 28
XTO 29
XTI 30
PDN 31
CM0/CDTO/CAD1 32
CM1/CDTI/SDA 33
OCKS1/CCLK/SCL 34
OCKS0/CSN/CAD0 35
INT0 36
AVDD 38
R39
VCOM 40
VSS3 41
RX0 42
NC 43
RX1 44
TEST1 45
RX2 46
VSS4 47
RX3 48
VIN/GP0
12
LRCK
24
SDTO 25
INT1 37
R200 51
C208
0.1u
C205 0.1u
L200 47uH
1 2
+C201
10u
C209
0.1u
+
C210
10u
SW200
1
2
3
4
5
10
9
8
7
6
C200
0.1u
TP200
RX-OPT
+
C211
10u
R203 10k
C207 5p
PORT200
RX-OPT
OUT 1
VCC 3
GND 2
J200
RX-COAX
12
3
4
5
R204 10k
C204
0.47u
R206 10k
X200
12.288MHz
12
R202
75
R205 10k
+
C202 10u
R207 10k
C203 0.1u
R201 10k
C206 5p
- 17-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OCKS0
H
L
DIF2
DIF1
DIF0
OCKS1
X300 Frequency Check -> 12.288MHz
+ 1pin Socket (AK4118 Xtal)
OPT
COAX
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS DVSS
DVSS
OCKS0-T
OCKS0-T
OCKS1-T
LRCK-4118A-T
MCLK-4118A-T
D33V
D33V
D33V
OCKS1-T
D33V
D33V
INT0-T
PDN-T
DAUX-4118A-T
BICK-4118A-T
EXT-MCLK-T
Title
Size Document Number Rev
Date: Sheet of
<AK4118A-DIT>
<0>
<AKD4133-A>
A3
3 6
Tuesday, October 21, 2014
Title
Size Document Number Rev
Date: Sheet of
<AK4118A-DIT>
<0>
<AKD4133-A>
A3
3 6
Tuesday, October 21, 2014
Title
Size Document Number Rev
Date: Sheet of
<AK4118A-DIT>
<0>
<AKD4133-A>
A3
3 6
Tuesday, October 21, 2014
JP300
MCLK-T-SEL
C309
0.1u
TP300
TX-OPT
R302 10k
PORT300
TX-OPT
GND 1
VCC 2
IN 3
U300
AK4118A
IPS0/RX4
1
NC
2
DIF0/RX5
3
TEST2
4
DIF1/RX6
5
VSS1
6
DIF2/RX7
7
IPS1/IIC
8
P/SN
9
XTL0
10
XTL1
11
TVDD
13
NC/GP1
14
TX0/GP2
15
TX1/GP3
16
BOUT/GP4
17
COUT/GP5
18
UOUT/GP6
19
VOUT/GP7
20
DVDD
21
VSS2
22
MCKO1
23
BICK 26
MCKO2 27
DAUX 28
XTO 29
XTI 30
PDN 31
CM0/CDTO/CAD1 32
CM1/CDTI/SDA 33
OCKS1/CCLK/SCL 34
OCKS0/CSN/CAD0 35
INT0 36
AVDD 38
R39
VCOM 40
VSS3 41
RX0 42
NC 43
RX1 44
TEST1 45
RX2 46
VSS4 47
RX3 48
VIN/GP0
12
LRCK
24
SDTO 25
INT1 37
C304 5p
C301 0.1u
R303 10k
R300 10k
T300
DA-02F
R304 10k
SW300
1
2
3
4
5
10
9
8
7
6
JP301XTO
C302
0.47u
J300
TX-COAX
12
3
4
5
C306
0.1u
C310
0.1u
R305 10k
C305
0.1u
C303 5p
R306
240
X300
12.288MHz
12
+
C307
10u
+
C308
10u
R307
150
JP302
TXDATA-SEL
+
C300 10u
R301 10k
- 18-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HL HL
HL
IBICK
ILRCK
SDTI
OMCLK
OBICK
OLRCK
SDTO
DIT
THR
INV
GND
PORT401
DIT
EXT
DIT
PORT401
DIT
PORT401
PORT400
DIR
DIR
PORT400
DIR
PORT400
THR
INV
HL
BICK-R-THR
BICK-R-INV
OBICK-T
BICK-T-INV
BICK-T-THR
PORT401-OMCLK
BICK-T-THR
BICK-T-INV
OLRCK-T
SDTO-T
PORT401-OBICK
PORT401-OLRCK
PORT400-SDTI
PORT400-ILRCK
PORT400-IBICK
PORT400-SDTI
PORT400-IBICK
PORT400-ILRCK
BICK-R0
LRCK-R0
ISDTI-R0
BICK-R-INV
BICK-R-THR
DAUX-4118A-T
PORT401-OLRCK
PORT401-OBICK
PORT401-OMCLK
DVSS
DVSS DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
D33V D33V
PDN0 PDN-T
D33V D33V
PDN-R
D33V
MCLK-4118A-T
OMCLK0
OBICK-T
OLRCK-T
SDTO-T
BICK-4118A-T
LRCK-4118A-T
D33V
IBICK-R
ILRCK-R
SDTO-4118A-R SDTI-R
BICK-4118A-R
LRCK-4118A-R
EXT-MCLK-T
SDTO
INT0-T
INT0-R
SRCEN0
SMUTE0
Title
Size Document Number Rev
Date: Sheet of
<LOGIC1>
<0>
<AKD4133-A>
A3
4 6
Tuesday, July 21, 2015
Title
Size Document Number Rev
Date: Sheet of
<LOGIC1>
<0>
<AKD4133-A>
A3
4 6
Tuesday, July 21, 2015
Title
Size Document Number Rev
Date: Sheet of
<LOGIC1>
<0>
<AKD4133-A>
A3
4 6
Tuesday, July 21, 2015
C402
0.1u
SW403
PDN-T
21
3
R407 10k
D402
HSU119
KA
D401
HSU119
KA
C403
0.1u
R404 10k
R402 10k
TP406
OMCLK
JP406
SDTI-R-SEL
C401
0.1u
JP402
BICK-T-SEL
C400
0.1u
R405 10k
C405
0.1u
TP405
SDTO-T
R411 1k
PORT400
RX-PORT
R400 10k
R410
10k
JP405
LRCK-T-SEL
LE401 SRCEN
2 1
JP403
BICK-T-PHASE
TP404
SDTI-R0
U401
74HC14P
GND
7
1A
1
3A
55A 11
5Y 10
3Y
6
1Y
2
2Y
4
4Y 8
6Y 12
6A 13
4A 9
2A
3VCC 14
R409
10k
JP409
EXT-MCLK
D403
HSU119
KA
R415
10k
JP404
LRCK-R-SEL
D400
HSU119
KA
PORT401
TX-PORT
LE400INT0-T
21
R414 0
J400
EXT-MCLK
12
3
4
5
TP401
OBICK-T
C404
0.1u
TP403
OLRCK-T
R401 10k
TP400
BICK-R
R412 1k
R413 0
SW401
PDN-R
21
3
JP408
OMCLK-SEL
JP401
BICK-R-PHASE
TP402
LRCK-R
SW400
PDN
21
3
LE402 INT0-R
2 1
JP400
BICK-R-SEL
R403
51
R416
10k
SW402
SMUTE
21
3
R406 10k
R408
open
U400
74HC14P
GND
7
1A
1
3A
55A 11
5Y 10
3Y
6
1Y
2
2Y
4
4Y 8
6Y 12
6A 13
4A 9
2A
3VCC 14
- 19-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DVDD -> D33V
D33V -> DVDD
U500 (Buffer)
10pin=DVSS
20pin=DVDD
D33V -> DVDD
DVDD -> D33V
for U500 74VCX541
SEL33
H
L
SD
CM0
CM1
TEST
VSEL
ODIF
IDIF
U504 (NAND)
7pin=DVSS
14pin=D33V
for U504 74VCX00
D33V -> DVDD
CM0
CM1
TEST
SD
VSEL
ODIF0
IDIF0
SEL33
CM10
CM00
CM1
CM0
CM10
CM00
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
DVSS
ILRCK
SDTI
IBICK
OBICK-T
OLRCK-T
ILRCK-R
IBICK-R DAUX-4118A-T
SDTI-R
DVDD
PDN0
DVDD
PDN
TEST
SD
VSEL
SEL33
DVDD
D33V
SRCEN0 SRCEN
SDTO-T
OBICK
OLRCK
CM1
CM0
IDIF
ODIF
SMUTE0 SMUTE
OMCLK0 OMCLK
D33V
D33V
D33V
Title
Size Document Number Rev
Date: Sheet of
<LOGIC2>
<0>
<AKD4133-A>
A3
5 6Tuesday, July 21, 2015
Title
Size Document Number Rev
Date: Sheet of
<LOGIC2>
<0>
<AKD4133-A>
A3
5 6Tuesday, July 21, 2015
Title
Size Document Number Rev
Date: Sheet of
<LOGIC2>
<0>
<AKD4133-A>
A3
5 6Tuesday, July 21, 2015
R536 0
R529 0
R550 51
R553 51
R516 51
R541 10k
R535 0
U505
74VCX125
A1
2
A2
5
A3
9
A4
12
1OE
1
2OE
4
Y1 3
Y2 6
Y3 8
Y4 11
3OE
10
4OE
13
VCC
14
GND
7
R515 51
R509 51
C504
0.1u
R519 51
R544 10k
U500
74VCX541
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
G1
1
G2
19
Y1 18
Y2 17
Y3 16
Y4 15
Y5 14
Y6 13
Y7 12
Y8 11
R507 51
R528 0
R521 0
R554 51
R502 51
R543 10k
R514 0
C500
0.1u
R513 51
R523 0
R546 10k
U501
74VCX125
A1 2
A2 5
A3 9
A4 12
1OE 1
2OE 4
Y1
3
Y2
6
Y3
8
Y4
11
3OE 10
4OE 13
VCC 14
GND 7
U504
74VCX00
1A
1
1B
2
2A
4
2B
5
3A
9
3B
10
1Y 3
2Y 6
3Y 8
4Y 11
4A
12
4B
13
R522 0
R547 10k
R500 51
C501
0.1u
R557 0
R524 0
R530 51
R545 10k
R556 0
R552 0
R510 51
R526 51
R511 51
R520 0
R517 0
U502
74VCX125
A1
2
A2
5
A3
9
A4
12
1OE
1
2OE
4
Y1 3
Y2 6
Y3 8
Y4 11
3OE
10
4OE
13
VCC
14
GND
7
R548 10k
U503
74VCX125
A1 2
A2 5
A3 9
A4 12
1OE 1
2OE 4
Y1
3
Y2
6
Y3
8
Y4
11
3OE 10
4OE 13
VCC 14
GND 7
R555 0
R512 51
R551 0
R503 51
C503
0.1u
C505
0.1u
R508 51
SW500
SW DIP-8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R501 51
R505 51
R527 51
R549 51
R525 51
R504 51
R506 51
R518 51
R542 10k
C502
0.1u
- 20-
Table of contents
Other AKM Motherboard manuals
