AKM AK4115 User manual

ASAHI KASEI [AKD4115-A]
<KM076403> 2006/08
- 1 -
GENERAL DESCRIPTION
AKD4115 is the evaluation board for AK4115, 192kHz digital audio transceiver. This board has optical,
cannon connector (XLR), and BNC connectors to interface with other digital audio equipment.
Ordering guide
AKD4115-A --- Evaluation board for AK4115
(A cable for connecting the printer port (parallel port) of IBM-AT compatible PC
and control software are packed with this document. Please note that the control
software does not operate on Windows NT)
FUNCTION
Digital interface
-S/PDIF :
8 channel input (optical, BNC or XLR)
2 channel output (optical, BNC or XLR)
- Serial audio data I/F :
1 input (for DIT data input. 10-pin port)
1 output (for DIR data output. 10-pin port)
-B,C,U,V bit :
1 input/output port (10-pin port)
-Serial control data I/F
1 input/output port (10-pin port)
RX0
RX1
AK4115
B,C,U,V Serial Data in
(To DIT)
Control
5V GND
Opt
RX7
TX0
TX1
Opt
Serial Data out
(From DIR
REG 3.3V
Figure 1. AKD4115-A Block Diagram
*Circuit diagram and PCB layout are attached at the end of this manual.
AK4115 Evaluation Board Rev.3
A
KD4115-
A

ASAHI KASEI [AKD4115-A]
<KM076403> 2006/08
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Evaluation Board Manual
Operating sequence
(1) Set up the power supply lines.
[+ 5V] (Red) = 5V
[GND] (Black) = 0V
Each supply line should be distributed from the power supply unit.
(2) Set up the evaluation mode and jumper pins. (Refer to the following item.)
(3) Connect cables. (Refer to the following item.)
(4) Power on.
The AK4115 should be reset once bringing PDN (SW2) “L” upon power-up.
Evaluation modes
(1) Evaluation for DIR
S/PDIF Optical, XLR or
BNC connector PORT2
(10pin Header)
MCLK
BICK
LRCK
SDTI
AK4115
(DIR)
AKD4115-A
DAC
MCLK
BICK
LRCK
SDTI
The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical
connector(PORT1: TORX176), BNC connector or cannon connector(XLR). The AKD4115 can be connected
with the AKM’s DAC evaluation board via 10-pin cable.
a. Set-up of Bi-phase Input
RXP0/RXN0 and RX1-7 should not select BNC at the same time.
a-1. RXP0/RXN0
Connector JP2(RXP0) JP3(RXN0)
Optical (PORT1) OPT BNC
XLR (J1) XLR XLR
BNC (J2) BNC BNC
Table 1. Set-up of RXP0/RXN0
a-2. RX1, 2, 3, 4, 5, 6, and 7 can be inputted from a BNC (J2) connector only.
Only RX1, RX2 and RX 3 can be used in parallel mode. The jumper which selects the Rx channel should be
Short.
Input RX1 RX2 RX3 RX4 RX5 RX6 RX7
JP4 JP5
JP6 JP7 JP8 JP9
JP10
JP Short Short
Short RX4 RX5 RX6 RX7
Table 2. Set-up of RX1, 2, 3, 4, 5, 6 and 7

ASAHI KASEI [AKD4115-A]
<KM076403> 2006/08
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a-3. Set-up of AK4115 input path
In Parallel Mode you will need to use SW1_1 & SW1_5.
In Serial Mode you will need to use IPS2-0 bits.
- IPS1 pin
(SW1_5)
IPS0 pin
(SW1_1)
IPS2 bit IPS1 bit IPS0 bit
INPUT Data
0 0 0 RX0 Default
0 0 1 RX1
0 1 0 RX2
0 1 1 RX3
1 0 0 RX4
1 0 1 RX5
1 1 0 RX6
1 1 1 RX7
(In parallel mode, IPS2 is fixed to “0”)
Table 3. Recovery Data Select
b. Set-up of clock input and output
The signal level outputted/inputted from PORT2 is 3.3V.
PORT2
DIR 5
6
1
10
GND GND GND GND
NC
MCLK BICK LRCK SDTO
Figure 2. PORT2 pin layout
b-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2
is selected by OCKS 1-0.
Output
signal JP12
MCKO1 MCKO1
Default
MCKO2 MCKO2
Table 4. MCKO1/MCKO2 set-up
OCKS1 pin
(SW3_2)
OCKS0 pin
(SW3_3)
OCKS1 bit OCKS0 bit
(X’tal) MCKO1 MCKO2 fs (max)
0 0 256fs 256fs 256fs 96 kHz
Default
0 1 256fs 256fs 128fs 96 kHz
1 0 512fs 512fs 256fs 48 kHz
1 1 128fs 128fs 64fs 192 kHz
Table 5. Master Clock Frequency Select

ASAHI KASEI [AKD4115-A]
<KM076403> 2006/08
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b-2. Set-up of BICK and LRCK input and output
Please select SW 3_7 (DIR_I/O) according to the setup of audio format of AK4115 (Refer to Table 7).
Audio format SW3_7 (DIR_I/O)
Slave mode 0 Default
Master mode 1
Table 6. DIR_I/O set-up
c. Set-up of Audio format
It sets up by SW 1_2 and SW 1_3 in parallel mode. Please set up DIF2-0 bit and AES3 bit in serial mode.
- -
DIF1 pin
(SW1_3)
DIF0 pin
(SW1_2) LRCK BICK
Mode AES3
bit
DIF2
bit DIF1 bit DIF0 bit
DAUX SDTO
I/O I/O
0 0 0 0 0 24bit, Left
justified
16bit, Right
justified H/L O 64fs O
1 0 0 0 1 24bit, Left
justified
18bit, Right
justified H/L O 64fs O
2 0 0 1 0 24bit, Left
justified
20bit, Right
justified H/L O 64fs O
3 0 0 1 1 24bit, Left
justified
24bit, Right
justified H/L O 64fs O
4 0 1 0 0 24bit, Left
justified
24bit, Left
justified H/L O 64fs O
5 0 1 0 1 24bit, I2S 24bit, I2S L/H O 64fs O
6 0 1 1 0 24bit, Left
justified
24bit, Left
justified H/L I 64-128f
s I Default
7 0 1 1 1 24bit, I2S 24bit, I2S L/H I 64-128f
s I
8 1 x x x 24bit, Left
justified AES3 Mode H/L O 64fs O
Table 7. Audio format

ASAHI KASEI [AKD4115-A]
<KM076403> 2006/08
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d. Set-up of CM1 and CM0
The operation mode of PLL is selected by CM1 and CM0. In parallel mode, it can be selected by SW3_4, SW3_1
and JP18. In serial mode, it can be selected by PSEL bit and CM1-0 bits.
PSEL pin
(SW3_4)
CM1 pin
(SW3_1)
CM0 pin
(JP18)
PSEL bit CM1 bit CM0 bit
(UNLOCK) PLL X'tal Clock source
SDTO
source
0 0 0 - ON ON(Note) PLL(RX) RX
Default
0 0 1 - OFF ON X'tal DAUX
0 ON ON PLL(RX) RX
0 1 0 1 ON ON X'tal DAUX
0 1 1 - ON ON X'tal DAUX
1 0 0 - ON ON(Note) PLL(ELRCK) DAUX
1 0 1 - OFF ON X'tal DAUX
0 ON ON PLL(ELRCK) DAUX
1 1 0 1 ON ON X'tal DAUX
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note: When the X’tal is not used as clock comparison for fs detection (XTL0, 1= “1,1”), the X’tal is OFF.
Table 8. Clock Operation Mode Select

ASAHI KASEI [AKD4115-A]
<KM076403> 2006/08
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(2) Evaluation for DIT
1. Synchronous mode
S/PDIF
Optical, XLR or
BNC connector
PORT2
(10pin Header)
MCLK
BICK
LRCK
DAUX
AK4115
(DIT)
PORT5
(10pin Header) AKD4115-A
ADC
MCLK
BICK
LRCK
DAUX
2. Asynchronous mode
S/PDIF
Optical, XLR or
BNC connector
PORT2
(10pin Header)
EMCK
EBICK
ELRCK
DAUX AK4115
(DIT)
AKD4115-A
ADC
EMCK
EBICK
ELRCK
DAUX
MCLK, BICK, LRCK and DAUX are input the via 10pin header (PORT5: DIT). The AKD4115-A can be
connected with the AKM’s ADC evaluation board via 10-pin cable.
a. Set-up of a Bi-phase output signal
TX0 and TXP0/TXN0 should not select an optical connector or a BNC connector at the same time.
a-1. The data outputted from TXP1/TXN1 can be selected by OPS12-10 bit.
Connector JP19 (TXP1) JP14 (TXN1)
Optical (PORT4) OPT BNC
XLR (J3) XLR XLR
BNC (J4) BNC BNC
Table 9. Set-up of TXP1/TXN1
a-2. As for TX0, only the loop back mode of RX corresponds. This mode is fixed to RX0 in parallel mode. In
serial mode, it can be selected by OPS02-00 bits.
Connector JP13 (TX0) JP19 (TXP1) JP14 (TXN1)
Optical (PORT4) OPT Open BNC
BNC (J4) BNC Open BNC
Table 10. Set-up of TX0

ASAHI KASEI [AKD4115-A]
<KM076403> 2006/08
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b. Set-up of clock input and output
b-1. In the case of synchronous mode (ASYNC bit="0" or Parallel mode)
The used signals are MCKO1, MCKO2, LRCK, BICK, ELRCK and DAUX.
The signal level outputted and inputted from PORT2 and PORT5 is 3.3V.
Clock PORT
MCLK PORT2
BICK PORT2
LRCK PORT2
DAUX PORT5
ELRCK PORT5(LRCK)
Table 11. Clock input and output
b-1-1. MCKO1/MCKO2
The output of MCKO1 pin or MCKO2 pin can be selected by JP12. The output frequency of MCKO1/MCKO2
sets up by OCKS 1-0.
Output
signal JP12 JP15 JP11
MCKO1 MCKO1 MCKO MCKO1
Default
MCKO2 MCKO2 MCKO MCKO2
Table 12. Selection of MCKO1/MCKO2
OCKS1 pin
(SW3_2)
OCKS0 pin
(SW3_3)
OCKS1 bit OCKS0 bit
(X’tal) MCKO1 MCKO2 fs (max)
0 0 256fs 256fs 256fs 96 kHz
Default
0 1 256fs 256fs 128fs 96 kHz
1 0 512fs 512fs 256fs 48 kHz
1 1 128fs 128fs 64fs 192 kHz
Table 13. Master Clock Frequency Select
b-1-2. Set-up of BICK and LRCK input and output
Please select SW 3_7 (DIR_I/O) according the setup of audio format of AK4115 (Refer to Table 7).
Audio format SW3_7 (DIR_I/O)
Slave mode 0 Default
Master mode 1
Table 14. Set-up DIR_I/O
b-1-3. A set up of ELRCK
As a reference clock of PLL, when using ELRCK clock, it inputs from PORT5 (LRCK).
JP16 JP17
When inputting by AC coupling AC AC
When inputting by CMOS level DC DC Default
Table 15. Set-up of ELRCK input

ASAHI KASEI [AKD4115-A]
<KM076403> 2006/08
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b-2. In the case of the asynchronous mode (ASYNC bit= "1" , This mode is supported in serial mode.)
The used signals are EMCK, X'tal, EBICK, ELRCK, and DAUX. These signal levels outputted / inputted from
PORT5 is 3.3V.
Clock PORT
MCLK PORT5
BICK PORT5
LRCK PORT5
DAUX PORT5
ELRCK PORT5
Table 16. Clock input and output
b-2-1. Set-up of Master clock
When EMCK is used
Output signal MSEL bit JP15
EMCK 1 EMCK
Table 17. Selection of EMCK
When X'tal is used as master clock
Output signal JP12 JP15 JP11
MCKO1 MCKO1 MCKO MCKO1
MCKO2 MCKO2 MCKO MCKO2
Table 18. Selection of MCKO1/MCKO2
b-2-2. Setup of BICK and LRCK input and output
Please set up SW 3_8 (DIT_I/O) according to the setup of audio format of AK4115 (Refer to Table 20).
JP16 and 17 are fixed to the “DC” side.
Audio format SW3_8 (DIT_I/O)
Slave mode 0 Default
Master mode 1
Table 19. DIT_I/O set-up
c. Set-up of audio data format
c-1. In case of synchronous mode.
Please refer to Table 7.
c-2. In case of asynchronous mode
ELRCK EBICK
Mode EDIF1 bit EDIF0 bit DAUX I/O I/O
4 0 0 24bit, Left justified H/L O 64fs O
5 0 1 24bit, I2S L/H O 64fs O
6 1 0 24bit, Left justified H/L I 64-128fs I Default
7 1 1 24bit, I2S L/H I 64-128fs I
Table 20. Audio data format in asynchronous mode

ASAHI KASEI [AKD4115-A]
<KM076403> 2006/08
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d. Set-up of PSEL, CM1 and CM0
d-1. In case of synchronous mode.
Please refer to Table 8.
d-2. In case of asynchronous mode
RX
CM1
bit
CM0
bit (UNLOCK) PLL X'tal Clock
source
Clock
I/O SDTO Clock source
Clock
I/O
0 0 - ON ON(Note 2) PLL
(RX) Note 3 RX
X’tal or
EMCK
(Note 5)
Note 4 Default
0 1 - OFF ON X’tal Note 3 “L”
X’tal or
EMCK Note 4
0 ON ON PLL
(RX) Note 3 RX X’tal or
EMCK Note 4
1 0
1 ON ON X’tal Note 3 “L”
X’tal or
EMCK Note 4
1 1 - ON ON X’tal Note 3 “L”
X’tal or
EMCK Note 4
ON: Oscillation (Power-up), OFF: STOP (Power-Down)
Note 2: When the X’tal is not used as clock comparison for sampling frequency detection (i.e. XTL1, 0 =
“1, 1”), the X’tal is OFF.
Note 3: MCKO1/2, BICK, LRCK
Note 4: EMCK OR X’tal, EBICK, ELRCK, DAUX
Note 5: When X’tal is OFF, the clock source supports EMCK only.
Table 21. Clock Operation Mode Select

ASAHI KASEI [AKD4115-A]
<KM076403> 2006/08
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B, C, U, V Inputs and output
B(block start), C(channel status), U(user data) and V(validity) are inputted via 10pin header (PORT3: BCUV).
When BCU_IO bit is set to “1”, they are input signals. And when BCU_IO bit is set to “0”, they are output signals.
In parallel mode, they are fixed to output signals. Pin arrangement of PORT3 has become like Figure 3.
PORT3
BCUV 6
5
10
1
GND GND GND GND GND
B C U VOUT VIN
Figure 3. PORT3 pin layout
Serial control
The AK4115 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect the included
10pin cable to PORT6 (uP-I/F) of the AKD4115-A. Take care of the direction of connector. There is a mark at
pin#1. And the pin layout of PORT6 is as Figure 4 shows.
Mode SW1_5 JP18
4 wire Serial L CDTO/CM0=“H” (Short)
IIC H
SDA (Short)
CM0=“L” (Short)
(Note)
Note: In IIC mode, the chip address is fixed to “01”.
Table 22. Set-up of Parallel mode and Serial mode
PORT6
uP I/F 10
9
2
1
NC
CDTO
CDTI
CCL
K
CSN
GND GND GND GND GND
Figure 4. PORT6 pin layout
The evaluation board also includes control software and a software operation procedure is included in the evaluation
board manual.