AKM AKD4552-A User manual

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 1 -
GENERAL DESCRIPTION
AKD4552-A is an evaluation board for the digital audio 24bit A/D and D/A converter, AK4552. The
AKD4552-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D
→D/A). The A/D section can be evaluated by interfacing with AKM’s DAC evaluation boards directly. The
AKD4552-A has the interface with AKM’s ADC evaluation boards. Therefore, it’s easy to evaluate the D/A
section. The AKD4552-A also has the digital audio interface and can achieve the interface with digital
audio systems via opt-connector.
Ordering guide
AKD4552-A --- Evaluation board for AK4552
FUNCTION
•DIT/DIR with optical input/output
•BNC connector for an external clock input
2.4 ~ 4.0V GND
LIN
RIN AK4552
AK4112B
(DIR)
AK4103A
(DIT)
Opt In
Opt Out
A/D, D/A Data
10pin Header
Clock
Generator
ROUT
LOUT
Figure 1. AKD4552-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
Evaluation board Rev.0 for AK4552
A
KD4552-
A

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 2 -
Analog Input Circuit
External analog signal fed through the BNC connector is terminated by a resistor of 560 ohms. The resistor value should
be properly selected in order to meet the output impedance of the signal source.
LIN(RIN)pi
n
R6(R4)
560
+
C4(C2)
10u
J4(J2)
LIN(RIN)
Figure 2. Input buffer circuit on board
* AKM assumes no responsibility for the trouble when using the circuit examples.
Analog Output Circuit
The AK4552 includes a combination of switched-capacitor filter (SCF) and continuous-time filter (CTF), so any external
filters are not required.
Operation sequence
1) Set up the power supply lines.
[VA] (orange) =2.4∼4.0V : for VA of AK4552 (typ. 3.0V)
[D2V] (orange) = 2.4 ∼4.0V : for D2V of 74LVC541 (typ. 3.0V)
[VCC] (red) = 3.6 ∼5.0V : for logic
[AGND] (black) = 0V : for analog ground (including VSS of AK4552)
[DGND] (black) = 0V : for logic ground
Each supply line should be distributed from the power supply unit.
D2V and VA must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4552 should be reset once bringing SW1 (PDN) “L” upon power-up.
Evaluation mode
Applicable Evaluation Mode
(1)Evaluation of A/D using DIT (Optical Link)
(2)Evaluation of D/A using DIR (Optical Link)
(3)Evaluation of loopback mode (default)
(4)Evaluation of D/A using A/D converted data
(5) Evaluation of A/D using D/A converted data
(6)All interface signals including master clock are fed externally.

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 3 -
(1)Evaluation of A/D using DIT (Optical Link)
PORT2 (DIT) and X2 (X’tal) is used. DIT generates audio bi-phase signal from received data and which is
output through optical connector (TOTX176). It is possible to connect AKM’s D/A converter evaluation boards
on the digital-amplifier which equips DIR input. Nothing should be connected to PORT1 (DIR), PORT3
(ROM). In case of using external clock through a BNC connector (J5), select EXT on JP11 (CLK) and short JP8
(XTE) and open JP13 (EXT). AK4112B should be powered down.
JP3
LRCK
DI
R
A
D
C
JP4
BCLK JP8 XTE JP13
DI
R
A
D
C
JP6
SDTI
DI
R
A
D
C
EXT
•Clock example
1-1) Normal speed of ADC (MCLK=256fs)
Master clock frequency example of X2 : X2 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2
MCKO
M2M1
JP7
SPEED JP
9
MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCF
S
JP12
LRFS
JP11
CLK
DI
R
EXT
XTL
1-2) Normal speed of ADC (MCLK=512fs)
Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
1-3) Double speed of ADC (MCLK=256fs)
Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M2M1
JP7
SPEED JP
9
MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCF
S
JP12
LRFS
JP11
CLK
DI
R
EXT
XTL

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 4 -
(2)Evaluation of D/A using DIR (Optical Link)
PORT1 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through
optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to
PORT3 (ROM). Set up “H” (AK4112B : PLL mode) for SW2-5 (CM0).
JP3
LRCK
DI
R
A
D
C
JP4
BCLK JP8 XTE JP13
DI
R
A
D
C
JP6
SDTI
DI
R
A
D
C
EXT
•Clock example
2-1) Normal speed of DAC (MCLK=256fs)
Input fs example for PORT1 : fs = 32kHz, 44.1kHz, 48kHz
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
SW2
MODE
12345
DEM0 DEM1 OCKS0 OCKS1 CM0
H
L
LLL
2-2) Normal speed of DAC (MCLK=512fs)
Input fs example for PORT1 : fs = 32kHz, 44.1kHz, 48kHz
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
SW2
MODE
12345
DEM0 DEM1 OCKS0 OCKS1 CM0
H
L
L
H
L
2-3) Double speed of DAC (MCLK=256fs)
Input fs example for PORT1 : fs = 64kHz, 88.2kHz, 96kHz
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
SW2
MODE
12345
DEM0 DEM1 OCKS0 OCKS1 CM0
H
L
LLL

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 5 -
2-4) 1/2 decimation of DAC (MCLK=128fs)
Input fs example for PORT1 : fs = 64kHz, 88.2kHz, 96kHz
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
SW2
MODE
12345
DEM0 DEM1 OCKS0 OCKS1 CM0
HH
LLL
(3) Evaluation of loopback mode (default)
Using U4 (AK4112B) and X1 (X’tal). Nothing should be connected to PORT1 (DIR), PORT3 (ROM). Set up
“H” (AK4112B : X’tal mode) for SW2-5 (CM0).
JP3
LRCK
DI
R
A
D
C
JP4
BCLK JP8 XTE JP13
DI
R
A
D
C
JP6
SDTI
DI
R
A
D
C
EXT
•Clock example
3-1)Normal speed (MCLK=256fs)
Master clock frequency example of X1 : X1 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
SW2
MODE
12345
DEM0 DEM1 OCKS0 OCKS1 CM0
H
L
LL
H
3-2)Normal speed (MCLK=512fs)
Master clock frequency example of X1 : X1 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
SW2
MODE
12345
DEM0 DEM1 OCKS0 OCKS1 CM0
H
L
L
HH

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 6 -
3-3)Double speed (MCLK=256fs)
Master clock frequency example of X1 : X1 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
SW2
MODE
12345
DEM0 DEM1 OCKS0 OCKS1 CM0
H
L
LL
H
(4)Evaluation of D/A using A/D converted data
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR). In case of
using external clock through a BNC connector (J5), select EXT on JP11 (CLK) and short JP8 (XTE) and open
JP13 (EXT). This mode corresponds to normal speed only.
JP3
LRCK
DI
R
A
D
C
JP4
BCLK JP8 XTE JP13
DI
R
A
D
C
JP6
SDTI
DI
R
A
D
C
EXT
•Clock example
4-1) Normal speed of DAC (MCLK=256fs)
Master clock frequency example of X2 : X2 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
SW2
MODE
12345
DEM0 DEM1 OCKS0 OCKS1 CM0
H
L
LLL
4-2) Normal speed of DAC (MCLK=512fs)
Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
SW2
MODE
12345
DEM0 DEM1 OCKS0 OCKS1 CM0
H
L
LLL

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
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(5)Evaluation of A/D using D/A converted data
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s D/A evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR).
JP3
LRCK
DI
R
A
D
C
JP4
BCLK JP8 XTE JP13
DI
R
A
D
C
JP6
SDTI
DI
R
A
D
C
EXT
•Clock example
5-1) Normal speed of ADC (MCLK=256fs)
DonotuseX2.
JP2
MCKO
M2M1
JP7
SPEED JP
9
MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCF
S
JP12
LRFS
JP11
CLK
DI
R
EXT
XTL
5-2) Normal speed of ADC (MCLK=512fs)
DonotuseX2.
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCF
S
JP12
LRFS
JP11
CLK
DI
R
EXT
XTL

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 8 -
(6) All interface signals including master clock are fed externally.
Under the following set-up, all external signals needed for the AK4552 to operate could be fed through PORT3
(ROM). In case of interfacing external sources to D/A converter, JP6 (SDTI) should be open. And in case of
using A/D data to externally, JP6 (SDTI) is set ADC side. When JP6 (SDTI) is open, the A/D data can be output
from the SDTO pin of PORT3 (ROM) at the same time if JP5 (SDTO) is short.
JP3
LRCK
DI
R
A
D
C
JP4
BCLK JP8 XTE JP13
DI
R
A
D
C
JP6
SDTI
DI
R
A
D
C
EXT
•Clock example
6-1) Normal speed, Double speed, 4 times speed of ADC and DAC
DonotuseX2.
JP2
MCKO
M2M1
JP7
SPEED JP9 MCLK
X2X1 X4X1
X4
X2
X1
X4X1
JP10
BCFS JP12 LRFS
JP11
CLK
DI
R
EXT
XTL
SW2
MODE
12345
DEM0 DEM1 OCKS0 OCKS1 CM0
H
L
LLL
DIP switch set up
Upper-side is “H” and lower-side is “L”.
[SW2] (MODE) : Sets the de-emphasis filter of AK4552 and clock mode of U4 (AK4112B).
No. Pin Name Mode
1 DEM0
2 DEM1 See Table 2.
3 OCKS0
4 OCKS1 See Table 3.
5 CM0 L : X’tal mode, H : PLL mode
Table 1. Set up SW2
DEM1 DEM0 Mode
L L 44.1kHz
L H OFF
H L 48kHz
H H 32kHz
default
Table 2. Set up of DEM0/1 of AK4552
No. OCKS1 OCKS0 MCKO1 MCKO2 fs (kHz)
0 L L 256fs 256fs 32, 44.1, 48, 96
1 H L 512fs 128fs 32, 44.1, 48
Table 3. Set up of OCKS0/1 for AK4112B

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
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Other jumper pins set up
[JP1] (GND): Analog ground and digital ground
open: separated
short: common (The connector “DGND” can be open.) <default>
[JP5] (SDTO): SDTO of AK4552
Always open. It is possible to short for evaluation mode 6.
The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Resets the AK4552. Keep “H” during normal operation.
[SW3] (DIR): Resets the AK4112B. Keep “H” during normal operation.
[SW4] (DIT): Resets the AK4103A. Keep “H” during normal operation.
Indication for LED
[LED1] (ERF): Monitor ERF pin of the AK4112B. LED turns on when some error has occurred to AK4112B.

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 10 -
MEASUREMENT RESULTS
[Measurement condition]
•Measurement unit : Audio Precision, System two Cascade
•MCLK : 256fs
•BCLK :64fs
•fs : 32kHz, 44.1kHz, 48kHz, 96kHz
•Bit : 24bit
•Band width : ADC : 10Hz ∼20kHz (Normal Speed), 10Hz ∼48kHz (Double Speed)
•Measurement Filter : DAC : 10Hz ∼20kHz (Normal Speed), 10Hz ∼40kHz (Double Speed)
•Power Supply : VA = VD = 3.0V
•Interface : DIT/DIR
•Temperature : Room
Parameter Result (Lch / Rch) Unit
ADC Analog Input Characteristics
S/(N+D) (-0.5dB Input)
fs=32kHz
fs=44.1kHz
fs=48kHz
fs=96kHz
87.8 / 87.9
88.5 / 88.5
89.2 / 89.2
89.5 / 89.4
dB
dB
dB
dB
D-Range (-60dB Input)
fs=32kHz, A-weighted
fs=44.1kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
96.1 / 96.1
97.1 / 97.1
97.5 / 97.5
93.3 / 93.3
dB
dB
dB
dB
S/N fs=32kHz, A-weighted
fs=44.1kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
96.1 / 96.1
97.1 / 97.1
97.6 / 97.6
93.3 / 93.3
dB
dB
dB
dB
Interchannel Isolation 118.5 / 118.7 dB
DAC Analog Output Characteristics
S/(N+D) (0dB Output)
fs=32kHz
fs=44.1kHz
fs=48kHz
fs=96kHz
88.3 / 89.2
88.1 / 88.8
88.3 / 89.2
85.6 / 86.3
dB
dB
dB
dB
D-Range (-60dB Output) fs=32kHz, A-weighted
fs=44.1kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
100.0 / 100.0
100.4 / 100.4
100.6 / 100.6
95.6 / 95.6
dB
dB
dB
dB
S/N
fs=32kHz, A-weighted
fs=44.1kHz, A-weighted
fs=48kHz, A-weighted
fs=96kHz
100.9 / 100.9
101.6 / 101.6
101.6 / 101.6
96.0 / 96.0
dB
dB
dB
dB
Interchannel Isolation 116.2 / 116.4 dB

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
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1. ADC (Normal Speed)
AKM AK4552 ADC THD+N vs. Input Level
VA=VD=3.0V, fs=44.1kHz, fin=1kHz
-100
-80
-98
-96
-94
-92
-90
-88
-86
-84
-82
d
B
F
S
-120 -10-110-100-90-80-70-60-50-40-30-20
dBr
Figure 1. THD+N vs. Input Level
AKM AK4552 ADC THD+N vs. Input Frequency
VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr
-100
-80
-98
-96
-94
-92
-90
-88
-86
-84
-82
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 2. THD+N vs. Input Frequency

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 12 -
AKM AK4552 ADC Linearity
VA=VD=3.0V, fs=44.1kHz, fin=1kHz
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
-120 +0-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
dBr
Figure 3. Linearity
AKM AK4552 ADC Frequency Response
VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr
-2
+0
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 4. Frequency Response

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 13 -
AKM AK4552 ADC Crosstalk
VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr
-140
-80
-135
-130
-125
-120
-115
-110
-105
-100
-95
-90
-85
d
B
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 5. Crosstalk
AKM AK4552 ADC FFT Plot
VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr, fin=1kHz
-180
+0
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 6. FFT Plot

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
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AKM AK4552 ADC FFT Plot
VA=VD=3.0V, fs=44.1kHz, Input=-60dBr, fin=1kHz
-180
+0
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 7. FFT Plot
AKM AK4552 ADC FFT Plot
VA=VD=3.0V, fs=44.1kHz, fin=None
-180
+0
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 8. FFT Plot

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 15 -
2. DAC (Normal Speed)
AKM AK4552 DAC THD+N vs. Input Level
VA=VD=3.0V, fs=44.1kHz, fin=1kHz
-120
-60
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
d
B
r
A
-120 +0-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
dBFS
Figure 1. THD+N vs. Input Level
AKM AK4552 DAC THD+N vs. Input Frequency
VA=VD=3.0V, fs=44.1kHz, Input=0dBFS
-120
-60
-115
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 2. THD+N vs. Input Frequency

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 16 -
AKM AK4552 DAC Linearity
VA=VD=3.0V, fs=44.1kHz, fin=1kHz
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
-120 +0-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
dBFS
Figure 3. Linearity
AKM AK4552 DAC Frequency Response
VA=VD=3.0V, fs=44.1kHz, Input=0dBFS
-0.5
+0.5
-0.4
-0.3
-0.2
-0.1
+0
+0.1
+0.2
+0.3
+0.4
d
B
r
A
2k 20k4k 6k 8k 10k 12k 14k 16k 18k
Hz
Figure 4. Frequency Response

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 17 -
AKM AK4552 DAC Crosstalk
VA=VD=3.0V, fs=44.1kHz, Input=0dBFS
-130
-80
-125
-120
-115
-110
-105
-100
-95
-90
-85
d
B
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 5. Crosstalk
AKM AK4552 DAC FFT Plot
VA=VD=3.0V, fs=44.1kHz, Input=0dBFS, fin=1kHz
-180
+0
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 6. FFT Plot

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 18 -
AKM AK4552 DAC FFT Plot
VA=VD=3.0V, fs=44.1kHz, Input=-60dBFS, fin=1kHz
-180
+0
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 7. FFT Plot
AKM AK4552 DAC FFT Plot
VA=VD=3.0V, fs=44.1kHz, fin=None
-180
+0
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
r
A
20 20k50 100 200 500 1k 2k 5k 10k
Hz
Figure 8. FFT Plot

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 19 -
3. ADC (Double Speed)
AKM AK4552 ADC THD+N vs. Input Level
VA=VD=3.0V, fs=96kHz, fin=1kHz
-120 -10-110-100-90-80-70-60-50-40-30-20
dBr
-100
-80
-98
-96
-94
-92
-90
-88
-86
-84
-82
d
B
F
S
Figure 1. THD+N vs. Input Level
AKM AK4552 ADC THD+N vs. Input Frequency
VA=VD=3.0V, fs=96kHz, Input=-0.5dBr
20 40k50 100 200 500 1k 2k 5k 10k 20k
Hz
-100
-80
-98
-96
-94
-92
-90
-88
-86
-84
-82
d
B
F
S
Figure 2. THD+N vs. Input Frequency

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 20 -
AKM AK4552 ADC Linearity
VA=VD=3.0V, fs=96kHz, fin=1kHz
-120 +0-110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10
dBr
-120
+0
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
d
B
F
S
Figure 3. Linearity
AKM AK4552 ADC Frequency Response
VA=VD=3.0V, fs=96kHz, Input=-0.5dBr
-2
+0
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
d
B
F
S
20 40k50 100 200 500 1k 2k 5k 10k 20k
Hz
Figure 4. Frequency Response