AKM AKD4558-A User manual

[AKD4558-A]
<KM116603> 2022/01
GENERAL DESCRIPTION
The AKD4558-A is an evaluation board for AK4558, which is 24/32bit, CODEC including 2ch ADC and
2ch DAC. The control settings of this board may be controlled via USB port, allowing for easy A/D and
D/A evaluation. BNC connectors are used for the input and output of the analog signals. This board also
has a digital interface which can be connected to the digital audio system via optical connector.
Ordering guide
AKD4558-A -- Evaluation board for AK4558
Control software included with package
FUNCTION
Clock generator circuit (AK4118A used)
Compatible with 2types of digital audio interface
- Optical input (x1) / Optical output (x1)
- Pin header for external data source
BNC connector for an external clock input
ADC 2ch input, DAC 2ch output
USB port and 10pin header for board control
Figure 1. AKD4558-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
AKD4558-A
AK4558 Evaluation Board Rev.3
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[AKD4558-A]
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Evaluation Board Diagram
Board Diagram
J700
SW401
U2
U1
J200
J202
SW500
SW400
T1 T2
J706 J701 J702 J703 J705 J704
PORT600
PORT1
PORT2
SW300
U60
SW501
J400
J201
J203
T3
Figure 2. AKD4558-A Board Diagram
Description
(1) U1 ( AK4558 )
24/32bit,2ch A/D Converter, 2ch D/A Converter.
(2) J200, J201, J202, J203 ( Analog data )
J200, J201 BNC connector : Analog Input for LIN, RIN.
J202, J203 BNC connector : Analog Output for LOUT, ROUT.
(3) PORT1, PORT2 ( Optical Connector )
PORT1 : Input optical signal to AK4118A.
PORT2 : Output optical signal from AK4118A.
(4) J700, J701, J702, J703, J704, J705, J706 ( Power supply )
J700 (+12V) : +12V Power Supply
J701 (AVDD1), J704 (D3.3V) : 3.3V Power Supply
J702 (TVDD) : 1.8V/3.3V Power Supply
J703 (VDD18) : 1.8V Power Supply
J705 (AVSS), J706 (DGND) : GND
(5) U2 ( AK4118A )
AK4118A has DIR, DIT and X’tal oscillator.
Transports input data to AK4558 when working in master mode, and output data from AK4558 when working in
slave mode.
(6) U60 ( PIC18F4550 )
USB control chip. Sets up AK4558 registers from PC via USB port (PORT600).
(7) J400 (BNC Connector)
Input external clock source.
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[AKD4558-A]
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(8) SW300 ( Dip-switch )
DIP type switch. Sets clock and audio format of AK4118A. DIF[2:0] used to set audio interface format and
OCKS[1:0] used to master clock frequency.
(9) SW500, SW501 ( Dip-switch )
DIP type switch. Sets clock and audio format and filter of AK4558.
(10)SW400 ( Toggle switch )
Toggle type-switch PDN for AK4558.
“H” : PDN = High
“L” : PDN = Low
(11)SW401 ( Toggle switch )
Toggle type-switch PDN for AK4118A.
“H” : PDN = High
“L” : PDN = Low
(12)T1, T2, T3 ( regulator )
Regulator for AK4558, AK4118A, Logic Circuit.
T1 : Regulated AVDD1, TVDD (3.3V) from +12V.
T2 : Regulated TVDD, VDD18 (1.8V) from +12V.
T3 : Regulated D3.3V (3.3V) from +12V.
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[AKD4558-A]
<KM116603> 2022/01
Evaluation Board Manual
Operation sequence
[1] Power supply line settings
[2] Jumped pins settings
[3] DIP switches settings
[4] Toggle switches settings
[5] Data format settings
[6] Register control (Serial control)
[7] Evaluation modes
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[AKD4558-A]
<KM116603> 2022/01
[1] Power supply line settings
(1-1) Power supply settings : Used the regulator (T1,T2,T3) <Default>
Set up the power supplied lines.
* Each supply line should be distributed from the power supply unit.
Name Color Setting (Typ) Function Comments Default Settings
J700 +12V Red +12V Regulator power supply Should always be connected +12V
J701 AVDD1 Red +3.3V AK4558 AVDD 3.3V regulator is used
(JP700=1pin-2pin short) by
default, when jack is used
(JP700=2pin-3pin short)
REG :
(JP700=1pin-2pin
short)
J702 TVDD Red +1.8 / +3.3V/ AK4558 TVDD, Logic
IC power supply
1.8V regulator is used
(JP702=1pin-2pin short and
JP701=REG1.8V) by default,
when 3.3V regulator is used
(JP702=1pin-2pin short and
JP701=REG3.3V), when jack
is used (JP702=2pin-3pin
short)
REG (1.8V) :
(JP702=1pin-2pin
short and
JP701=REG1.8V)
J703 VDD18 Yellow +1.8V AK4558 VDD18 1.8V regulator is used
(JP703=1pin-2pin short and
JP100=short) by default,
when LDO of AK4558 is
used (JP100=open), when
jack is used (JP703=2pin-3pin
short and JP100=short)
REG :
(JP703=1pin-2pin
short and
JP100=short)
J704 D3.3V Red +3.3V AK4118A 3.3V VDD,
Logic IC power supply
3.3V regulator is used
(JP704=1pin-2pin short) by
default, when jack is used
(JP704=2pin-3pin short)
REG :
(JP704=1pin-2pin
short)
J706 AVSS Black 0V Analog ground Should always be connected 0V
J705 DGND Black 0V Digital ground Should always be connected 0V
Table 1.Power supply line setting (default: used the regulator )
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[AKD4558-A]
<KM116603> 2022/01
(1-2) About jumper for power supply
The roles of the jumper for each power supply supplied from the regulator are as follows.
Connection of the jumper for power supply :
Name Function Comments Default Settings
JP700 AVDD1 Select regulator power supply
or jack for AVDD1
AVDD for AK4558:
JP700=1pin-2pin short : 3.3V regulator is used by default.
JP700=2pin-3pin short : Jack is used.
REG :
JP700=1pin-2pin short
JP701 REG3.3V
REG1.8V
Select regulator power supply
3.3V or 1.8V for TVDD
TVDD for AK4558 and Logic IC:
JP701=1pin-2pin short : 3.3V regulator is used.
JP701=2pin-3pin short : 1.8V regulator is used by default.
REG1.8V :
JP701=2pin-3pin short
JP702 TVDD Select regulator power supply
or jack for TVDD
TVDD for AK4558 and Logic IC:
JP702=1pin-2pin short : Regulator is used by default.
JP702=2pin-3pin short : Jack is used.
REG :
JP702=1pin-2pin short
JP703 VDD18 Select regulator power supply
or jack for VDD18
VDD18 for AK4558:
JP703=1pin-2pin short : 1.8V regulator is used by default.
JP703=2pin-3pin short : Jack is used.
REG :
JP703=1pin-2pin short
JP100 VDD18SEL Select External power supply or
LDO power supply of AK4558
for VDD18
VDD18 selector for AK4558:
JP100=short : External Power supply is used by default.
JP100=open : LDO of AK4558 is used.
External :
JP100=short
JP704 D3.3V Select regulator power supply
or jack for D3.3V
D3.3V for AK4118A and Logic IC:
JP704=1pin-2pin short : 3.3V regulator is used by default.
JP704=2pin-3pin short : Jack is used.
REG :
JP704=1pin-2pin short
JP705 GND Select connection / separation
between analog ground and
digital ground.
Analog ground / digital ground short or opem:
JP705=open: Separate analog ground from digital ground
JP705=short: Connect analog ground to digital ground by
default.
Short :
JP705=short
Table 2. Jumper for power supply
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[AKD4558-A]
<KM116603> 2022/01
[2] Jumped pins settings
No Names Default Functions
1 JP100 VDD18SEL Short Select Short / Open VDD18.
Open: VDD18 pin of AK4558 open.
Short: VDD18 pin of AK4558 input 1.8V. (default)
2 JP400 EXT Open Open: No input (default)
Short: External MCLK(JACK:J400 EXT) input.
3 JP401 BICK-SEL DIR Select input to AK4558 (U1) BICK Buffer
Case of MCLK=256fs
MCLK/2: 128fs divider
MCLK/4: 64fs divider
MCLK/8: 32fs divider
MCLK/16: 16fs divider
DIR: DIR-AK4118-BICK (default)
PORT3: Pin Header PORT3-BICK
Open: No signal
4 JP402 LRCK-SEL DIR Select input to AK4558 (U1) LRCK Buffer
Case of MCLK=256fs
MCLK/128: 2fs divider
MCLK/256: 1fs divider
MCLK/512: 0.5fs divider
DIR: DIR-AK4118-LRCK (default)
PORT3: Pin Header PORT3-LRCK
Open: No signal
5 JP403 MCKI-SEL DIR PORT3: Pin Header PORT3-MCLK
EXT: External MCLK (JACK:J400 EXT) input.
GND: GND
DIR: DIR-AK4118-MCKI (default)
6 JP404 BICK-PHASE THR
(1pin-2pin
short)
Select polarity (non-inverted output / inverted output) of
BICK_SEL outputs.
THR: Non-inverted output. (default)
INV: Inverted output.
7 JP405 SDTI-SEL DIR Select input to AK4558 (U1) SDTI
DIR: DIR-AK4118-SDTO (default)
PORT4: Pin Header PORT4-SDTI
GND: Digital ground
8 JP406 TDMI-SEL Open Select connect to AK4558 (U1) TDMI/TDMO
DIR: DIR-AK4118-SDTO (default)
TDMI: Pin Header PORT4-TDMI/O
TDMO: Pin Header PORT4-TDMI/O
9 JP407 DAUX_SEL Short Select input to DIT:AK4118 (U2) DAUX
short: AK4558-SDTO is used. (default)
open: No signal
10 JP408 TDMI/O SEL Open Select input/output for AK4558 (U1) TDMI/O
DIR: DIR-AK4118-SDTO
TDMI: TDMI of AK4558 (PinHeader PORT4-TDMI/O)
TDMO: TDMO of AK4558 (PinHeader PORT4-TDMI/O)
open: No signal (default)
11 JP500 PMADL/SCLSEL SCL Select input to AK4558 (U1) PMADL/SCL
SCL: SCL signal input to AK4558. (default)
PMADL: PMADL signal of SW500 input to AK4558.
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[AKD4558-A]
<KM116603> 2022/01
12 JP501 PMADR/SDASEL SDA Select input to AK4558 (U1) PMADR/SDA
SDA: SDA signal input to AK4558. (default)
PMADR: PMADR signal of SW500 input to AK4558.
13 JP502 PMDAL/CAD0SEL CAD0 Select input to AK4558 (U1) PMDAL/CAD0
CAD0: CAD0 signal input to AK4558. (default)
PMDAL: PMDAL signal of SW500 input to AK4558.
14 JP503 PMDAR/CAD1SEL CAD1 Select input to AK4558 (U1) PMDAR/CAD1
CAD1: CAD1 signal input to AK4558. (default)
PMDAR: PMDAR signal of SW500 input to AK4558.
15 JP504 TDMI/CKS0SEL CKS00 Select connect to AK4558 (U1) TDMI/CKS0
CKS00: CKS00 signal of SW501 input to AK4558. (default)
TDMI: TDMI/O signal connect to AK4558.
16 JP505 TDMI I/O SEL TDMO0 Select connect to AK4558 (U1) TDMI/TDMO
TDMO: TDMO signal connect to AK4558. (default)
TDMI: TDMI/O signal connect to AK4558.
17 JP700 AVDD1-SEL REG
(1pin-2pin
short)
Select power supply to AVDD
REG(1pin-2pin short): Regulator T1 (default)
(When regulator “T1” is selected, power supply jack
“AVDD1” should be open.)
Jack(2pin-3pin short): Power supply jack J701 “AVDD1”
18 JP701 TVDDVOL-SEL REG1.8V
(2pin-3pin
short)
Select power supply voltage of TVDD
REG3.3V(1pin-2pin short): Regulator T1 (default)
REG1.8V(2pin-3pin short): Regulator T2 (default)
19 JP702 TVDD-SEL TVDD
(1pin-2pin
short)
Select power supply to TVDD
REG(1pin-2pin short): Regulator T1/T2 (default)
(When regulator “T1/T2” is selected, power supply jack
“TVDD” should be open.)
Jack(2pin-3pin short): Power supply jack J702 “TVDD”
20 JP703 VDD18-SEL VDD18
(1pin-2pin
short)
Select power supply to VDD18
REG(1pin-2pin short): Regulator T2 (default)
(When regulator “T2” is selected, power supply jack
“VDD18” should be open.)
Jack(2pin-3pin short): Power supply jack J703 “VDD18”
21 JP704 D3.3V-SEL REG
(1pin-2pin
short)
Select power supply to D3.3V
REG(1pin-2pin short): Regulator T3 (default)
(When regulator “T3” is selected, power supply jack
“D3.3V” should be open.)
Jack(2pin-3pin short): Power supply jack J704 “D3.3V”
22 JP705 GND Short Select connection / separation between analog ground and
digital ground.
Open: Separate analog ground from digital ground
Short: Connect analog ground to digital ground (default)
Table 3. Main board Jumper pin setting
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[AKD4558-A]
<KM116603> 2022/01
[3] DIP switches settings
(3-1). Setting for SW300 (Sets AK4118 (U2) audio format and master clock setting)
No. Switch Name Function default
1 DIF0 Set-up of DIF0 pin. (in parallel mode) H
2 DIF1 Set-up of DIF1 pin. (in parallel mode) L
3 DIF2 Set-up of DIF2 pin. (in parallel mode) H
4 OCKS1 Set-up of OCKS1 pin. (in parallel mode) L
5 OCKS0 Set-up of OCKS0 pin. (in parallel mode) L
Table 4. SW1 Setting
Mode DIF2 pin
SW
300
_1
DIF1 pin
SW
300
_2
DIF0 pin
SW
300
_3
DAUX SDTO LRCK BICK
DIF2 bit
DIF1 bit
DIF0 bit
I/O
I/O
0 0 0 0 24bit, Left
justified
16bit, Right
justified
H/L O 64fs O
1 0 0 1 24bit, Left
justified
18bit, Right
justified
H/L O 64fs O
2 0 1 0 24bit, Left
justified
20bit, Right
justified
H/L O 64fs O
3 0 1 1 24bit, Left
justified
24bit, Right
justified
H/L O 64fs O
4 1 0 0 24bit, Left
justified
24bit, Left
justified
H/L O 64fs O
5 1 0 1 24bit, I2S 24bit, I2S L/H O 64fs O default
6 1 1 0 24bit, Left
justified
24bit, Left
justified
H/L I 64-128fs I
7
1
1
1
24bit, I
2
S
24bit, I
2
S
L/H
I
64
-
128fs
I
Table 5. Audio format
OCKS1 pin
SW300_4
OCKS0 pin
SW300_5 (X’tal) MCKO1 MCKO2 fs (max)
OCKS1 bit OCKS0 bit
0 0 256fs 256fs 256fs 96 kHz default
0 1 256fs 256fs 128fs 96 kHz
1 0 512fs 512fs 256fs 48 kHz
1 1 128fs 128fs 64fs 192 kHz
Table 6. Master Clock Frequency Select
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[AKD4558-A]
<KM116603> 2022/01
(3-2). Setting for SW500 (Sets AK4558 (U1) )
No. Switch Name Function default
1 PMADL ADC Lch Power Management Pin in parallel control mode. (PS pin =”H”) L: ADC Lch Power Down
H: Normal Mode
H
2 PMADR ADC Rch Power Management Pin in parallel control mode. (PS pin =”H”) L: ADC Rch Power Down
H: Normal Mode
H
3 PMDAL DAC Lch Power Management Pin in parallel control mode. (PS pin =”H”) L: DAC Lch Power Down
H: Normal Mode
H
4 PMDAR DAC Rch Power Management Pin in parallel control mode. (PS pin =”H”) L: DAC Rch Power Down
H: Normal Mode
H
5 CAD1 Chip Address1 Pin in serial control mode. (PS pin =”L”) L
6 CAD0 Chip Address0 Pin in serial control mode. (PS pin =”L”) L
7 LOPS
DAC Lch/Rch Output (LOUT/ROUT) Power Save Mode Pin in parallel
control mode. (PS pin =”H”)
L: Normal Mode
H: DAC LOUT/ROUT Power Save Mode
L
8 LDOE LDO Enable Pin L: LDO disable
H: LDO enable
L
Table 7. SW500 Setting
(3-3). Setting for SW501 (Sets AK4558 (U1) )
No. Switch Name Function default
1 PS Control mode select pin. L: I2C Bus control mode.
H: Parallel control mode.
L
2 CKS3 Mode Setting Pin #3 L
3 CKS2 Mode Setting Pin #2 H
4 CKS1 Mode Setting Pin #1 H
5 CKS0 Mode Setting Pin #0 H
6 - Not used -
7 - Not used -
8 - Not used -
Table 8. SW501 Setting
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