AKM AKD7736A-A User manual

[AKD7736A-A]
<KM113102> 2012/12
- 1 -
GENERAL DESCRIPTION
The AKD7736A-A is an evaluation board for the AK7736A that is an audio processor with a 2ch SRC. This
board consists of a main board and a sub board. It is possible to control by a PC via USB port. This board
has digital interfaces enabling to interface with digital audio systems via optical connector, ADC-Port,
DAC-Port and EXT-Port.
■Ordering guide
AKD7736A-A --- AK7736A Evaluation board
The AK77XX-HF-CONTROL-BOX, Control software and USB cable are
included in this package.
FUNCTION
Read/Write access to PRAM, CRAM, OFFRAM and registers of the AK7736A
Compatible with 2 types of digital audio interface
- Optical input (x1) / Optical output (x1)
- 10-pin header (x2) and 44-pin header (x1) for interface with external data source
USB port for board control
FPGA
(XC95288XL)
ADC DAC
10 Pin Header
Regulator
GND+3.3V
1.8V
CONTROL
Opt In
Opt Out
AK4118A
EXT
44 Pin Header
10 Pin Header
AK7736A
Figure 1. AKD7736A-A Block Diagram
AK7736A Evaluation Board Rev.0
AKD7736A-A

[AKD7736A-A]
<KM113102> 2012/12
- 2 -
Evaluation Board Diagram
■Board Diagram
Figure 2. AKD7736A-A Board Diagram
(1)
(2)
(3) (5) (6)
(4)
(7)
(8)
(9)
(13)
(12)
(14)
(10)
(11)
(15)
(16)
(17)
(18)
(19)

[AKD7736A-A]
<KM113102> 2012/12
- 3 -
■Description
No. Name Function
(1) AKD7736A-A-SUB Connector for the AKD7736A-A-SUB board.
(2) Interface select
(3-pin header x 13)
Interface selector of the AK7736A.
EXT: EXT port;
Xilinx: ADCport, DACport
No Name AK7736A
JP15 DI4 SDIN4
JP18 DI3 SDIN3
JP11 DI2C SDIN2C
JP10 DI2B SDIN2B
JP9 DI2A SDIN2A
JP8 DI1 SDIN1
JP20 LR3 LRCLKI3
JP19 BTI3 BITCLKI3
JP17 LR2 LRCLKI2/JX2
JP16 BTI2 BITCLKI2/JX1
JP14 LR1 LRCLK1
JP13 BT1 BITCLK1
JP12 XT1 XTI
(3) EXT port
J1 (44-pin header)
44-pin header for external interface
When using this connector, jumper pins of (2) must be shorted to Xilinx.
(4) XC95288XL
U6(xilinx)
FPGA for data path controlling
Various operations are available by setting the control software.
(5) DAC port
JP3 (10-pin header)
10-pin header for external interface
Interfacing to external digital audio devices.
Pin I/O Function Pin I/O Function
1 O MCLK 2 P GND
3 O BITCLK 4 P GND
5 O LRCLK 6 O SDTI1
7 - Open 8 O SDTI2
9 O SDTI4 10 O SDTI3
(6) ADC port
JP2 (10-pin header)
10-pin header for external interface
Interfacing to external digital audio devices.
Pin I/O Function Pin I/O Function
1 I/O MCLK 2 P GND
3 I/O BITCLK 4 P GND
5 I/O LRCLK 6 - Open
7 I SDTO1 8 - Open
9 I SDTO2 10 - open
(7) JTAG port
JP21(10-pin header)
10-pin header for Xilinx access
Do not use.
(8) CONTROL port
JP1 (10-pin header)
10-pin header for AK7736A control
Normally, connect the AKD77XX-HF-CONTROL-BOX to interface to a PC
via USB port.
Pin I/O Function Pin I/O Function
1 P GND 2 P +3.3V
3 I HOST 4 I RQN
5 I SCK/SCL 6 I SI
7 I/O XCS/SDA 8 O SO
9 I CSN 10 - RESET

[AKD7736A-A]
<KM113102> 2012/12
- 4 -
(9) 5 DIP Switches
S2
DIP switches for the AK7736A pin setting (L/H).
No Name AK7736A
1 TESTI3 TESTI3(6 pin)
2 TESTI1 TESTI1(1 pin)
3 TESTI2 TESTI2(46 pin)
4 JX0 JX0(43 pin)
5 I2C I2CSEL(19 pin)
(10) VDD Jumper
JP6 (2-pin header)
Jumper pin for VDD power supply of the AK7736A.
Open: Supply from the VDD test pin
Short: +3.3V
(11) P-TVDD Jumper
JP5 (3-pin header)
Jumper pin for S2 and level shifter power supply
3.3VShort: +3.3V
1.8VShort: +1.8V
(12) Optical Connector
PORT1, PORT2
SPDIF-IN (Input): Optical digital signal (Fs: 8~48kHz) is input to the AK4118A.
SPDIF-OUT (Output): Optical digital signal (Fs: 8~48kHz) is output from the
AK4118A.
(13) AK4118A
U1
AK4118A (Digital Audio Transceiver)
(14) 7 DIP Switches
S1
DIP Switch for pin settings (L/H) of the AK4118A.
Refer to the “AK4118A Setting” for details
No Name AK4118A
1 CM0 CM0(32 pin)
2 CM1 CM1(33 pin)
3 OCKS0 OCKS0(35 pin)
4 OCKS1 OCKS1(34 pin)
5 DIF0 DIF0(3 pin)
6 DIF1 DIF1(5 pin)
7 DIF2 DIF2(7 pin)
(15) Toggle Switch
SW1
Toggle Switch for selecting clock source to the AK4118A-XTI.
XTL: Crystal Clock
TX-CLK: External Clock
(16) P-DVDD Jumper
JP7 (2-pin header)
Jumper Pin for selecting power supply to IC’s except the AK7736A.
Open: Supply from the P-DVDD test pin
Short: +3.3V
(17) +3.3V power supply
TM1
Power Supply Connector
Supply +3.3V.
(18) GND
TM2
Connect to GND
(19) TVDD Jumper
JP4 (2-pin header)
Jumper pin for selecting power supply to the TVDD pin of the AK7736A
Open: Supply from the TVDD test pin
Short: P-TVDD
Table 1. Main Board Functions (Bold: Default Setting)

[AKD7736A-A]
<KM113102> 2012/12
- 5 -
Evaluation Board Manual
■Operation Sequence
(1) Set up the power supply lines.
[The jumper pins should be set as following]
JP4
TVDD
(Short)
JP6
VDD
(
Short
)
JP7
P-DVDD
(
Short
)
JP5
PIC-VDD-SEL
1.
8
V3.3V
Set up the power supply lines.
N
ame Colo
r
Volta
g
e Commen
t
Attention
+3.3V Red +3.3V Regulator,
Input/Output buffe
r
Should always be connected.
GND Blac
k
0V Ground Should alwa
y
s be connected.
Table 2. Set Up of Power Supply Lines
Each supply line should be distributed separately from the power supply unit. The regulator on the board that
converts 3.3V to 1.8V can also supply TVDD of the AK7736A.
(2) Set up the evaluation mode, jumper pins and connectors. (according to the following section)
(3) Connect the board to a PC with a USB cable via the AKD77XX-HF-CONTROL-BOX (called
“CONTROL-BOX” hereafter) which is included in this package. It is required to push down the reset button
(yellow) of the CONTROL-BOX to initialize the USB control chip.
(4) Power On
(5) Start the control software and set up registers by PC. (according to the following section)
■Evaluation Mode
In case of evaluating theAK7736A by using the AK4118A, it is necessary that audio interface format of both
devices are matched. Refer to the datasheet for audio interface format of the AK7736A, and refer to
“Jumper Pin and Switch Setting” for audio interface format of the AK4118A.
Applicable Evaluation Mode
(1) Digital-to-Digital Evaluation using ADC-Port and DAC-Port: CKM Master Mode = 0/1
(2) Digital-to-Digital Evaluation using ADC-Port and DAC-Port: CKM Slave Mode = 2/3/4/5
Refer to the “Control Software” section of this manual and the datasheet of the AK7736A for FPGA, the AK4118A
and control register setting of the AK7736A.

[AKD7736A-A]
<KM113102> 2012/12
- 6 -
(1) Digital-to-Digital Evaluation using ADC Port and DAC Port: CKM Master Mode = 0/1
ADC-Port and DAC-Port are used on this evaluation. Set the clock mode of the AK7736A to CKM Master Mode
0 (12.288MHz) or CKM Master Mode 1 (18.432MHz). The AK7736A outputs BICK and LRCK to the ADC-Port
and DAC-Port by setting the FPGA. The ADC-Port inputs data to the SDIN1, SDIN2A, SDIN2B, SDIN2C,
SDIN3 or SDIN4 pin. The DAC-Port output data from the SDOUT1, SDOUT2A, SDOUT2B, SDOUT3 or
SDOUT4 pin.
[Jumper Pins Setting]
JP1
XTI-SEL
CRYEXT
For digital output, optical connector PORT2 (SPDIF-OUT) is also available. The following setting must be made
and the FPGA setting should be changed when using the SPDIF-OUT instead of the DAC-Port. Refer to
“AK4118A Setting” for detail setting of the AK4118A.
Main Board
Jumper / Switch Setting (Default)
SW1 (AK4118A
Clock) “TX-CLK”
S1(AK4118A Setting) 1->7=LHLLLHH
Table 3. Configuration of the AK4118A switch in Master Mode
(2) Digital-to-Digital Evaluation using ADC Port and DAC Port: CKM Slave Mode = 2/3/4/5
ADC-Port and DAC-Port are used on this evaluation. Set the clock mode of AK7736A to CKM Slave Mode
2/3/4/5. ADC-Port supplies MCLK, BICK, LRCK and digital data to the AK7736A. (MCLK is needed in CKM
Slave Mode 2 only)
[Jumper Pins Setting]
JP10
XTI-SEL
CRYEXT
(MCLK is needed in CKM Slave Mode 2 only)
For digital input and output, optical connector PORT1 (SPDIF-IN) and PORT2 (SPDIF-OUT) are available,
respectively. The following setting must be made and the FPGA setting should be changed when using these
connectors. Refer to “AK4118A Setting” for detail setting of the AK4118A.
Main Board
Jumper / Switch Setting (Default)
SW1 (AK4118A
Clock) “XTL”
S1(AK4118A Setting) 1->7=LHLLLLH
Table 4. Configure the AK4118A switch at the Slave Mode

[AKD7736A-A]
<KM113102> 2012/12
- 7 -
■Board control
The AKD7736A-A can be controlled by a PC via USB port. Connect the CONTROL-BOX included in this package to
the AKD7736A-A with a 10-pin flat cable, and connect the CONTROL-BOX to a PC with a USB cable. The 10-pin
flat cable should be connected in the direction that the side with a bump meets a marking, that says “CONTROL”, on
the main board of the AKD7736A-A.
Figure 1. Direction of the 10-pin Flat Cable
The interface setting is made by jumper pins of the CONTROL-BOX and the I2CSEL pin of the AK7736A.
SPI(Serial) Setting I2C Setting
Figure 2. Configuration of the CONTROL-BOX
Control software is different depending on the interface setting.
The software operation sequence is shown in this manual.
■Indication for LED
[LED] D1: The status of AK7736A’s PDN pin is shown. “H” →Light off; “L” →Light on.
CONTROL
Open
Short
Open
Short
Short
Open
Short
Open

[AKD7736A-A]
<KM113102> 2012/12
- 8 -
■Jumper Pin and Switch Setting
<Main board>
Jumper / Switch Setting (Default) Note
SW1 (AK4118A
Clock) “TX-CLK”
AK4118A Clock Source
“XTL”: Crystal Clock
“TX-CLK”: External Clock
S1(AK4118A Setting) 1->7=LHLLLHH Refer to “AK4118A Setting”
S2(AK7736A Setting) 1->5=LLLLL Refer to (9) in Table 1
JP4 (TVDD) Short AK7736A TVDD
JP5 (P-TVDD) “3.3V” Refer to (11) in Table 1
JP6 (VDD) Short AK7736A VDD
JP7 (P-DVDD) Short Peripheral DVDD
JP8 (DI1) “Xilinx”
Refer to (2) in Table 1
JP9 (DI2A) “Xilinx”
JP10 (DI2B) “Xilinx”
JP11 (DI2C) “Xilinx”
JP12 (XTI) “Xilinx”
JP13 (BTI1) “Xilinx”
JP14 (LR1) “Xilinx”
JP15 (DI4) “Xilinx”
JP16 (BTI2) “Xilinx”
JP17 (LR2) “Xilinx”
JP18 (DI3) “Xilinx”
JP19 (BTI3) “Xilinx”
JP20 (LR3) “Xilinx”
Table 5. Setting of Jumper Pins on Main Board
<Sub board>
Jumper/ Switch Setting (Default) Note
JP1 (XTI-SEL) “CRY”
AK7736A Clock Source
“CRY”: Crystal Clock
“EXT”: External Clock
Table 6. Setting of Jumper Pins on Sub Board

[AKD7736A-A]
<KM113102> 2012/12
- 9 -
<AK4118A Setting>
OCKS1 OCKS0 MCKO1 MCKO2 X’tal Fs(max)
0 0 256fs L 256fs 96kHz default
0 1 256fs L 256fs 96kHz
1 0 512fs L 512fs 48kHz
1 1 128fs L 128fs 192kHz
Table 7. AK4118A-OCKS[1:0]
CM1 CM0 Clock
source MCKO1 MCKO2 SDTO
0 0 PLL PLL L RX
0 1 X’tal X’tal X’tal DAUX
1 0 PLL PLL L RX default
1 1 X’tal X’tal X’tal DAUX
Table 8. AK4118A-CM[1:0]
DIF2 DIF1 DIF0 DAUX SDTO LRCK BICK
0 0 0 24bit,Left justified 16bit,Right justified H/L O 64fs O
0 0 1 24bit,Left justified 18bit,Right justified H/L O 64fs O
0 1 0 24bit,Left justified 20bit,Right justified H/L O 64fs O
0 1 1 24bit,Left justified 24bit,Right justified H/L O 64fs O
1 0 0 24bit,Left justified 24bit,Left justified L/H O 64fs O
1 0 1 24bit,I2S 24bit,I2S H/L
O 64fs O
1 1 0 24bit,Left justified 24bit,Left justified L/H I 64fs I default
1 1 1 24bit,I2S 24bit,I2S H/L
I 64fs I
Table 9. AK4118A-DIF[2:0]

[AKD7736A-A]
<KM113102> 2012/12
- 10 -
■Digital Input Circuit (External DIR: PORT1)
Figure 3. Digital Input Circuit
For digital input SPDIF-IN, optical connector PORT1 is available.
■Digital Output Circuit (External DIT: PORT2)
Figure 4. Digital Output Circuit
For digital output SPDIF-OUT, optical connector PORT2 is available.