AKM AKD4753-A User manual

[AKD4753-A]
AKD4753-A
A
K4753 Evaluation Board Rev.2
GENERAL DESCRIPTION
The AKD4753-A is an evaluation board for AK4753, 2-in, 4-out CODEC with DSP Functions. The
AKD4753-A has the Digital Audio I/F and can achieve the interface with digital audio systems via
optical connector.
■Ordering guide
AKD4753-A --- Evaluation Board for AK4753
(Control software and USB cable are packed with this.)
FUNCTION
•RCA connectors for analog audio input/output
•Optical connector for digital audio input
•On-board digital audio interface (AK4118A)
•Potentiometers for Volume and Bass gain control
•USB connector for serial control interface
•1k bits EEPROM
AK4753
AINL
DSP
LOUT1
ROUT2
ROUT1
LOUT1
AINR
3.3V
10 Pin Header
EEPROM
PIC4550
I2C
10 Pin Header
Regulator
USB 3.3V
Regulator
PORT1
Opt In
PORT4
USB
PORT3 PORT2
AK4118A
(DIR)
SAIN2
SAIN1
Volume
Bass Gain
Potentiometer
GND+5V
A
VDDDVDDD3.3V
Figure 1. AKD4753-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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[AKD4753-A]
Evaluation Board Manual
■Operation sequence
1) Set up the power supply lines
Name of
jack
Color of
jack
Default
Setting
Used for Open / Connect
Regulator T2: Should be always connected When default
setting.
+5V Red AVDD, DVDD of AK4753,
Digital Logic
+5V
Should be always connected when AVDD of
AK4753 is not supplied from regulator T2.
AVDD Red AVDD of AK4753 Open
In this case “JP13” is set to “Open”.
Should be always connected when DVDD of
AK4753 is not supplied from regulator T2.
DVDD Red DVDD of AK4753 Open
In this case “JP14” is set to “Open”.
Should be always connected when Digital
Logic is not supplied from regulator T2.
D3.3V Red Digital Logic Open
In this case “JP15” is set to “Open.”
Should be always connected.
AGND Black Analog Ground GND
Should be always connected.
DGND Black Digital Ground GND
Table 1. Set up the power supply lines
Each supply line should be distributed from the power supply unit.
2) Setup the evaluation mode, jumper pins
(2-1) External Slave Mode
(a) Evaluation of using DIR of AK4118A <default>
(b) All interface signals including master clock are fed externally
(2-2) External Master Mode
(a) Evaluation of using DIR of AK4118A
(2-3) PLL Slave Mode
(a) Evaluation of using DIR AK4118A
(b) All interface signals including master clock are fed externally
(2-4) PLL Master Mode
(a) All interface signals including master clock are fed externally
3) Power on
The AK4118A should be reset once bringing S1 (AK4118-PDN) “L” upon power-up.
The AK4753 should be reset once bringing S2 (AK4753-PDN) “L” upon power-up.
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[AKD4753-A]
■Evaluation mode
1) External Slave Mode
(a) Evaluation of D/A using DIR of AK4118A. <default>
In case of AK4753 evaluation using AK4118A, it is necessary to correspond to audio interface format for
AK4753 and AK4118A.Please use AK4118A in the master mode.
PORT1(RX) is used. Nothing should be connected to PORT3(DSP) and J7(MCKI).
EX
T
DIR
JP4
AK4753-BICK JP7
AK4753-MCLK
JP5
AK4753-SDATA JP6 AK4753-LRCK
MCKI DIR EXT
JP3
XTL EXT GND
EX
T
DIR EX
T
DIR
Figure 2. Setting of D/A using DIR of AK4118A
(b) All interface signals including master clock are fed externally.
PORT3(DSP) is used. Nothing should be connected to PORT1(RX) and J7(MCKI).
EX
T
DI
R
JP4
AK4753-BICK JP7
AK4753-MCLK
JP5
AK4753-SDATA JP6 AK4753-LRCK
MCKI DIR EXT
JP3
XTL EXT GND
EX
T
DIR EX
T
DI
R
JP17
MODE_SEL
SLAVEMASTE
R
JP18
MCLK_SEL
MCLKMUTEN
Figure 3. Setting of all interface signals including master clock are fed externally
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[AKD4753-A]
2) External Master Mode
(a) Evaluation of D/A using DIR of AK4118A.
In case of AK4753 evaluation using AK4118A, it is necessary to correspond to audio interface format for
AK4753 and AK4118A.Please use AK4118A in the slave mode.
PORT1(RX) is used. Nothing should be connected to PORT3(DSP) and J7(MCKI).
EX
T
DIR
JP4
AK4753-BICK JP7
AK4753-MCLK
JP5
AK4753-SDATA JP6 AK4753-LRCK
MCKI DIR EXT
JP3
XTL EXT GND
EX
T
DIR EX
T
DIR
Figure 4. Setting of D/A using DIR of AK4118A
3) PLL Slave Mode
(a) Evaluation of D/A using DIR of AK4118A.
In case of AK4753 evaluation using AK4118A, it is necessary to correspond to audio interface format for
AK4753 and AK4118A.Please use AK4118A in the master mode.
PORT1(RX) is used. Nothing should be connected to PORT3(DSP) and J7(MCKI).
EX
T
DIR
JP4
AK4753-BICK JP7
AK4753-MCLK
JP5
AK4753-SDATA JP6 AK4753-LRCK
MCKI DIR EXT
JP3
XTL EXT GND
EX
T
DIR EX
T
DIR
Figure 5. Setting of D/A using DIR of AK4118A
(b) All interface signals including master clock are fed externally.
PORT3(DSP) is used. Nothing should be connected to PORT1(RX) and J7(MCKI).
EX
T
DI
R
JP4
AK4753-BICK JP7
AK4753-MCLK
JP5
AK4753-SDATA JP6 AK4753-LRCK
MCKI DIR EXT
JP3
XTL EXT GND
EX
T
DIR EX
T
DI
R
JP17
MODE_SEL
SLAVEMASTE
R
JP18
MCLK_SEL
MCLKMUTEN
Figure 6. Setting of all interface signals including master clock are fed externally
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[AKD4753-A]
4) PLL Master Mode
(a) All interface signals including master clock are fed externally.
(a-1) Setup the MCKI.
X1(X’Tal) or J7(MCKI) are used. Nothing should be connected to PORT1(RX).
(a) When using X1(X’Tal) (b) When using J7(MCKI)
JP7
AK4753-MCLK
MCKI DIR EXT
JP3
XTL EXT GND
JP7
AK4753-MCLK
MCKI DIR EXT
JP3
XTL EXT GND
Figure 7. Setup the MCKI
(a-2) Other Setting (BICK, LRCK and SDATA).
PORT3(DSP) is used. Nothing should be connected to PORT1(RX).
EX
T
DI
R
JP4
AK4753-BICK JP5
AK4753-SDATA JP6 AK4753-LRCK
EXTDIR EX
T
DI
R
JP17
MODE_SEL
SLAVEMASTE
R
JP18
MCLK_SEL
MCL
K
MUTEN
Figure 8. Other Setting (BICK, LRCK and SDATA)
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[AKD4753-A]
■EEP-ROM operation setting
1) When you write the setting from Control Soft to EEPR M.O
5)
At this time, please fix the EXTEE switch (See Table to "L".
JP10 PC-SD
A
JP8 PC-SCL
JP9
WP
.
"L
Figure 9. Setting of EEP-ROM operation1
2) When you load the setting from EEPROM to AK4753
Please change the EXTEE switch (See Table 5) from " to "H" after setting JP8, JP9 and JP10.
JP10 PC-SD
A
JP8 PC-SCL
JP9
WP
Figure 10. Setting of EEP-ROM operation2
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[AKD4753-A]
■Jumper pins setting
[JP1 (SAIN1)]: The selection of connection to SAIN1 pin.
SHORT : Connection. (Default)
OPEN : Unconnection.
[JP2 (SAIN2)]: The selection of connection to SAIN2 pin.
SHORT : Connection. (Default)
OPEN : Unconnection.
[JP8 (PC-SCL)]: The selection of SCL signal.
SHORT : When you write the setting in EEPROM.
OPEN : When you load the setting from EEPROM. (Default)
[JP9 (WP)]: The selection of Write Protect setting of EEPROM.
SHORT : Write protect is Disable.
OPEN : Write protect is Enable. (Default)
[JP10 (PC-SDA)]: The selection of SDA signal.
SHORT : When you write the setting in EEPROM.
OPEN : When you load the setting from EEPROM. (Default)
[JP11]: Not to use.
[JP12 (GND)]: Analog ground and Digital ground.
SHORT : Common. (Default)
OPEN : Separated.
[JP16 (TEST)]: The selection of connection to TEST pin.
SHORT : Connect to VDD.
OPEN : Connect to GND. (Default)
■Potentiometer setting
[R5]: Volume control
Upper - side: 0dB
Lower - side: Mute (-∞)
[R7]: Bass control
Upper - side: +12dB
Lower - side: -12dB
SAIN2SAIN1
R5 R7
Figure 11. Potentiometers
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[AKD4753-A]
■DIR SW Setting
Upper-side is “ON(H)” and lower-side is “OFF(L)”.
[S3] (SW DIP-4): Mode setting for AK4118A.
No. Name ON (“H”) OFF (“L”) Default
1 OCKS0 OFF
AK4118A Master Clock Setting
Table 3See
2 OCKS1 OFF
3 DIF0 ON
AK4118A Audio Interface Format Setting
Table 4See
4 DIF1 OFF
Table 2. Mode Setting for AK4118A
OCKS1 OCKS0 MCKO1
L L 256fs Default
H L 512fs
H H Not to use
Table 3. Setting for AK4118A Master Clock Setting
DIF2 DIF1 DIF0 SDTO LRCK BICK
L L 24bit, Left justified H/L O 64fs O
L H 24bit, I2S L/H O 64fs O
Fixed Default
H L 24bit, Left justified H/L I 64-128fs I
”H”
H H 24bit, I2S L/H I 64-128fs I
Table 4. Setting for AK4118A Audio Interface Format Setting
[S4] (SW DIP-2): Mode setting for AK4753.
No. Name ON (“H”) OFF (“L”) Default
1 EXTEE EEP-ROM Download Mode Serial Control Mode OFF
2 BYPASS DSP Bypass Mode Normal Operation OFF
Table 5. Mode Setting for AK4753
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[AKD4753-A]
■Function of the Toggle SW
Upper-side is “H” and lower-side is “L”.
[S1] (AK4118-PDN): Resets the AK4118A. Keep “H” during normal operation.
The AK4118A should be resets once bringing “L” upon power-up.
[S2] (AK4753-PDN): Resets the AK4753. Keep “H” during normal operation.
The AK4753 should be resets once bringing “L” upon power-up.
■Indication for LED
[LED1] (STO): Monitor STO pin of the AK4753.
LED turns on when Read error of EEPROM has occurred to AK4753.
[LED2] (EFR): Monitor INT0 pin of the AK4118A.
LED turns on when some error has occurred to AK4118A.
■Control Port
It is possible to control AKD4753-A via general USB port. Connect cable with the USB port on board and PC.
Control software is packed with this board. The software operation sequence is included in the evaluation board
manual.
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[AKD4753-A]
■Analog Input / Output Circuits
1) Analog Inputs
(a) AINL, AINR
+
C4
1u
+
C2
1u
J1
AINR
AINR
12
3
4
5
J3
AINL
12
3
4
5 R3
(open)
R1
(open)
AINL
Figure 12. Circuit diagram of AINL and AINR
(b) SAIN1, SAIN2
SAIN1
AVDD R5
10k
SAIN2
R7
10k
C9 (OPEN)
C12 (OPEN)
Figure 13. Circuit diagram of SAIN1 and SAIN2
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[AKD4753-A]
2) Analog Outputs
(a) STEREO Mode (Full-differential)
R6
(open)
C8
(OPEN)
TEST3
ROUT-
J2
Figure 14. Circuit diagram of STEREO Mode
(b) 2.1-channel Mode
Figure 15. Circuit diagram of 2.1-channel Mode
(c) 4-channel Mode (Single-ended)
Figure 16. Circuit diagram of 4-channel Mode
ROUT-LOUT+
C3
(OPEN)
TEST1
LOUT+
R2
(open)
C6
(OPEN)
LOUT-
TEST2
LOUT-
R4
(open)
+
C1
10u
+
C5
10u
+
C7
10u
+
C10
10u R8
(open)
C11
(OPEN)
TEST4
ROUT+
J6
LOUT2
ROUT+
R6
(open)
C8
(OPEN)
TEST3
ROUT-
SW-
LOUT1
C3
(OPEN)
TEST1
LOUT+
R2
(open)
C6
(OPEN)
ROUT1
TEST2
LOUT-
R4
(open)
+
C1
10u
+
C5
10u
+
C7
10u
+
C10
10u
R8
(open)
C11
(OPEN)
TEST4
ROUT+
SW+
R6
(open)
C8
(OPEN)
TEST3
ROUT-
ROUT2LOUT1
C3
(OPEN)
TEST1
LOUT+
R2
(open)
C6
(OPEN)
ROUT1
TEST2
LOUT-
R4
(open)
+
C1
10u
+
C5
10u
+
C7
10u
+
C10
10u R8
(open)
C11
(OPEN)
TEST4
ROUT+
LOUT2
ROUT2
J5
LOUT1
J4
ROUT1
J5
LOUT1
J2 ROUT2
J6
J4
ROUT1 LOUT2
J5
J2 ROUT2
LOUT1
J6
J4 LOUT2
ROUT1
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[AKD4753-A]
Control Soft Manual
■Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect Evaluation board to PC with USB cable.
USB control is recognized as HID (Human Interface Device) on the PC.
When it can not be recognized correctly please Connect Evaluation board to PC with USB cable.
3.Proceed evaluation by following the process below.
■Operation Screen
1. Start up the control program following the process above.
2. After the evaluation board’s power is supplied, the AK4753 must be reset once bring S2 (AK4753-PDN) “L” to
“H”.
3. The operation screen is shown below.
Figure 17. Window of Control Soft
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[AKD4753-A]
■Operation Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the
switching tab window. Refer to the “ ” for details of each dialog box setting.■Dialog Boxes
1. [Port Reset]: For when connecting to USB I/F board (AKDUSBIF-B)
Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-B).
2. [Write Default]: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executing write commands for all registers displayed.
4. [All Read]: Executing read commands for all registers displayed.
5. [Save]: Saving current register settings to a file.
6. [Load]: Executing data write from a saved file.
7. [All Reg Write]: “All Reg Write” dialog box is popped up.
8. [Data R/W]: “Data R/W” dialog box is popped up.
9. [Sequence]: “Sequence” dialog box is popped up.
10. [Sequence(File)]: “Sequence(File)” dialog box is popped up.
11. [EEPROM Write]: Executing EEPROM write.
12. [Read]: Reading current register settings and display on to the Register area on the right of the main window.
This is different from [All Read] button, it does not reflect to a register map, only displaying
hexadecimal.
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[AKD4753-A]
■Tab Functions
1. [Function]: Function control
This tab is for function control.
Each operation is executed by the function buttons on the left side of the screen.
Figure 18.Window of [Function]
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[AKD4753-A]
1-1. [Mode Setting]: Power Management and Signal Path Setting
When [Mode Setting] button is clicked, the window as shown in opens.
This window is for Power Management and Signal Path Setting.
Refer to the datasheet for register settings of the AK4753.
Figure 19. Window of [Mode Setting]
1-2. [PLL Setting]: System Clock and Audio I/F Setting
When [PLL Setting] button is clicked, the window as shown in opens.
This window is for System Clock and Audio I/F Setting.
Refer to the datasheet for register settings of the AK4753.
Figure 20. Window of [PLL Setting]
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[AKD4753-A]
1-3. [Volume Setting]: Volume Setting
When [Volume Setting] button is clicked, the window as shown in opens.
This window is for Volume Setting.
Refer to the datasheet for register settings of the AK4753.
Figure 21. Window of [Volume Setting]
1
-3-1. Register map
The volume can be controlled by slide bars.
A register writing is made on every slide bar move.
After the volume slide is moved, it is reflected on to the register map and data writing dialog box.
1-3-2. Volume Control by Slide bar
Slide bar is moved to the selected value
Figure 22. Volume Control by Slide bar
The volume can also be changed by writing a value in a dialog box. The slide bar is moved to the value that
written in the dialog box. Use the mouse or arrow keys on the keyboard for small adjustments.
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[AKD4753-A]
1-4. [Digital Filter Setting]: Filter Setting
A calculation of a coefficient of Digital Programmable Filters such as HPF / LPF and EQ filters,
a register writing and a frequency response checking of HPF / LPF and EQ filters can be made.
When [Digital Filter Setting] button is clicked, the window as shown in opens.
Refer to the datasheet for register settings of the AK4753.
Figure 23. Window of [Digital Filter Setting]
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[AKD4753-A]
1-4-1. Parameter Setting
(1) Please set a parameter of each Filter.
Parameter Function Setting Range
Sampling Rate Sampling frequency (fs) 7350Hz ≤fs ≤48000Hz
HPF
Cut Off Frequency 1.042x10-3 ≤fc/fs ≤0.24
High pass filter cut off frequency
LPF
Cut Off Frequency Low pass filter cut off frequency 5.208x10-3 ≤fc/fs ≤0.24
5 Band Equalizer
EQ1-5 Center Frequency EQ1-5 Center Frequency 3.125x10-3 ≤fon/fs < 0.4969
EQ1-5 Band Width Note 1 fbn/fs ≤0.25
EQ1-5 Band Width )
(
EQ1-5 Gain Note 2 -1≤Gain < 3
EQ1-5 Gain )
(
Table 6. Parameter Setting
Note 1. A gain difference is a bandwidth of 3dB from center frequency.
Note 2. When a gain is smaller than 0 , EQ becomes a notch filter.
(2) “HPF LPF Enable” , “HPF” ,”LPF” , “EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5”
Please set ON/OFF of Filter with a check button. When checked it, Filter becomes ON.
When “Notch Filter Auto Correction” is checked, perform automatic correction of the center frequency
of the notch filter is executed.
Figure 24. Filter ON/OFF setting button
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[AKD4753-A]
1-4-2. A calculation of a register
A register set value is displayed when push a [Register Setting] button. When a value out of a setting range is
set, error message is displayed, and a calculation of register setting is not carried out.
Figure 25. A register setting calculation result
Followings are the cases when a register set value is updated.
(1) When [Register Setting] button was pushed.
(2) When [F Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “HPF LPF Enable”, “HPF” ,”LPF”,“EQ1”, “EQ2”, “EQ3”,
“EQ4”, “EQ5”
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[AKD4753-A]
1-4-3. Indication of a frequency characteristic
A frequency characteristic is displayed when push a [F Response] button. Then, a register set point is also
updated.
Change "Frequency Range", and indication of a frequency characteristic is updated when push a [UpDate]
button.
Figure 26. A frequency characteristic indication result
Followings are the cases when a register set value is updated.
(1) When [Register Setting] button was pushed.
(2) When [F Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “HPF LPF Enable”, “HPF” ,”LPF”,“EQ1”, “EQ2”, “EQ3”,
“EQ4”, “EQ5”
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