AKM AK4584 User manual

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
- 1 -
GENERAL DESCRIPTION
AKD4584 is an evaluation board for the 24bit 96kHz CODEC, AK4584. The AKD4584 can evaluate A/D
converter D/A converter separately in addition to loop back mode (A/D →D/A). The AKD4584 also has
the digital audio interface and can achieve the interface with digital audio systems via opt-connector.
Ordering guide
AKD4584 --- Evaluation board for AK4584
(Cable for connecting with printer port of IBM-AT,
compatible PC and control software are packed with this.)
FUNCTION
•DIT/DIR with optical input/output
•BNC connector for an external clock input
•10pin Header for serial control mode
10pin Header
Control Data
10pin Header
ROM
2.7 ~ 5.25V 4.75 ~ 5.25V GND
ROUT
Opt In
BNC In
LOUT
LIN
RIN
BNC out
Opt out AK4114 Opt In
Opt Out
Clock
Gen
AK4584
Figure 1. AKD4584 Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
AK4584 Evaluation Board Rev.A
AKD4584

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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Evaluation Board Manual
Analog Input / Output circuits
(1) Input circuits
The analog input of AK4584 inputs from J1 (RIN), J3 (LIN).
J3
LIN
J1
RIN
R19
560
+
C34
10u
+
C32
10u RIN
LIN
R16
560
Figure 2. LIN/RIN Input circuits
(2) Output circuits
The analog output of AK4584’s DAC outputs from J2 (ROUT), J4 (LOUT).
ROUT
+
C35
22u
R17
10k
+
C33
22u
J2
ROUT
R18
220
R20
10k
J4
LOUT
LOUT
R15
220
Figure 3. LOUT/ROUT Output circuits
* AKM assumes no responsibility for the trouble when using the above circuit examples.

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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Digital Input / Output circuits & Set-up jumper pin
(1) Digital input circuits
The digital input of AK4584 inputs from J7 (RX) or PORT5 (DIR).
C39
0.1u
BNC
RX
R39
470 RX2
RX3
L4
47u
1 2
JP13
RX
RX4
VDD
+C38
10u
JP12
RX1-4
J7
RX
RX4
PORT5
DIR
1
3
4
2
6
5OUT
VCC
GND
GND
6
5
RX3
C37
0.1u
RX2
RX1
RX1
R40
75
Figure 4. Digital input circuit
1. Digital signal is input to RX1-4 pins respectively.
JP12
RX1-4
RX2
RX1
JP12
RX1-4
RX2
RX1
RX4
RX3
RX4
RX3
JP12
RX1-4
RX2
RX1
RX4
RX3
JP12
RX1-4
RX2
RX1
RX4
RX3
2. Digital signal is input to RX1-4 pins via J7 (RX) and PORT5 (DIR).
JP13
RX
BNCRX
JP13
RX
BNCRX
* AKM assumes no responsibility for the trouble when using the above circuit examples.

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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(2) Digital output circuits
The digital output of AK4584 inputs from J6 (TX) or PORT4 (DIT).
TX3
JP9
TX1-3
J6
TX
JP8
TX
VDD
TX2
TX1
BNC
T2
DA-02F
R38
100
TX3
TX1
TX
R32
1k TX2
C36
0.1u
R37
330
PORT4
DIT
1
2
3
45
6GND
IF
VCC
IN5
6
Figure 5. Digital output circuit
1. Digital signal is output to TX1-3 pins respectively.
JP9
TX1-3
TX2
TX1
JP9
TX1-3
TX2
TX1
TX3 TX3
JP9
TX1-3
TX2
TX1
TX3
2. Digital signal is output to TX1-3 pins via J6 (TX) and PORT4 (DIT).
JP8
TX
BNCTX
JP8
TX
BNCTX
* AKM assumes no responsibility for the trouble when using the above circuit examples.

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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Operation sequence
1) Set up the power supply lines.
[AVDD] (Red) = 4.75 ∼5.25V : for AVDD, DVDD, PVDD of AK4584 (typ. 5.0V)
[TVDD] (Orange) = 2.7 ∼5.25V : for TVDD of AK4584 (typ. 3.0V)
[VCC] (Red) = 5.0V : for logic (typ. 5.0V)
[VDD] (Red) = 5.0V : for logic (typ. 5.0V)
[AGND] (Black) = 0V : for analog ground
[DGND] (Black) = 0V : for logic ground
Each supply line should be distributed from the power supply unit.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4584 should be reset once bringing SW1 “L” upon power-up.
Evaluation mode
(1) Slave mode
In case of AK4584 evaluation using AK4114, it is necessary to correspond to AK4584’s and AK4114’s audio
interface format. About AK4584’s audio interface format, refer to AK4584’s datasheet. About AK4114’s audio
interface format, see Table2.
(1-1)A/D evaluation using DIT function of AK4584
(1-2)A/D evaluation using DIT function of AK4114
(1-3)D/A evaluation using DIR function of AK4114
(1-4)All interfacing signal (MCLK, BICK, LRCK) are fed from the external circuit
(1-1) A/D evaluation using DIT function of AK4584
Using J5 (EXT), PORT4 (DIT) and J6 (TX). Nothing should be connected to J7 (RX), PORT1 (DIR), PORT5
(DIR) and PORT6 (ROM). Remove the X’tal (X1). The bi-phase data is output from TX3. JP6 (EXT) should be
open.
JP10
MCLK
JP3
XTI JP14
LRCK
JP6
EXT JP11
BICK
EX
T
DIR
DIR EXT ADC
JP15
SDTI
ADCDIREX
T
DIR

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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•Clock setting
(1-1-1) Normal Speed (MCLK=256fs=11.2896MHz@fs=44.1kHz)
JP5
BCFS JP7 LRFS
JP4
MCLK
x1x4
x4 x2 x1
JP1
MCKO
M2M1 x2x1
(1-1-2) Normal Speed (MCLK=512fs=22.5792MHz@fs=44.1kHz)
JP5
BCFS JP7 LRFS
JP4
MCLK
x1x4
x4 x2 x1
JP1
MCKO
M2M1 x2x1
(1-1-3) Double Speed (MCLK=256fs=22.5792MHz@fs=88.2kHz)
JP5
BCFS JP7 LRFS
JP4
MCLK
x1x4
x4 x2 x1
JP1
MCKO
M2M1 x2x1
•SW2 (MODE) setting (See Table 1)
Normal speed and double speed are same setting.
(1)When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down.
(2)When DMCK is “H”, MCKO1 output is disabled.
H
L
12345 867 910
DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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(1-2) A/D evaluation using DIT function of AK4114
Using X’tal (X2) and PORT2 (DIT). Nothing should be connected to J5 (EXT), J7 (RX), PORT1 (DIR), PORT5
(DIR) and PORT6 (ROM). Remove the X’tal (X1). JP6 (EXT) should be short. In normal speed and double
speed mode, JP1 (MCKO), JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open.
JP10
MCLK
JP3
XTI JP14
LRCK
JP6
EXT JP11
BICK
EX
T
DIR
DIR EXT ADC
JP15
SDTI
ADCDIREX
T
DIR
•SW2 (MODE) setting (See Table 1)
Normal speed and double speed are same setting.
(1) Set the audio interface format of AK4114 using DIF2-0.
(2) Set the master clock output of AK4114using OCKS1-0.
(3) Set the PLL mode or X’tal mode of AK4114 using CM0.
(4) When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down.
(5) When DMCK is “H”, MCKO1 output is disabled.
H
L
12345 867 910
DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS
Above figure is 24bit MSB justified, MCKO output of AK4114 is 256fs, AK4114 is X’tal mode.
Using DIT of AK4114, AK4114 is set X’tal mode.

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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(1-3) D/A evaluation using DIR function of AK4114
Using PORT1 (DIR). Nothing should be connected to J7 (RX), PORT5 (DIR) and PORT6 (ROM). Remove the
X’tal (X1). JP6 (EXT) should be short. In normal speed, double speed mode and quad speed mode, JP1 (MCKO),
JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open.
JP10
MCLK
JP3
XTI JP14
LRCK
JP6
EXT JP11
BICK
EX
T
DIR
DIR EXT ADC
JP15
SDTI
ADCDIREX
T
DIR
•SW2 (MODE) setting (See Table 1)
(1)Set the audio interface format of AK4114 using DIF2-0.
(2)Set the master clock output of AK4114using OCKS1-0.
(3)Set the PLL mode or X’tal mode of AK4114 using CM0.
(4)When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down.
(5)When DMCK is “H”, MCKO1 output is disabled.
H
L
12345 867 910
DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS
Above figure is 24bit MSB justified, MCKO output of AK4114 is 256fs, AK4114 is PLL mode.
In quad speed mode of AK4114, set OCKS1=“H” and OCKS0=“H”. The MCKO output of AK4114 is output
128fs.

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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(1-4) All interfacing signal (MCLK, BICK, LRCK) are fed from the external circuit
Using PORT6 (ROM). Nothing should be connected to J7 (RX), PORT1 (DIR) and PORT5 (DIR). Remove the
X’tal (X1). JP6 (EXT) should be short. In normal speed, double speed mode and quad speed mode, JP1 (MCKO),
JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open.
JP10
MCLK
JP3
XTI JP14
LRCK
JP6
EXT JP11
BICK
EX
T
DIR
DIR EXT ADC
JP15
SDTI
ADCDIREX
T
DIR
•SW2 (MODE) setting (See Table 1)
(1)When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down.
(2)When DMCK is “H”, MCKO1 output is disabled.
H
L
12345 867 910
DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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(2) Master Mode
(2-1) A/D evaluation using DIT function of AK4584（Default）
Using X’tal (X1), PORT4 (DIT) and J6 (TX). Nothing should be connected to J7 (RX), PORT1 (DIR), PORT5
(DIR) and PORT6 (ROM). The bi-phase data is output from TX3. JP6 (EXT) should be short. In normal speed,
double speed mode and quad speed mode, JP3 (XTI), JP4 (MCLK), JP5 (BCFS) and JP7 (LRFS) should be open.
JP10
MCLK
JP3
XTI JP14
LRCK
JP6
EXT JP11
BICK
EX
T
DIR
DIR EXT ADC
JP15
SDTI
ADCDIREX
T
DIR
•Clock Setting
(2-1-1) Select MCKO1
JP5
BCFS JP7 LRFS
JP4
MCLK
x1x4
x4 x2 x1
JP1
MCKO
M2M1 x2x1
(2-1-2) Select MCKO2
JP5
BCFS JP7 LRFS
JP4
MCLK
x1x4
x4 x2 x1
JP1
MCKO
M2M1 x2x1
•SW2 (MODE) setting (See Table 1)
Normal speed and double speed are same setting.
(1)When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down.
(2)When DMCK is “H”, MCKO1 output is disabled.
H
L
12345 867 910
DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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(2-2) D/A evaluation using DIR function of AK4584（Default）
Using PORT5 (DIR) or J7 (RX). Nothing should be connected to PORT1 (DIR) and PORT6 (ROM). JP6 (EXT)
should be short. In normal speed and double speed mode, JP1 (MCKO), JP4 (MCLK), JP5 (BCFS) and JP7
(LRFS) should be open.
JP10
MCLK
JP3
XTI JP14
LRCK
JP6
EXT JP11
BICK
EX
T
DIR
DIR EXT ADC
JP15
SDTI
ADCDIREX
T
DIR
•Clock setting
(2-2-1) Select MCKO1
JP5
BCFS JP7 LRFS
JP4
MCLK
x1x4
x4 x2 x1
JP1
MCKO
M2M1 x2x1
(2-2-2) Select MCKO2
JP5
BCFS JP7 LRFS
JP4
MCLK
x1x4
x4 x2 x1
JP1
MCKO
M2M1 x2x1
•SW2 (MODE) setting (See Table 1)
Normal speed, double speed and quad speed mode are same setting.
(1)When XTALE is “H”, MCLK can output from MCKO1/2 pins though AK4584 is powered down.
(2)When DMCK is “H”, MCKO1 output is disabled.
H
L
12345 867 910
DIF0 DIF1 DIF2 OCKS0 OCKS1 CM0 TEST3 XTALE DMCK MS

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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DIP Switch set up
[SW2] (MODE): Setting evaluation mode for AK4584 and AK4114
ONis“H”,OFFis“L”.
No. Name ON (“H”) OFF (“L”)
1 DIF0
2 DIF1
3 DIF2
AK4114 Audio Format Setting
See Table 2
4 OCKS0
5 OCKS1 AK4114 Master Clock Output Setting
See Table 3
6 CM0 AK4114 X’tal Mode AK4114 PLL Mode
7 TEST3 Normally OFF
8 XTALE MCKO1/2 Enable MCKO1/2 Disable
9 DMCK MCKO1 Disable MCKO1 Enable
10 M/S Master Mode Slave Mode
Table 1. Setting mode for AK4584 and AK4114
Mode DIF2 DIF1 DIF0 AK4114 DAUX AK4114 SDTO
0 0 0 0 24bit, MSB justified 16bit, LSB justified
1 0 0 1 24bit, MSB justified 18bit, LSB justified
2 0 1 0 24bit, MSB justified 20bit, LSB justified
3 0 1 1 24bit, MSB justified 24bit, LSB justified
4 1 0 0 24bit, MSB justified 24bit, MSB justified
5 1 0 1 24bit, I2S 24bit, I2S
Table 2. Setting AK4114 audio interface format
Mode OCKS1 OCKS0 MCKO1 X’tal fs
0 0 0 256fs 256fs
∼96kHz
1 0 1 256fs 256fs
∼96kHz
2 1 0 512fs 512fs
∼48kHz
3 1 1 128fs 128fs
∼192kHz
Table 3. Setting AK4114 master clock output
Other jumper pins set up
1. JP1 (GND): Analog ground and Digital ground
OPEN: Separated. <Default>
SHORT: Common. (The connector “DGND” can be open.)
The function of the toggle SW
Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Power down of AK4584. Keep “H” during normal operation.
[SW3] (DIR): Power down of AK4114. Keep “H” during normal operation.

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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Indication for LED
[LED1] (INT0): Output INT0 pin of AK4584.
[LED2] (INT1): Output INT1 pin of AK4584.
[LED3] (ERF): Output INT0 pin of AK4114.
[LED4] (DZF): Output DZF pin of AK4584.
Serial Control
The AK4584 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3
(CTRL) with PC by 10 wire flat cable packed with the AKD4584.
Connect CSN
CCLK
CDTI
10pin Header
10pin
Connector
10 wire
flat cable
PC AKD4584
CDTO
Figure 6. Connect of 10 wire flat cable

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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Control Software Manual
Set-up of evaluation board and control software
1.Set up the AKD4584 according to previous term.
2.Connect IBM-AT compatible PC with AKD4584 by 10-line type flat cable (packed with AKD4584). Take care of
the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3.Insert the CD-ROM labeled “AKD4584 Evaluation Kit” into the CD-ROM drive.
4.Access the CD-ROM drive and double-click the icon of “akd4584.exe” to set up the control program.
5.Then please evaluate according to the follows.
Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
Explanation of each buttons
1. [Port Reset]: Set up the USB interface board (AKDUSBIF-A).
2. [Write default]: Initialize the register of AK4584.
3. [All Write]: Write all registers that is currently displayed.
4. [Function1]: Dialog to write data by keyboard operation.
5. [Function2]: Dialog to write data by keyboard operation.
6. [Function3]: The sequence of register setting can be set and executed.
7. [Function4]: The sequence that is created on [Function3] can be assigned to buttons and executed.
8. [Function5]: The register setting that is created by [SAVE] function on main window can be assigned
to buttons and executed.
9. [SAVE]: Save the current register setting.
10. [OPEN]: Write the saved values to all register.
11. [Write]: Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”.
Blank is the part that is not defined in the datasheet.

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog.
If you check the check box, data becomes “H” or “1”. If not, “L” or “0”.
When writing the input data to AK4584, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog]: Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal.
Data Box: Input registers data in 2 figures of hexadecimal.
When writing the input data to AK4584, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog]: Dialog to evaluate GAIN/ATT
This dialog corresponds to address 04H, 05H, 06H, and 07H.
Address Box: Input registers address in 2 figures of hexadecimal.
Start Data Box: Input starts data in 2 figures of hexadecimal.
End Data Box: Input end data in 2 figures of hexadecimal.
Interval Box: Data is written to AK4584 by this interval.
Step Box: Data changes by this step.
Mode Select Box:
With checking this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
Without checking this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
When writing the input data to AK4584, click [OK] button. If not, click [Cancel] button.

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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4. [Save] and [Open]
4-1. [Save]
Save the current register setting data. The extension of file name is “akr”.
(Operation flow)
(1) Click [Save] Button.
(2) Set the file name and push [Save] Button. The extension of file name is “akr”.
4-2. [Open]
The register setting data saved by [Save] is written to AK4584. The file type is the same as [Save].
(Operation flow)
(1) Click [Open] Button.
(2) Select the file (*.akr) and Click [Open] Button.

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [Start] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file
name is “aks”.
Figure 1. Window of [F3]

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the
window as shown in Figure 2 opens.
Figure 2. [F4] window

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks).
The sequence file name is displayed as shown in Figure 3.
Figure 3. [F4] window(2)
(2) Click [START] button, then the sequence is executed.
3-2. [SAVE] and [OPEN] buttons on right side
[SAVE]: The sequence file names can assign be saved. The file name is *.ak4.
[OPEN]: The sequence file names assign that are saved in *.ak4 are loaded.
3-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.

ASAHI KASEI [AKD4584]
<KM065802> 2009/06
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7. [Function5 Dialog]
The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When
[F5] button is clicked, the following window as shown in Figure 4opens.
Figure 4. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
(2) Click [WRITE] button, then the register setting is executed.
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE]: The register setting file names assign can be saved. The file name is *.ak5.
[OPEN]: The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to
reflect the change.