AKM AKD4953-A User manual

[AKD4953-A]
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GENERAL DESCRIPTION
The AKD4953-A is an evaluation board for the AK4953 24bit CODEC with built-in PLL and MIC/HP/SPK
Amplifier. The AKD4953-A has the interface with AKM’s A/D evaluation boards. Therefore, it’s easy to
evaluate the AK4953. The AKD4953-A also has the digital audio interface and can achieve the interface with
digital audio systems via opt-connector.
Ordering Guide
AKD4953-A --- Evaluation board for AK4953
(Cable for connecting with printer port of IBM-AT compatible PC and control software
are packed with this. This control software does not operate on Windows NT.)
FUNCTION
•Compatible with 2 types of interface
- Direct interface with AKM’s A/D converter evaluation boards
- DIT/DIR with optical input/output
•BNC connector for an external clock input
•10pin header for serial control interface
AK4953
PORT3
(DSP)
LIN
RIN
Mini
Jack
Opt In
Opt Out
PORT4
(CTRL)
AK4118A
(DIT/DIR)
External
Clock
LIN1
RIN1
LIN2
RIN2
Digital
MIC
REG
REG
TVDD DVDD AVDD SVDD AGND
3.3V
1.8V3.3V 3.3V 3.3V 0V
LIN3
RIN3
SPK HP
HPL HPR
SPN
S
PP
5V
Figure 1. AKD4953-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
Evaluation board Rev.2 for AK4953
A
KD4953-
A

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Operation Sequence
(1) Set up the power supply lines.
(1-1) In case of using the regulator. <Default>
JP3
SVDD-SEL JP4
AVDD-SEL JP6 TVDD-SEL JP7 VCC-SEL
Name of
Jack
Color Default Setting Using
REG red 5V for regulator (3.3V output : AVDD ,SVDD)
AVDD orange Open for AVDD of AK4953
SVDD orange Open for SVDD of AK4953
DVDD orange 1.6~2.0V (typ1.8V) for DVDD of AK4953
TVDD orange 1.6~3.5V (typ3.3V) for TVDD of AK4953
VCC orange Open for logic
D3V orange 2.7~3.6V (typ3.3V) for AK4118A and logic
AGND black 0V for analog ground
DGND black 0V for logic ground
Table 1. Set up of power supply lines
(1-2) In case of using the power supply connectors.
JP3
SVDD-SEL JP4
AVDD-SEL JP6 TVDD-SEL JP7 VCC-SEL
Name of
Jack
Color Default Setting Using
REG red Open No using
AVDD orange 3.0~3.5V (typ3.3V) for AVDD of AK4953
SVDD orange 0.9~5.5V (typ3.3V) for SVDD of AK4953
DVDD orange 1.6~2.0V (typ1.8V) for DVDD of AK4953
TVDD orange 1.6~3.5V (typ3.3V) for TVDD of AK4953
VCC orange 1.6~3.5V (typ3.3V) for logic(This voltage must be same as TVDD)
D3V orange 2.7~3.6V (typ3.3V) for AK4118A and logic
AGND black 0V for analog ground
DGND black 0V for logic ground
Table 2. Set up of power supply lines
* Each supply line should be distributed from the power supply unit.
(2) Set up the evaluation mode, jumper pins and DIP switch. (See the followings.)
(3) Power on.
The AK4953 and AK4114 should be reset once bringing SW1 (PDN) and SW2 (DIR) “L” upon power-up.
Click the reset button on the control software after releasing the reset by SW1= “H”.

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Evaluation mode
In case of using the AK4118A when evaluating the AK4953, both the AK4953 and AK4118A’s audio interface
formats must be matched.
Reter to the datasheet for AK4953’s audio interface format, and Table 3 for AK4118’s audio interface format.
The AK4118A operates at fs of 32kHz or more. If the fs is slower than 32kHz, please use other mode.
In addition, MCLK of AK4118A supports 256fs and 512fs. When evaluating in a condition except above, please
use other mode.
Refer to the datasheet for register setting of the AK4953.
Applicable Evaluation Mode
(1) Evaluation of A/D using DIT of AK4118A.
(1-1) Setting with External Slave Mode
(2) Evaluation of D/A using DIR of AK4118A. <Default>
(2-1) Setting with External Slave Mode
(3) Evaluation of A/D, D/A using PORT3 (DSP).
(3-1) Setting with PLL Master Mode
(3-2) Setting with PLL Slave Mode
(3-3) Setting with External Slave Mode
(4) Evaluation of Loop-back.
(4-1) Setting with PLL Master Mode
(4-2) Setting with PLL Slave Mode
(4-3) Setting with External Slave Mode

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(1) Evaluation of A/D using DIT of AK4118A.
(1-1) Setting with External Slave Mode
X1 (X’tal) and PORT2 (DIT) are used. Nothing should be connected to PORT1 (DIR) and PORT3 (DSP).
JP23 (M/S) should be set to “Slave”. In addition, Registers of the AK4953 should be set to “EXT Slave Mode”.
MCKI, BICK and LRCK are supplied from the AK4118A, and SDTO of the AK4953 is output to the AK4118A.
The jumper pins should be set as follows.
JP15
MCLK JP18 BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP22
4114_MCKI
(2) Evaluation of D/A using DIR of AK4118A. <Default>
(2-1) Setting with External Slave Mode
PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT) and PORT3 (DSP).
JP23 (M/S) should be set to “Slave”. In addition, Registers of the AK4953 should be set to “EXT Slave Mode”.
The jumper pins should be set as follows.
JP15
MCLK JP18 BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP22
4114_MCKI
JP24
SDTI_SEL
ADCDIR

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(3) Evaluation of A/D, D/A using PORT3 (DSP).
PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR) and PORT2 (DIT).
(3-1) Setting with PLL Master Mode
The master clock is input from MCKI of PORT3 (DSP). An internal PLL circuit generates MCKO, BICK, and
LRCK.
JP23 (M/S) should be set to “Master”. In addition, Registers of the AK4953 should be set to “PLL Master Mode”.
SDTI, SDTO, LRCK and BICK of PORT3 are respectively connected with SDTO, SDTI, LRCK and BICK of DSP.
When MCKO is supplied to DSP, test pin (MCKO) should be directly connected to DSP.
AK4953 DSP or
μ
P
MCKO
BICK
LRCK
SDTO
SDTI
BCLK
LRCK
SDTI
SDTO
MCKI
1fs
32fs, 64fs
256fs/128fs/64fs/32fs
11.2896MHz, 12MHz, 13.5MHz
24MHz, 25MHz, 27MHz
MCLK
Figure 2. PLL Master Mode
Supplied Master Clock (MCKI) from MCLK (PORT3).
The jumper pins should be set as follows.
JP15
MCLK JP18
BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP24
SDTI_SEL
ADCDIR
JP14
EXT
Supplied Master Clock (MCKI) from J11.
The jumper pins should be set as follows.
JP15
MCLK JP18 BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP24
SDTI_SEL
ADCDIR
JP14
EXT
*When a termination (51) is not used, JP14 (EXT) should be open.

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(3-2) Setting with PLL Slave Mode
A reference clock of PLL is selected among the input clocks supplied from PORT3 (DSP) to MCKI, BICK or
LRCK pin. The required clock to the AK4953 is generated by an internal PLL circuit.
JP23 (M/S) should be set to “Slave”.
(3-2-1) PLL Reference Clock: MCKI pin
Registers of the AK4953 should be set to “PLL Slave Mode” (Reference Clock: MCKI).
BICK and LRCK inputs should be synchronized with MCKO output. However the phase between MCKO and
LRCK dose not matter.
AK4953 DSP or
μ
P
MCKO
BICK
LRCK
SDTO
SDTI
BCLK
LRCK
SDTI
SDTO
MCKI
1fs
≥32fs
11.2896MHz, 12MHz,13.5MHz
24MHz, 25MHz, 27MHz
MCLK
256fs/128fs/64fs/32fs
Figure 3. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
Supplied Master Clock (MCKI) from MCLK (PORT3).
The jumper pins should be set as follows.
JP15
MCLK JP18
BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP24
SDTI_SEL
ADCDIR
JP14
EXT
Supplied Master Clock (MCKI) from J11.
The jumper pins should be set as follows.
JP15
MCLK JP18 BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP24
SDTI_SEL
ADCDIR
JP14
EXT
*When a termination (51) is not used, JP14 (EXT) should be open.

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(3-2-2) PLL Reference Clock: BICK pin
Registers of the AK4953 should be set to “PLL Slave Mode” (Reference Clock = BICK).
AK4953
DSP or
μ
P
MCKI
BICK
LRCK
SDTO
SDTI
BCLK
LRCK
SDTI
SDTO
MCKO
1fs
32fs, 64fs
Figure 4. PLL Slave Mode 2(PLL Reference Clock: BICK pin)
 Evaluation using DIR (Optical Link) of AK4118A
PORT1 (DIR) is used.
The jumper pins should be set as follows.
JP15
MCLK JP18 BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP24
SDTI_SEL
ADCDIR
JP14
EXT
*The AK4118A supports fs up to 32kHz, and BICK outputs 64fs clock. In case of other clocks, use other
evaluation modes.
 Evaluation connecting with external DSP
PORT3 (DSP) is used. Nothing should be connected to PORT1 (DIR).
SDTI, BICK, LRCK of PORT3 should be connected to SDTO, BICK, LRCK for DSP.
The jumper pins should be set as follows.
JP15
MCLK JP18 BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP24
SDTI_SEL
ADCDIR
JP14
EXT
*When a termination (51) is not used, JP14 (EXT) should be open.

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(3-3) Setting with External Slave Mode
MCLK, BICK, LRCK, and SDTI are input from PORT3 (DSP).
JP23 (M/S) should be set to “Slave”. In addition, Registers of the AK4953 should be set to “EXT Slave Mode”.
AK4953
DSP or
μ
P
MCKI
BICK
LRCK
SDTO
SDTI
BCLK
LRCK
SDTI
SDTO
MCKO
1fs
≥32fs
MCLK
256fs,384fs
512fs or 1024fs
Figure 5. EXT Slave Mode
The jumper pins should be set as follows.
JP15
MCLK JP18
BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP24
SDTI_SEL
ADCDIR
(4) Evaluation of Loop-back.
(4-1) Setting with PLL Master Mode
Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP).
JP23 (M/S) should be set to “Master”. In addition, Registers of the AK4953 should be set to “PLL Master Mode”.
(4-1-1) In case of supplying MCLK from J11 (EXT)
The jumper pins should be set as follows.
JP15
MCLK JP18 BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP24
SDTI_SEL
ADCDIR
JP14
EXT
* When a termination (51) is not used, JP14 (EXT) should be open.

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(4-2) Setting with PLL Slave Mode
BICK and LRCK are generated on the AKD4953-A by dividing MCKO from the AK4953. The generated BICK
and LRCK is input to the AK4953.
JP23 (M/S) should be set to “Slave”. In addition, Registers of the AK4953 should be set to “PLL Master Mode”
(Reference Clock: MCKI).
Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP).
(4-2-1) In case of supplying MCLK from J11 (EXT)
The jumper pins should be set as follows.
JP15
MCLK
JP14
EXT JP19 PHASE
INVTHR
JP21
LRCK_SEL
4040DIR
JP24
SDTI_SEL
ADCDIR
DIR
EXT
JP18
BICK_SEL
4040DIR
JP16
MKFS
512fs
1024fs
256fs
MCKO
JP17
BGFS
64fs
32fs
JP109
MCKO
384/768fs
32fs-384
64fs-384
*When a termination (51) is not used, JP14 (EXT) should be open.
(4-3) Setting with External Slave Mode
JP23 (M/S) should be set to “Slave”. In addition, Registers of the AK4953 should be set to “EXT Slave Mode”.
Nothing should be connected to PORT1 (DIR), PORT2 (DIT) and PORT3 (DSP).
(4-3-1) In case of using clocks from AK4118A
X1 (12.288MHz) is used.
The jumper pins should be set as follows.
JP15
MCLK JP18 BICK_SEL JP19 PHASE
4040DIR INVTHR
JP21
LRCK_SEL
4040DIR
DIR
EXT
JP22
4118
A
_
MCKI JP24
SDTI_SEL
ADCDIR

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(4-3-2) In case of using the clock divider on the board
In case of supplying MCLK from J11 (EXT)
( MCLK=256fs, BICK=64fs)
The jumper pins should be set as follows.
JP15
MCLK
JP14
EXT JP19 PHASE
INVTHR
JP21
LRCK_SEL
4040DIR
JP24
SDTI_SEL
ADCDIR
DIR
EXT
JP18
BICK_SEL
4040DIR
JP16
MKFS
512fs
1024fs
256fs
MCKO
JP17
BGFS
64fs
32fs
384/768fs
32fs-384
64fs-384
* When a termination (51) is not used, JP14 (EXT) should be open.

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DIP Switch Set Up
[S1] (SW DIP-6): Mode setting of the AK4953 and AK4118A.
No. Name ON (“H”) OFF (“L”) Default
1 DIF2 H
2 DIF1 L
3 DIF0
AK4118A Audio Format Setting
See Table 4 L
4 OCKS1 AK4118A Master Clock Setting : See Table 5 L
5 CAD0 AK4953Control Mode Setting : See Table 6 L
6 I2C I2C Bus 3-Wire Serial H
Table 3. Mode Setting of the AK4953 and AK4118A
LRCK BICK
Mode DIF2 DIF1 DIF0 DAUX SDTO I/O I/O
0 0 0 0 24bit, Left justified 16bit, Right justified H/L O 64fs O
1 0 0 1 24bit, Left justified 18bit, Right justified H/L O 64fs O
2 0 1 0 24bit, Left justified 20bit, Right justified H/L O 64fs O
3 0 1 1 24bit, Left justified 24bit, Right justified H/L O 64fs O
4 1 0 0 24bit, Left justified 24bit, Left justified H/L O 64fs O Default
5 1 0 1 24bit, I2S 24bit, I2S L/H O 64fs O
6 1 1 0 24bit, Left justified 24bit, Left justified H/L I 64 -128fs I
7 1 1 1 24bit, I2S 24bit, I2S L/H I 64 -128fs I
Table 4. AK4118A Audio Interface Format Setting
OCKS1 MCKO1 X’tal
0 256fs 256fs
1 512fs 512fs
Default
Table 5. AK4118A Master Clock Setting

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Jumper Pins Set Up
Main Board
[JP1] (GND): Analog ground and Digital ground
OPEN: Separated.
SHORT: Common. (The connector “DGND” can be open.) <Default>
[JP16] (MKFS): MCLK Frequency
256fs: 256fs <Default>
512fs: 512fs
1024fs: 1024fs
384fs: 384fs
MCKO: MCKO of the AK4953
[JP17] (BCFS): BICK Frequency
64fs-384: 64fs (When MCLK is 384fs.)
32fs-384: 32fs (When MCLK is 384fs.)
64fs: 64fs (When MCLK is 256fs or 512fs or 1024fs.) <Default>
32fs: 32fs (When MCLK is 256fs or 512fs or 1024fs.)
[JP20] (LRCK): LRCK Frequency
fs: When MCLK is 256fs or 512fs or 1024fs. <Default>
fs-384: When MCLK is 384fs.
[JP22] (4114-MCKI): AK4118A Clock Source
OPEN: X’tal of AK4118A is used. <Default>
SHORT: MCKO of the AK4953 is supplied to the AK4118A.
Sub Board
[JP101] (CSN/CAD0): Control Mode Setting
CSN: I2Cpin= “L”
CAD0: I2Cpin= “H” <Default>
[JP108] (CDTIO/SDA): Control Mode Setting
CDTIO: I2Cpin= “L”
SDA: I2Cpin= “H” <Default>
[JP109] (MCKO): MCKO Output Circuit
OPEN: <Default>
SHORT: When dismantle MCKO
The function of the toggle SW
*Upper-side is “H” and lower-side is “L”.
[SW1] (PDN): Power down of AK4953. Keep “H” during normal operation.
[SW2] (DIR): Power down of AK4118A. Keep “H” during normal operation.
Keep “L” when AK4118A is not used.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4118A. LED turns on when an error has occurred to AK4118A.

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Serial Control
The AKD4953 can be connected to the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4
(CTRL) with PC by 10 wire flat cable packed with the AKD4953. Table 6 shows switch and jumper settings for
serial control. 3-WIRE Mode should be selected in Table 6.
Connect CSN
CCLK/SCL
CDTI/SDA
10pin
Header
10pin
Connector
10 wire
flat cable
PC AKD4953
CDTO/SDA(ACK)
PORT4
Figure 6. Connect of 10 wire flat cable
S1 JP25
Mode CAD0 I2C CTRL-SEL
3-WIRE L L 3-WIRE
CAD=0 L H Default
I2C CAD=1 H H I2C
Table 6. AK4953 Control Mode Setting

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Analog Input/Output Circuits
(1) Input Circuits
LIN3
LIN2
RIN3
RIN2
J3
RIN
12
3
4
5
+
C30
(short)
JP8
LIN_SEL
JP9
RIN_SEL
R10
(short)
+
C31
(short) R11 (short)
J2
LIN
12
3
4
5
LIN2
LIN3
RIN2
RIN3
RIN1
LIN1
J1
LIN1/RIN1
6
4
3
Figure 7. LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 Input Circuits
(1-1)LIN1/RIN1Input Circuit <Default>
LIN1/RIN1 is input from J1.
When the Mic Power is not used, JP104 and JP105 should be set to open.
JP102 JP103
RIN1 DMDAT LIN1DMCLK
JP104 JP105
MPW
R
-RIN1 MPW
R
-LIN1
(1-2) LIN2/RIN2 Input Circuit <Default>
LIN2/RIN2 is input from J2/J3.
When the Mic Power is not used, JP106 and JP107 should be set to open.
JP8
LIN-SEL
LIN3
LIN2
JP9
RIN-SEL
RIN3
RIN2
JP106
MPWR-LIN2
JP107
MPWR-RIN2

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(1-3)LIN3/RIN3 Input Circuit
LIN3/RIN3 is input from J2/J3.
JP8
LIN-SEL
LIN3
LIN2
JP9
RIN-SEL
RIN3
RIN
2
(1-4)Digital Mic Input Circuit
JP102 JP103
RIN1 DMDAT LIN1DMCLK

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(2) Output Circuits
(2-1) HPL/HPR Output Circuit
C65
0.22u
R39
10
C64
0.22u
R38
10
JP13
HPR
R18
16
JP12
HPL
+
C36
(short)
+
C35
(short)
J8
HPL
1 2
3
4
5
J7
HPR
1 2
3
4
5
R19
(short)
R17
(short)
R20
16
HPR
HPL
HP
RCA
HP
RCA
J9
HP/LINE
6
4
3
Figure 8. HPL/HPR Output Circuit
(2-1-1) In case that HPL/HPR is output from J7 and J8. <Default>
JP12
HPL
HPRCA
JP13
HPR
RC
A
HP
(2-2-2) In case that HPL/HPR is output from J9.
JP12
HPL
HPRCA
JP13
HPR
RC
A
HP

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(2-3) SPP/SPN Output Circuit <Default>
J10
SPK/MOUT
6
4
3
R21
(open) R23
(open)
R22
(open)
+
C37
(short)
+
C38
(short)
JP26
(open)
SPN
SPP
Figure 9. SPP/SPN Output Circuit
SPP/SPN is output from J10.
* AKM assumes no responsibility for the trouble when using the above circuit examples.

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AK4953 Control Soft Manual
Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect the evaluation board to an IBM PC/AT compatible PC by a 10wire flat cable. Be aware of the direction of
the 10pin header. When running this control soft on the Windows 2000/XP, the driver which is included in the CD
must be installed. Refer to the “Driver Control Install Manual for AKM Device Control Software” for installing the
driver. When running this control soft on the windows 95/98/ME, driver installing is not necessary. This control soft
does not support the Windows NT.
3. Then please evaluate according to the following descriptions.
Operation Screen
1. Start up the control program following the process above.
2. After the evaluation board’s power is supplied, the AK4953 must be reset once bring SW1 (toggle Switch) “L” to
“H”, and Click [RESET] button.
3. The operation screen is shown below.
Figure 10. Window of Control Soft

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Operation Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching
tab window. Refer to the “Dialog Boxes” for details of each dialog box setting.
1. [Port Reset]: For when connecting to USB I/F board (AKDUSBIF-A)
Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-A).
2. [Write Default]: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executing write commands for all registers displayed.
4. [All Read]: Executing read commands for all registers displayed.
5. [Save]: Saving current register settings to a file.
6. [Load]: Executing data write from a saved file.
7. [All Reg Write]: “All Reg Write” dialog box is popped up.
8. [Data R/W]: “Data R/W” dialog box is popped up.
9. [Sequence]: “Sequence” dialog box is popped up.
10. [Sequence(File)]: “Sequence(File)” dialog box is popped up.
11. [Read]: Reading current register settings and display on to the Register area (on the right of the main window).
This is different from [All Read] button, it does not reflect to a register map, only displaying
hexadecimal.
12. [RESET]:Writes a reset command
After the evaluation board power is supplied, the AK4953 must be reset once bring SW1 (toggle Switch)
“L” to “H”, and then the [RESET] button should be clicked once to reset the register setting of the
AK4953.

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Tab Functions
1. [Function]: Function control
This tab is for function control.
Each operation is executed by the function buttons on the left side of the screen.
Figure 11.Window of [Function]