Alinx AC7Z100 User manual

ZYNQ7000 FPGA
Development Board
AC7Z100
System on Module

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Version Record
Version
Date
Release By
Description
Rev 1.0
2020-06-28
Rachel Zhou
First Release

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Table of Contents
Version Record......................................................................................... 2
Part 1: AC7Z100 Core Board Introduction ................................................ 4
Part 2: ZYNQ Chip ................................................................................... 5
Part 3: DDR3 DRAM ................................................................................ 8
Part 4: QSPI Flash ................................................................................. 14
Part 5: eMMC Flash ............................................................................... 16
Part 6: Clock Configuration..................................................................... 17
Part 7: LED Light.................................................................................... 20
Part 8: Reset circuit................................................................................ 21
Part 9: Power Supply.............................................................................. 22
Part 10: AC7Z100 Core Board Size Dimension...................................... 24
Part 11: Board to Board Connectors Pin Assignment.............................. 25

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Part 1: AC7Z100 Core Board Introduction
AC7Z100 (core board model, the same below) FPGA core board, ZYNQ
chip is based on XC7Z100-2FFG900 of XILINX company ZYNQ7000 series.
The ZYNQ chip's PS system integrates two ARM CortexTM-A9 processors,
AMBA® interconnects, internal memory, external memory interfaces and
peripherals. The FPGA of the ZYNQ chip contains a wealth of programmable
logic cells, DSP and internal RAM.
The core board uses four Micron 512MB DDR3 chips
MT41J256M16HA-125 for a total capacity of 4GB. Two DDR3s are mounted on
the PS and PL sides, respectively, which form a 32-bit bus width. The DDR3
SDRAM on the PS side can run at up to 533MHz (data rate 1066Mbps), and
the DDR3 SDRAM on the PL side can run at speeds up to 800MHz (data rate
1600Mbps). In addition, two 256MBit QSPI FLASH and 8GB eMMC FLASH
chips are integrated on the core board to boot the storage configuration and
system files.
In order to connect with the carrier board, the four board-to-board
connectors of the core board expand the USB interface, the Gigabit Ethernet
interface, the SD card interface and other remaining IO ports of the PS side;
and also extend the 8-pair high-speed transceiver GTX interface of the ZYNQ,
almost all IO ports (144) on the PL side. The level of IO of BANK12 and
BANK13 can be modified by replacing the LDO chip on the core board to meet
the requirements of different level interfaces of users. For users who need a lot
of IO, this core board will be a good choice. Moreover, the IO connection part,
the routing between the ZYNQ chip and the interface is equal length and
differential processing, and the core board size is only 80*60 (mm), which is
very suitable for secondary development.

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Figure 1-1: AC7Z100 Core Board (Front View)
Figure 1-2: AC7Z100 Core Board (Rear View)
Part 2: ZYNQ Chip
The FPGA core board AC7Z100 uses Xilinx's Zynq7000 series chip,

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module XC7Z100-2FFG900. The chip's PS system integrates two ARM
Cortex™-A9 processors, AMBA® interconnects, internal memory, external
memory interfaces and peripherals. These peripherals mainly include USB bus
interface, Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus
interface, UART interface, GPIO etc. The PS can operate independently and
start up at power on or reset. Figure 2-1 detailed the Overall Block Diagram of
the ZYNQ7000 Chip.
Figure 2-1: Overall Block Diagram of the ZYNQ7000 Chip
The main parameters of the PS system part are as follows:
ARM dual-core CortexA9-based application processor, ARM-v7
architecture, up to 800MHz
32KB level 1 instruction and data cache per CPU, 512KB level 2 cache
2 CPU shares
On-chip boot ROM and 256KB on-chip RAM
External storage interface, support 16/32 bit DDR2, DDR3 interface
Two Gigabit NIC support: divergent-aggregate DMA, GMII, RGMII,

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SGMII interface
Two USB2.0 OTG interfaces, each supporting up to 12 nodes
Two CAN2.0B bus interfaces
Two SD card, SDIO, MMC compatible controllers
2 SPIs, 2 UARTs, 2 I2C interfaces
54 multi-function IOs that can be configured as normal IO or peripheral
control interfaces
High bandwidth connection within PS and PS to PL
The main parameters of the PL logic part are as follows:
Logic Cells: 444K
Look-up-tables (LUTs): 277440
Flip-flops: 554,800
18x25MACCs：2020
 Block RAM ： 26.5Mb
16-channel high-speed GTX transceiver, supporting PCIE Gen2x8;
Two AD converters for on-chip voltage, temperature sensing and up
to 17 external differential input channels, 1MBPS
XC7Z100-2FFG900I chip speed grade is -2, industrial grade, package is
FGG900, pin pitch is 1.0mm the specific chip model definition of ZYNQ7000
series is shown in Figure 2-2

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Figure 2-2: The Specific Chip Model Definition of ZYNQ7000 Series
Figure 2-3: The XC7Z100 chip used on the Core Board
Part 3: DDR3 DRAM
The FPGA core board AC7Z100 is equipped with four Micron 512MB
DDR3 chips, model MT41J256M16HA-125 (compatible with
MT41K256M16HA-125), in which Two DDR3s are mounted on the PS and PL

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sides respectively. Two DDR3 SDRAMs form a 32-bit bus width. The PS-side
DDR3 SDRAM has a maximum operating speed of 533MHz (data rate
1066Mbps), and two DDR3 memory systems are directly connected to the
memory interface of the BANK 502 of the ZYNQ Processing System (PS). The
PL-side DDR3 SDRAM has a maximum operating speed of 800MHz (data rate
1600Mbps), and two DDR3 memory systems are connected to the BANK33
and BANK34 interfaces of the FPGA. The specific configuration of DDR3
SDRAM is shown in Table 3-1.
Bit Number
Chip Model
Capacity
Factory
U4,U5,U7,U8
MT41J256M16HA-125
256M x 16bit
Micron
Table 3-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
Figure 3-1: The Schematic Part of DDR3 DRAM on the PS side

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Figure 3-2: The Schematic Part of DDR3 DRAM on the PL side
PS side DDR3 DRAM pin assignment:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
PS_DDR3_DQS0_P
PS_DDR_DQS_P0_502
C26
PS_DDR3_DQS0_N
PS_DDR_DQS_N0_502
B26
PS_DDR3_DQS1_P
PS_DDR_DQS_P1_502
C29
PS_DDR3_DQS1_N
PS_DDR_DQS_N1_502
B29
PS_DDR3_DQS2_P
PS_DDR_DQS_P2_502
G29
PS_DDR3_DQS2_N
PS_DDR_DQS_N2_502
F29
PS_DDR3_DQS3_P
PS_DDR_DQS_P3_502
L28
PS_DDR3_DQS4_N
PS_DDR_DQS_N3_502
L29
PS_DDR3_D0
PS_DDR_DQ0_502
A25
PS_DDR3_D1
PS_DDR_DQ1_502
E25
PS_DDR3_D2
PS_DDR_DQ2_502
B27
PS_DDR3_D3
PS_DDR_DQ3_502
D25
PS_DDR3_D4
PS_DDR_DQ4_502
B25
PS_DDR3_D5
PS_DDR_DQ5_502
E26
PS_DDR3_D6
PS_DDR_DQ6_502
D26
PS_DDR3_D7
PS_DDR_DQ7_502
E27
PS_DDR3_D8
PS_DDR_DQ8_502
A29

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PS_DDR3_D9
PS_DDR_DQ9_502
A27
PS_DDR3_D10
PS_DDR_DQ10_502
A30
PS_DDR3_D11
PS_DDR_DQ11_502
A28
PS_DDR3_D12
PS_DDR_DQ12_502
C28
PS_DDR3_D13
PS_DDR_DQ13_502
D30
PS_DDR3_D14
PS_DDR_DQ14_502
D28
PS_DDR3_D15
PS_DDR_DQ15_502
D29
PS_DDR3_D16
PS_DDR_DQ16_502
H27
PS_DDR3_D17
PS_DDR_DQ17_502
G27
PS_DDR3_D18
PS_DDR_DQ18_502
H28
PS_DDR3_D19
PS_DDR_DQ19_502
E28
PS_DDR3_D20
PS_DDR_DQ20_502
E30
PS_DDR3_D21
PS_DDR_DQ21_502
F28
PS_DDR3_D22
PS_DDR_DQ22_502
G30
PS_DDR3_D23
PS_DDR_DQ23_502
F30
PS_DDR3_D24
PS_DDR_DQ24_502
J29
PS_DDR3_D25
PS_DDR_DQ25_502
K27
PS_DDR3_D26
PS_DDR_DQ26_502
J30
PS_DDR3_D27
PS_DDR_DQ27_502
J28
PS_DDR3_D28
PS_DDR_DQ28_502
K30
PS_DDR3_D29
PS_DDR_DQ29_502
M29
PS_DDR3_D30
PS_DDR_DQ30_502
L30
PS_DDR3_D31
PS_DDR_DQ31_502
M30
PS_DDR3_DM0
PS_DDR_DM0_502
C27
PS_DDR3_DM1
PS_DDR_DM1_502
B30
PS_DDR3_DM2
PS_DDR_DM2_502
H29
PS_DDR3_DM3
PS_DDR_DM3_502
K28
PS_DDR3_A0
PS_DDR_A0_502
L25
PS_DDR3_A1
PS_DDR_A1_502
K26
PS_DDR3_A2
PS_DDR_A2_502
L27
PS_DDR3_A3
PS_DDR_A3_502
G25
PS_DDR3_A4
PS_DDR_A4_502
J26
PS_DDR3_A5
PS_DDR_A5_502
G24

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PS_DDR3_A6
PS_DDR_A6_502
H26
PS_DDR3_A7
PS_DDR_A7_502
K22
PS_DDR3_A8
PS_DDR_A8_502
F27
PS_DDR3_A9
PS_DDR_A9_502
J23
PS_DDR3_A10
PS_DDR_A10_502
G26
PS_DDR3_A11
PS_DDR_A11_502
H24
PS_DDR3_A12
PS_DDR_A12_502
K23
PS_DDR3_A13
PS_DDR_A13_502
H23
PS_DDR3_A14
PS_DDR_A14_502
J24
PS_DDR3_BA0
PS_DDR_BA0_502
M27
PS_DDR3_BA1
PS_DDR_BA1_502
M26
PS_DDR3_BA2
PS_DDR_BA2_502
M25
PS_DDR3_S0
PS_DDR_CS_B_502
N22
PS_DDR3_RAS
PS_DDR_RAS_B_502
N24
PS_DDR3_CAS
PS_DDR_CAS_B_502
M24
PS_DDR3_WE
PS_DDR_WE_B_502
N23
PS_DDR3_ODT
PS_DDR_ODT_502
L23
PS_DDR3_RESET
PS_DDR_DRST_B_502
F25
PS_DDR3_CLK0_P
PS_DDR_CKP_502
K25
PS_DDR3_CLK0_N
PS_DDR_CKN_502
J25
PS_DDR3_CKE
PS_DDR_CKE_502
M22
PL side DDR3 DRAM pin assignment:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
PL_DDR3_DQS0_P
IO_L3P_T0_DQS_33
K3
PL_DDR3_DQS0_N
IO_L3N_T0_DQS_33
K2
PL_DDR3_DQS1_P
IO_L9P_T1_DQS_33
J1
PL_DDR3_DQS1_N
IO_L9N_T1_DQS_33
H1
PL_DDR3_DQS2_P
IO_L15P_T2_DQS_33
E6
PL_DDR3_DQS2_N
IO_L15N_T2_DQS_33
D5
PL_DDR3_DQS3_P
IO_L21P_T3_DQS_33
A5
PL_DDR3_DQS4_N
IO_L21N_T3_DQS_33
A4
PL_DDR3_D0
IO_L5N_T0_33
J3

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PL_DDR3_D1
IO_L1N_T0_33
L2
PL_DDR3_D2
IO_L4P_T0_33
J4
PL_DDR3_D3
IO_L1P_T0_33
L3
PL_DDR3_D4
IO_L2N_T0_33
K1
PL_DDR3_D5
IO_L5P_T0_33
K6
PL_DDR3_D6
IO_L2P_T0_33
J5
PL_DDR3_D7
IO_L4N_T0_33
K5
PL_DDR3_D8
IO_L7N_T1_33
H4
PL_DDR3_D9
IO_L10N_T1_33
G1
PL_DDR3_D10
IO_L7P_T1_33
H6
PL_DDR3_D11
IO_L8N_T1_33
F2
PL_DDR3_D12
IO_L11N_T1_SRCC_33
H2
PL_DDR3_D13
IO_L8P_T1_33
G4
PL_DDR3_D14
IO_L11P_T1_SRCC_33
G6
PL_DDR3_D15
IO_L10P_T1_33
H3
PL_DDR3_D16
IO_L18P_T2_33
E1
PL_DDR3_D17
IO_L14P_T2_SRCC_33
E3
PL_DDR3_D18
IO_L14N_T2_SRCC_33
D3
PL_DDR3_D19
IO_L13P_T2_MRCC_33
F4
PL_DDR3_D20
IO_L16P_T2_33
D1
PL_DDR3_D21
IO_L17P_T2_33
E5
PL_DDR3_D22
IO_L16N_T2_33
D4
PL_DDR3_D23
IO_L17N_T2_33
E2
PL_DDR3_D24
IO_L23P_T3_33
C2
PL_DDR3_D25
IO_L22N_T3_33
A2
PL_DDR3_D26
IO_L19P_T3_33
B4
PL_DDR3_D27
IO_L20N_T3_33
B5
PL_DDR3_D28
IO_L24P_T3_33
C1
PL_DDR3_D29
IO_L20P_T3_33
A3
PL_DDR3_D30
IO_L24N_T3_33
C4
PL_DDR3_D31
IO_L22P_T3_33
B2
PL_DDR3_DM0
IO_L6P_T0_33
L1
PL_DDR3_DM1
IO_L12P_T1_MRCC_33
G5

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PL_DDR3_DM2
IO_L13N_T2_MRCC_33
F3
PL_DDR3_DM3
IO_L23N_T3_33
B1
PL_DDR3_A0
IO_L17N_T2_34
H7
PL_DDR3_A1
IO_L23P_T3_34
L8
PL_DDR3_A2
IO_L14P_T2_SRCC_34
H11
PL_DDR3_A3
IO_L15N_T2_DQS_34
D10
PL_DDR3_A4
IO_L10N_T1_34
H8
PL_DDR3_A5
IO_L17P_T2_34
D11
PL_DDR3_A6
IO_L11N_T1_SRCC_34
L7
PL_DDR3_A7
IO_L15P_T2_DQS_34
E10
PL_DDR3_A8
IO_L12N_T1_MRCC_34
L10
PL_DDR3_A9
IO_L18N_T2_34
H12
PL_DDR3_A10
IO_L24N_T3_34
G7
PL_DDR3_A11
IO_L11P_T1_SRCC_34
J9
PL_DDR3_A12
IO_L23N_T3_34
H9
PL_DDR3_A13
IO_L16P_T2_34
J11
PL_DDR3_A14
IO_L12P_T1_MRCC_34
K10
PL_DDR3_BA0
IO_L18P_T2_34
K11
PL_DDR3_BA1
IO_L19N_T3_VREF_34
K8
PL_DDR3_BA2
IO_L22N_T3_34
G11
PL_DDR3_S0
IO_L14N_T2_SRCC_34
F8
PL_DDR3_RAS
IO_L19P_T3_34
G9
PL_DDR3_CAS
IO_L20N_T3_34
E7
PL_DDR3_WE
IO_L20P_T3_34
F7
PL_DDR3_ODT
IO_L22P_T3_34
J10
PL_DDR3_RESET
IO_L16N_T2_34
E11
PL_DDR3_CLK0_P
IO_L21P_T3_DQS_34
D9
PL_DDR3_CLK0_N
IO_L21N_T3_DQS_34
D8
PL_DDR3_CKE
IO_L24P_T3_34
D6
Part 4: QSPI Flash
The FPGA core board AC7Z100 is equipped with two 256MBit Quad-SPI
FLASH chips to form an 8-bit bandwidth data bus, the flash model is

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W25Q256FVEI, which uses the 3.3V CMOS voltage standard. Due to the
non-volatile nature of QSPI FLASH, it can be used as a boot device for the
system to store the boot image of the system. These images mainly include
FPGA bit files, ARM application code, and other user data files. The specific
models and related parameters of QSPI FLASH are shown in Table 4-1.
Position
Model
Capacity
Factory
U13,U14
W25Q256FVEI
256M bit
Winbond
Table 4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure 4-1
shows the QSPI Flash in the schematic.
Figure 4-1: QSPI Flash in the schematic
Configure chip pin assignments:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
QSPI0_SCK
PS_MIO6_500
D24

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QSPI0_CS
PS_MIO1_500
D23
QSPI0_D0
PS_MIO2_500
F23
QSPI0_D1
PS_MIO3_500
C23
QSPI0_D2
PS_MIO4_500
E23
QSPI0_D3
PS_MIO5_500
C24
QSPI1_SCK
PS_MIO9_500
A24
QSPI1_CS
PS_MIO0_500
F24
QSPI1_D0
PS_MIO10_500
E22
QSPI1_D1
PS_MIO11_500
A23
QSPI1_D2
PS_MIO12_500
E21
QSPI1_D3
PS_MIO13_500
F22
Part 5: eMMC Flash
The FPGA core board AC7Z100 is equipped with a large-capacity 8GB
eMMC FLASH chip, model THGBMFG6C1LBAIL, which supports the JEDEC
e-MMC V5.0 standard HS-MMC interface with level support of 1.8V or 3.3V.
The data width of the eMMC FLASH and ZYNQ connections is 4 bits. Due to
the large capacity and non-volatile nature of eMMC FLASH, it can be used as a
large-capacity storage device for the ZYNQ system, such as ARM applications,
system files and other user data files. The specific models and related
parameters of eMMC FLASH are shown in Table 5-1.
Position
Model
Capacity
Factory
U15
THGBMFG6C1LBAIL
8G Byte
TOSHIBA
Table 5-1: eMMC FLASH Specification
eMMC FLASH is connected to the GPIO port of the BANK501 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the SD interface. Figure 5-1 shows the
eMMC Flash in the schematic.

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ZYNQ eMMC
(THGBMFG6C1
LBAIL)
MMC_CCLK
U11
U1
BANK
501
MMC_CMD
MMC_DAT0~MMC_DAT3
Figure 5-1: eMMC Flash in the Schematic
Pin Assignment of eMMC Flash
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
MMC_CCLK
PS_MIO48_501
C19
MMC_CMD
PS_MIO47_501
A18
MMC_D0
PS_MIO46_501
F20
MMC_D1
PS_MIO49_501
D18
MMC_D2
PS_MIO50_501
A19
MMC_D3
PS_MIO51_501
F19
Part 6: Clock Configuration
The core system provides a reference clock for the PS system, the PL
logic section, and the GTX transceiver, allowing the PS system and PL logic to
work independently. The schematic diagram of the clock circuit design is shown
in Figure 6-1:

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ǁ
ǁǁǁ ǁ
ǁ
ǁǁǁ ǁ
Figure 6-1: Clock source in the Core Board
PS system clock source
The ZYNQ chip provides a 33.333MHz clock input to the PS section via
the X4 crystal on the FPGA core board AC7Z100. The input of the clock is
connected to the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip.
The schematic diagram is shown in Figure 6-2:
Figure 6-2: Active crystal oscillator to the PS section
PS Clock Pin Assignment
Signal Name
ZYNQ Pin
PS_CLK
A22
BANK
500
ZYNQ
Single-ended Clock
33.33 Mhz
BANK
34
Differential Clock
200 Mhz
BANK
111
Differential Clock
200 Mhz
PS_CLCK
SYS_CLCK_P
SYS_CLCK_N
Bank111_CLK1_P
Bank111_CLK1_N

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PL system clock source
The differential 200MHz PL system clock source is provided on the FPGA
core board AC7Z100 for the reference clock of the DDR3 controller. The crystal
output is connected to the global clock (MRCC) of the FPGA BANK34, which
can be used to drive the DDR3 controller and user logic in the FPGA. The
schematic diagram of the clock source is shown in Figure 6-3
Figure 6-3: PL system clock source
PL Clock pin assignment:
Signal Name
ZYNQ Pin
SYS_CLK_P
F9
SYS_CLK_N
E8
GTX reference clock
The FPGA core board AC7Z100 provides a 125Mhz reference clock for
the GTX transceiver. The reference clock is connected to the reference clock
input REFCLK1P/REFCLK1N of the BANK111. The schematic diagram of the
clock source is shown in Figure 6-4.

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Figure 6-4: GTX Clock Source
Figure 6-5: Programmable Clock Source on the AX7Z100 FPGA Core Board
GTX clock source ZYNQ pin assignment:：
Signal Name
ZYNQ Pin
BANK111_CLK1_P
AC8
BANK111_CLK1_N
AC7
Part 7: LED Light
There are 2 red LED lights on the AC7Z100 FPGA core board, one of
which is the power indicator light (PWR), one is the configuration LED light
(DONE). When the core board is powered, the power indicator will illuminate;
when the FPGA is configured, the configuration LED will illuminate. The
schematic diagram of the LED light hardware connection is shown in Figure
7-1: