Alinx ZYNQ7000 FPGA User manual

ZYNQ7000 FPGA
Development Board
AX7350B
User Manual

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Version Record
Revision
Date
Release By
Description
Rev 1.0
2019-04-05
Rachel Zhou
First Release

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Table of Contents
Version Record......................................................................................... 2
Part 1: FPGA Development Board Introduction ........................................ 5
Part 2: ZYNQ Chip ................................................................................... 9
Part 3: DDR3 DRAM .............................................................................. 12
Part 4: QSPI Flash ................................................................................. 18
Part 5：eMMC Flash.............................................................................. 19
Part 6: Clock Configuration..................................................................... 20
Part 7: USB to Serial Port....................................................................... 24
Part 8: Gigabit Ethernet Interface ........................................................... 25
Part 9: USB2.0 Host Interface ................................................................ 28
Part 10: HDMI Output Interface .............................................................. 30
Part 11: SFP Interface ............................................................................ 31
Part 12: PCIe Slot................................................................................... 33
Part 13: SD Card Slot............................................................................. 35
Part 14: FMC Connector......................................................................... 36
Part 15: LED Light.................................................................................. 40
Part 16: Reset Button and User Button .................................................. 41
Part17: JTAG Debug Port....................................................................... 42
Part 18: DIP Switch Configuration .......................................................... 43
Part 19: Power Supply............................................................................ 43
Part 20: Fan ........................................................................................... 45
Part 21: Dimensional structure ............................................................... 46

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The ZYNQ7000 FPGA development platform uses XILINX's Zynq7000
SOC chip XC7Z035 solution, which uses ARM+FPGA SOC technology to
integrate dual-core ARM Cortex-A9 and FPGA programmable logic on a single
chip. ZYNQ has two 512MB high-speed DDR3 SDRAM chips on the PS and PL
sides. In addition, there are one 8GB eMMC memory chip and one 256Mb
QSPI FLASH chip on the PS side.
In terms of peripheral circuits, we have extended a wealth of interfaces for
users, such as a PCIex4 slot, 2 fiber interfaces, 2 Gigabit Ethernet interfaces, 4
USB2.0 HOST interfaces, 1 HDMI output interface, 1 channel UART serial
interface, 1 SD card interface, and an FMC expansion interface. It meets users'
requirements for high-speed data exchange, data storage, video transmission
processing and industrial control. It is a "professional" ZYNQ development
platform. For high-speed data transmission and exchange, pre-verification and
post-application of data processing is possible. This product is very suitable for
students, engineers and other groups engaged in ZYNQ development.

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Part 1: FPGA Development Board Introduction
The AX7350B FPGA development board is mainly composed of
ZYNQ7350 main chip, 4 DDR3, 1 eMMC, 1 QSPI FLASH and some peripheral
interfaces. The ZYNQ7350 uses Xilinx's Zynq7000 series of chips, model
number XC7Z035-2FFG676. The ZYNQ7035 chip can be divided into
Processor System (PS) and Programmable Logic (PL). On the PS and PL
sides of the ZYNQ7350 chip, two DDR3s are mounted, each with a DDR3
capacity of up to 512 Mbytes. The ARM system and the FPGA system can
independently process and store data. The PS-side 8GB eMMC FLASH
memory chip and 256Mb QSPI FLASH are used to statically store ZYNQ's
operating system, file system and user data.
The AX7350B FPGA development board expands its rich peripheral
interface, including one PCIex4 slot, two SFP interfaces, two Gigabit Ethernet
interfaces, four USB2.0 HOST interfaces, one HDMI output interface, and one
UART serial interface. 1 SD card interface, 1 FMC expansion interface and
some button LEDs.
Figure 1-1 is the Schematic diagram of the entire FPGA development
boards:

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LED&KEY
KSZ9031R
以太网网
口
CP2102
USB
UART
PCIE插槽
ADV7511
HDMI输出
FMC
扩展口
JTAG
USB3320
C
2 *
USB接口
USB2514
2 *
USB接口
TXS0261
2RTWR
SD Card
XILINX
ZYNQ7000
XC7Z035FFG676-2
50Mhz
33.33
3Mhz
DDR3DDR3
QSPI
FLASH
eMMC
FLASH
KSZ9031R
以太网网
口
FT232HL
DDR3DDR3
SI5338
SFP1
SFP2
50Mhz
Figure 1-1: The Schematic Diagram of the AX7350B
Through this diagram, you can see the interfaces and functions that the
AX7350B FPGA Development Board contains:
Xilinx ARM+FPGA chip Zynq-7000 XC7Z035-2FFG676
DDR3
With four large-capacity 512M bytes (2GB total), high-speed DDR3
SDRAM. Two of them are mounted on the PS side, which can be used
as a buffer for ZYNQ chip data, or as a memory for the operating
system. The other two are attached to the PL end and can be used as
data storage, image analysis cache, and data processing of the FPGA.
eMMC

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The PS side mounts an 8GB eMMC FLASH memory chip to store user
operating system files or other user data.
QSPI FLASH
A 256Mbit QSPI FLASH memory chip can be used as a Uboot file for
ZYNQ chips, storage of system files and user data;
PCIe x4 Interface
The standard PCIEx8 host slot is used for PCIEx4 communication, and
can be used to connect PCIEx4, x2, x1 PCIE boards for PCIE data
communication. Support the PCI Express 2.0 standard with single
channel communication, rates up to 5GBaud.
2 SFP Interface
The 2-channel high-speed transceiver of ZYNQ's GTX transceiver is
connected to the transmission and reception of two optical modules to
realize two high-speed optical fiber communication interfaces. Each
fiber optic data communication receives and transmits at speeds of up
to 10 Gb/s.
Gigabite Ethernet Interface
2-channel 10/100M/1000M Ethernet RJ45 interface for Ethernet data
exchange with computers or other network devices. The network
interface chip uses Micrel's KSZ9031 industrial grade GPHY chip, one
Ethernet is connected to the PS end of the ZYNQ chip, and one
Ethernet is connected to the PL end of the ZYNQ chip.
HDMI video output
1 channel HDMI video output interface, selected ADV7511 HDMI
encoding chip of ANALOG DEVICE, up to 1080P@60Hz output,
support 3D output.
USB2.0 HOST Interface
Extend the 4-channe USB HOST interface through the USB Hub chip
for connecting external USB slave devices, such as connecting a

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mouse, keyboard, USB flash drive etc. The USB interface uses a flat
USB interface (USB Type A).
USB Uart Interface
2-way Uart to USB interfaces for communication with the computer, for
user debugging. 1 channel on the core board, Used for the core board
works independently; 1 way is on the bottom board, and used for the
whole board debugging. The serial port chip adopts the USB-UAR chip
of Silicon Labs CP2102GM, and the USB interface adopts the MINI
USB interface.
Micro SD card holder
1-channel Micro SD card holder, for save operating system images and
file systems.
FMC expansion port
A standard FMC LPC expansion port for connecting XILINX or
ALINXDE various FMC modules (HDMI input and output modules,
binocular camera modules, high-speed AD modules etc.). The FMC
expansion port contains 34 pairs of differential IO signals and one
high-speed GTX transceiver signal.
USB JTAG Interface
One way USB JTAG port, debug and download ZYNQ system through
USB cable and onboard JTAG circuit
Clock
An on-board 33.333Mhz active crystal oscillator provides a stable clock
source for the PS system, a 50MHz active crystal oscillator that
provides additional clocking for the PL logic, and a programmable clock
chip on the board that provides the clock source for the GTX. Provide a
reference clock for PCIE, SFP and DDR operation.
LED Light
9 LEDs, 1 power indicator; 1 DONE configuration indicator; 2 serial

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communication indicators, 1 PS control LED, 4 PL control indicators.
Button
6 buttons, 1 reset button, 1 PS user button, 4 PL user buttons
Part 2: ZYNQ Chip
The AX7350B FPGA development board uses Xilinx's Zynq7000 series
chip, model XC7Z035-2FFG676. The chip's PS system integrates two ARM
CortexTM-A9 processors, AMBA® interconnects, internal memory, external
memory interfaces and peripherals. These peripherals mainly include USB bus
interface, Ethernet interface, SD/SDIO interface, I2C bus interface, CAN bus
interface, UART interface, GPIO etc. The PS can operate independently and
start up at power up or reset. Figure 2-1 detailed the Overall Block Diagram of
the ZYNQ7000 Chip.
Figure 2-1:
Overall Block Diagram of the ZYNQ7000 Chip

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The main parameters of the PS system part are as follows:
ARM dual-core CortexA9-based application processor, ARM-v7
architecture, up to 800MHz
32KB level 1 instruction and data cache per CPU, 512KB level 2 cache
2 CPU shares
On-chip boot ROM and 256KB on-chip RAM
External storage interface, support 16/32 bit DDR2, DDR3 interface
Two Gigabit NIC support: divergent-aggregate DMA, GMII, RGMII,
SGMII interface
Two USB2.0 OTG interfaces, each supporting up to 12 nodes
Two CAN2.0B bus interfaces
Two SD card, SDIO, MMC compatible controllers
2 SPIs, 2 UARTs, 2 I2C interfaces
54 multi-function IOs that can be configured as normal IO or peripheral
control interfaces
High bandwidth connection within PS and PS to PL
The main parameters of the PL logic part are as follows:
Logic Cells: 275K
Look-up-tables (L U Ts ) : 171,900
Flip-flops: 343,800
18x25MACCs：900

Block RAM ： 17.6Mb
8-channel high-speed GTX transceiver, supporting PCIE Gen2x8;
Two AD converters for on-chip voltage, temperature sensing and up
to 17 external differential input channels, 1MBPS
XC7Z020-2CLG484I chip speed grade is -2, industrial grade, package is

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FGG676, pin pitch is 1.0mm the specific chip model definition of ZYNQ7000
series is shown in Figure 2-2
Figure 2-2: The Specific Chip Model Definition of ZYNQ7000 Series
Figure 2-3: The XC7Z035 chip used on the Core Board

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Part 3: DDR3 DRAM
The AX7350B FPGA development board is equipped with four Micron
512MB DDR3 chips, model MT41J256M16HA-125 (compatible with
MT41K256M16HA-125), in which Two DDR3s are mounted on the PS and PL
sides. Two DDR3 SDRAMs form a 32-bit bus width. The PS-side DDR3
SDRAM has a maximum operating speed of 533MHz (data rate 1066Mbps),
and two DDR3 memory systems are directly connected to the memory
interface of the BANK 502 of the ZYNQ Processing System (PS). The PL-side
DDR3 SDRAM has a maximum operating speed of 800MHz (data rate
1600Mbps), and two DDR3 memory systems are connected to the BANK33
and BANK34 interfaces of the FPGA. The specific configuration of DDR3
SDRAM is shown in Table 3-1.
Bit Number Chip Model Capacity Factory
U4,U5,U7,U8
MT41J256M16HA-125
256M x 16bit
Micron
Table 3-1: DDR3 SDRAM Configuration
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.

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Figure 3-1: The Schematic Part of DDR3 DRAM on the PS side
Figure 3-2: The Schematic Part of DDR3 DRAM on the PL side
PS side DDR3 DRAM pin assignment:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
PS_DDR3_DQS0_P
PS_DDR_DQS_P0_502
H24
PS_DDR3_DQS0_N
PS_DDR_DQS_N0_502
G25
PS_DDR3_DQS1_P
PS_DDR_DQS_P1_502
L24
PS_DDR3_DQS1_N
PS_DDR_DQS_N1_502
L25
PS_DDR3_DQS2_P
PS_DDR_DQS_P2_502
P25
PS_DDR3_DQS2_N
PS_DDR_DQS_N2_502
R25

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PS_DDR3_DQS3_P
PS_DDR_DQS_P3_502
W24
PS_DDR3_DQS4_N
PS_DDR_DQS_N3_502
W25
PS_DDR3_D0
PS_DDR_DQ0_502
J26
PS_DDR3_D1
PS_DDR_DQ1_502
F25
PS_DDR3_D2
PS_DDR_DQ2_502
J25
PS_DDR3_D3
PS_DDR_DQ3_502
G26
PS_DDR3_D4
PS_DDR_DQ4_502
H26
PS_DDR3_D5
PS_DDR_DQ5_502
H23
PS_DDR3_D6
PS_DDR_DQ6_502
J24
PS_DDR3_D7
PS_DDR_DQ7_502
J23
PS_DDR3_D8
PS_DDR_DQ8_502
K26
PS_DDR3_D9
PS_DDR_DQ9_502
L23
PS_DDR3_D10
PS_DDR_DQ10_502
M26
PS_DDR3_D11
PS_DDR_DQ11_502
K23
PS_DDR3_D12
PS_DDR_DQ12_502
M25
PS_DDR3_D13
PS_DDR_DQ13_502
N24
PS_DDR3_D14
PS_DDR_DQ14_502
M24
PS_DDR3_D15
PS_DDR_DQ15_502
N23
PS_DDR3_D16
PS_DDR_DQ16_502
R26
PS_DDR3_D17
PS_DDR_DQ17_502
P24
PS_DDR3_D18
PS_DDR_DQ18_502
N26
PS_DDR3_D19
PS_DDR_DQ19_502
P23
PS_DDR3_D20
PS_DDR_DQ20_502
T24
PS_DDR3_D21
PS_DDR_DQ21_502
T25
PS_DDR3_D22
PS_DDR_DQ22_502
T23
PS_DDR3_D23
PS_DDR_DQ23_502
R23
PS_DDR3_D24
PS_DDR_DQ24_502
V24
PS_DDR3_D25
PS_DDR_DQ25_502
U26
PS_DDR3_D26
PS_DDR_DQ26_502
U24
PS_DDR3_D27
PS_DDR_DQ27_502
U25
PS_DDR3_D28
PS_DDR_DQ28_502
W26
PS_DDR3_D29
PS_DDR_DQ29_502
Y25
PS_DDR3_D30
PS_DDR_DQ30_502
Y26
PS_DDR3_D31
PS_DDR_DQ31_502
W23
PS_DDR3_DM0
PS_DDR_DM0_502
G24
PS_DDR3_DM1
PS_DDR_DM1_502
K25

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PS_DDR3_DM2
PS_DDR_DM2_502
P26
PS_DDR3_DM3
PS_DDR_DM3_502
V26
PS_DDR3_A0
PS_DDR_A0_502
K22
PS_DDR3_A1
PS_DDR_A1_502
K20
PS_DDR3_A2
PS_DDR_A2_502
N21
PS_DDR3_A3
PS_DDR_A3_502
L22
PS_DDR3_A4
PS_DDR_A4_502
M20
PS_DDR3_A5
PS_DDR_A5_502
N22
PS_DDR3_A6
PS_DDR_A6_502
L20
PS_DDR3_A7
PS_DDR_A7_502
J21
PS_DDR3_A8
PS_DDR_A8_502
T20
PS_DDR3_A9
PS_DDR_A9_502
U20
PS_DDR3_A10
PS_DDR_A10_502
M22
PS_DDR3_A11
PS_DDR_A11_502
H21
PS_DDR3_A12
PS_DDR_A12_502
P20
PS_DDR3_A13
PS_DDR_A13_502
J20
PS_DDR3_A14
PS_DDR_A14_502
R20
PS_DDR3_BA0
PS_DDR_BA0_502
U22
PS_DDR3_BA1
PS_DDR_BA1_502
T22
PS_DDR3_BA2
PS_DDR_BA2_502
R22
PS_DDR3_S0
PS_DDR_CS_B_502
Y21
PS_DDR3_RAS
PS_DDR_RAS_B_502
V23
PS_DDR3_CAS
PS_DDR_CAS_B_502
Y23
PS_DDR3_WE
PS_DDR_WE_B_502
V22
PS_DDR3_ODT
PS_DDR_ODT_502
Y22
PS_DDR3_RESET
PS_DDR_DRST_B_502
H22
PS_DDR3_CLK0_P
PS_DDR_CKP_502
R21
PS_DDR3_CLK0_N
PS_DDR_CKN_502
P21
PS_DDR3_CKE
PS_DDR_CKE_502
U21
PL side DDR3 DRAM pin assignment:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
PL_DDR3_DQS0_P
IO_L3P_T0_DQS_33
G2
PL_DDR3_DQS0_N
IO_L3N_T0_DQS_33
F2
PL_DDR3_DQS1_P
IO_L9P_T1_DQS_33
K2

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PL_DDR3_DQS1_N
IO_L9N_T1_DQS_33
K1
PL_DDR3_DQS2_P
IO_L15P_T2_DQS_33
N3
PL_DDR3_DQS2_N
IO_L15N_T2_DQS_33
N2
PL_DDR3_DQS3_P
IO_L21P_T3_DQS_33
M8
PL_DDR3_DQS4_N
IO_L21N_T3_DQS_33
L8
PL_DDR3_D0
IO_L5N_T0_33
E1
PL_DDR3_D1
IO_L1N_T0_33
F4
PL_DDR3_D2
IO_L4P_T0_33
D1
PL_DDR3_D3
IO_L1P_T0_33
G4
PL_DDR3_D4
IO_L2N_T0_33
D3
PL_DDR3_D5
IO_L5P_T0_33
E2
PL_DDR3_D6
IO_L2P_T0_33
D4
PL_DDR3_D7
IO_L4N_T0_33
C1
PL_DDR3_D8
IO_L7N_T1_33
H1
PL_DDR3_D9
IO_L10N_T1_33
G1
PL_DDR3_D10
IO_L7P_T1_33
J1
PL_DDR3_D11
IO_L8N_T1_33
H3
PL_DDR3_D12
IO_L11N_T1_SRCC_33
K3
PL_DDR3_D13
IO_L8P_T1_33
H4
PL_DDR3_D14
IO_L11P_T1_SRCC_33
L3
PL_DDR3_D15
IO_L10P_T1_33
H2
PL_DDR3_D16
IO_L18P_T2_33
N1
PL_DDR3_D17
IO_L14P_T2_SRCC_33
L5
PL_DDR3_D18
IO_L14N_T2_SRCC_33
L4
PL_DDR3_D19
IO_L13P_T2_MRCC_33
M6
PL_DDR3_D20
IO_L16P_T2_33
M2
PL_DDR3_D21
IO_L17P_T2_33
N4
PL_DDR3_D22
IO_L16N_T2_33
L2
PL_DDR3_D23
IO_L17N_T2_33
M4
PL_DDR3_D24
IO_L23P_T3_33
N7
PL_DDR3_D25
IO_L22N_T3_33
J6
PL_DDR3_D26
IO_L19P_T3_33
M7
PL_DDR3_D27
IO_L20N_T3_33
J5
PL_DDR3_D28
IO_L24P_T3_33
K8
PL_DDR3_D29
IO_L20P_T3_33
K5
PL_DDR3_D30
IO_L24N_T3_33
K7

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PL_DDR3_D31
IO_L22P_T3_33
K6
PL_DDR3_DM0
IO_L6P_T0_33
F3
PL_DDR3_DM1
IO_L12P_T1_MRCC_33
J4
PL_DDR3_DM2
IO_L13N_T2_MRCC_33
M5
PL_DDR3_DM3
IO_L23N_T3_33
N6
PL_DDR3_A0
IO_L17N_T2_34
A8
PL_DDR3_A1
IO_L23P_T3_34
C2
PL_DDR3_A2
IO_L14P_T2_SRCC_34
D6
PL_DDR3_A3
IO_L15N_T2_DQS_34
B9
PL_DDR3_A4
IO_L10N_T1_34
D5
PL_DDR3_A5
IO_L17P_T2_34
A9
PL_DDR3_A6
IO_L11N_T1_SRCC_34
E7
PL_DDR3_A7
IO_L15P_T2_DQS_34
C9
PL_DDR3_A8
IO_L12N_T1_MRCC_34
F7
PL_DDR3_A9
IO_L18N_T2_34
A7
PL_DDR3_A10
IO_L24N_T3_34
A2
PL_DDR3_A11
IO_L11P_T1_SRCC_34
F8
PL_DDR3_A12
IO_L23N_T3_34
B1
PL_DDR3_A13
IO_L16P_T2_34
B10
PL_DDR3_A14
IO_L12P_T1_MRCC_34
G7
PL_DDR3_BA0
IO_L18P_T2_34
B7
PL_DDR3_BA1
IO_L19N_T3_VREF_34
C3
PL_DDR3_BA2
IO_L22N_T3_34
A3
PL_DDR3_S0
IO_L14N_T2_SRCC_34
C6
PL_DDR3_RAS
IO_L19P_T3_34
C4
PL_DDR3_CAS
IO_L20N_T3_34
B4
PL_DDR3_WE
IO_L20P_T3_34
B5
PL_DDR3_ODT
IO_L22P_T3_34
A4
PL_DDR3_RESET
IO_L16N_T2_34
A10
PL_DDR3_CLK0_P
IO_L21P_T3_DQS_34
B6
PL_DDR3_CLK0_N
IO_L21N_T3_DQS_34
A5
PL_DDR3_CKE
IO_L24P_T3_34
B2

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Part 4: QSPI Flash
The AX7350B FPGA development board is equipped with a 256MBit
Quad-SPI FLASH chip, model W25Q256FVEI, which uses the 3.3V CMOS
voltage standard. Due to the non-volatile nature of QSPI FLASH, it can be used
as a boot device for the system to store the boot image of the system. These
images mainly include FPGA bit files, ARM application code, and other user
data files. The specific models and related parameters of QSPI FLASH are
shown in Table 4-1.
Position Model Capacity Factory
U10
W25Q256FVEI
32M Byte
Winbond
Table 4-1: QSPI FLASH Specification
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure 4-1
shows the QSPI Flash in the schematic.
ZYNQ QSPI FLASH
(W25Q256F)
QSPI_CS
U10
U1
BANK
500
QSPI_SCK
QSPI_D0~QSPI_D3
Figure 4-1: QSPI Flash in the schematic

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Configure chip pin assignments:
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
QSPI_SCK
PS_MIO6_500
F23
QSPI_CS
PS_MIO1_500
D26
QSPI_D0
PS_MIO2_500
E25
QSPI_D1
PS_MIO3_500
D25
QSPI_D2
PS_MIO4_500
F24
QSPI_D3
PS_MIO5_500
C26
Part 5：eMMC Flash
The AX7350B FPGA development board is equipped with a
large-capacity 8GB eMMC FLASH chip, model THGBMFG6C1LBAIL, which
supports the JEDEC e-MMC V5.0 standard HS-MMC interface with level
support of 1.8V or 3.3V. The data width of the eMMC FLASH and ZYNQ
connections is 4 bits. Due to the large capacity and non-volatile nature of
eMMC FLASH, it can be used as a large-capacity storage device for the ZYNQ
system, such as ARM applications, system files and other user data files. The
specific models and related parameters of eMMC FLASH are shown in Table
5-1.
Position Model Capacity Factory
U11
THGBMFG6C1LBAIL
8G Byte
TOSHIBA
Table 5-1: eMMC FLASH Specification
eMMC FLASH is connected to the GPIO port of the BANK501 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the SD interface. Figure 5-1 shows the
eMMC Flash in the schematic.

ZYNQ FPGA Development Board AX7350B User Manual
20 / 46
Amazon Store: https://www.amazon.com/alinx
ZYNQ eMMC
(THGBMFG6C1
LBAIL)
MMC_CCLK
U11
U1
BANK
501
MMC_CMD
MMC_DAT0~MMC_DAT3
Figure 5-1: eMMC Flash in the Schematic
Pin Assignment of eMMC Flash
Signal Name
ZYNQ Pin Name
ZYNQ Pin Number
MMC_CCLK
PS_MIO48_501
B21
MMC_CMD
PS_MIO47_501
B19
MMC_D0
PS_MIO46_501
E17
MMC_D1
PS_MIO49_501
A18
MMC_D2
PS_MIO50_501
B22
MMC_D3
PS_MIO51_501
B20
Part 6: Clock Configuration
The AX7350B FPGA development board provides a single-ended active
clock for the PS system and the PL logic, allowing the PS system and PL logic
to work independently.
PS system clock source
The ZYNQ chip provides a 33.333MHz clock input to the PS section via
the X4 crystal on the development board. The input of the clock is connected to
the pin of the PS_CLK_500 of the BANK500 of the ZYNQ chip. The schematic